CN102034440B - Gate driver and method of operation thereof - Google Patents

Abstract

The invention discloses a gate driver applied to a liquid crystal display device. The gate driver includes a plurality of channels and a chamfering control module. Each of the plurality of sets of channels includes a plurality of channels. The chamfering control module comprises a plurality of chamfering control units which are respectively connected and correspond to the plurality of groups of channels. If a shift register signal received by the chamfering control module corresponds to a channel and the channel belongs to one of the plurality of groups of channels, the chamfering control module starts a chamfering control unit corresponding to the group of channels according to the shift register signal, so that a high-potential power supply signal input to the channel starts to discharge and has a chamfered waveform.

Description

Gate driver and method of operation thereof

technical field

The present invention relates to a display device, in particular to a gate driver of a liquid crystal display (LCD display) and an operating method thereof.

Background technique

In recent years, due to the continuous development of technology related to image display, various new types of display devices appearing on the market gradually replace traditional cathode ray tube (CRT) displays. Among them, the liquid crystal display device (LCD) is widely favored by general consumers due to its advantages of power saving and space-saving, and thus has become the mainstream in the display market.

Please refer to FIG. 1 . FIG. 1 shows a schematic diagram of the operation of a power management chip and a gate driver of a conventional liquid crystal display device. As shown in FIG. 1 , a power management chip 1 traditionally used in a liquid crystal display device mainly includes two parts: a boost regulator (boostregulator) 10 and a clipping wave generator (gate pulse modulation switch, gate pulse modulation switch) 12. Wherein, the boost regulator 10 is used to boost the low-voltage input power VIN to a relatively high-voltage analog main power AVDD. The analog main power supply AVDD is used to provide the power required by the source driver of the liquid crystal display device, the Gamma reference voltage buffer, the first charge pump 2 and the second charge pump 3 . As for the first charge pump 2 and the second charge pump 3 , they will respectively generate a high-level output power VGH and a low-level output power VGL to provide to each gate driver 5 .

Generally speaking, after the signal is transmitted through the scanning lines of the liquid crystal display device, the waveform of the signal will be deformed due to the influence of parasitic resistance and parasitic capacitance delay, resulting in different signals of the gate driver 5 at the front end and the end. waveform, thus causing the screen displayed by the liquid crystal display device to flicker. In order to improve the picture flickering phenomenon, the high-level output power VGH output by the first charge pump 2 is not directly provided to the gate driver 5, but first passed through the clipping wave generator 12 of the power management chip 1 to clip The corner control signal YVC is used as a reference to perform chamfering processing on the high-level output power VGH to generate a chamfered output power signal VGHM, and then output the chamfered output power signal VGHM to each gate driver 5 .

Please refer to FIG. 2 , which shows an example of the clipping wave generator 12 of the conventional power management chip 1 . As shown in FIG. 2 , the clipping wave generator 12 uses two PMOSs P1 and P2 as switches and the discharge node RE is externally connected to the discharge resistor R1 . When the chamfer control signal YVC is at a high level, the reverse signal YVC_N of the chamfer control signal YVC is at a low level. At this time, the switch P1 will be turned on and the switch P2 will be closed, so the chamfer output power signal VGHM will be charged to the high-voltage potential VGH; when the angle-cutting control signal YVC is at a low level, the reverse signal YVC_N of the angle-cutting control signal YVC is at a high level, at this time, the switch P1 will be closed and the switch P2 will be is turned on, so the chamfer output power signal VGHM will use the grounded discharge resistor R1 to start discharging from the high voltage potential VGH.

Although the above method can improve the picture flicker phenomenon encountered by the liquid crystal display device, it also causes other problems that are difficult to overcome. Please refer to FIG. 3 , which shows a timing diagram of the operation of the conventional chamfered wave generator 12 . As shown in FIG. 3 , it is assumed that the high voltage potential VGH is 30 volts (V), and the voltage at the bottom of the chamfered corner is 10V. During the first time interval t1, the switch P1 is turned off and the switch P2 is turned on, and the chamfered output power signal VGHM starts to discharge the discharge node RE to form a chamfered waveform.

Then, when the time enters the second time interval t2, the switch P1 is switched from the original closed state to the open state and the switch P2 is switched from the open state to the closed state. Since the resistance of the general switches P1 and P2 is about 15 ohms or more Therefore, a surge current will be generated at the moment when the switch P1 is switched from off to on, and its peak value is about (30V-10V)/15Ω=1.3A.

It is worth noting that as the size of the panel of the liquid crystal display device continues to increase, the number of channels of the gate driver will also increase, so that the load capacitance of the chamfered output power signal VGHM will become larger, resulting in a delay in the moment when the switch P1 is turned on. The duration of the formed surge current also becomes longer. On the other hand, the high-voltage potential VGH of the gate driver will also increase as the size of the panel increases. When the voltage at the bottom of the chamfer remains unchanged, the peak value of the surge current will also increase, thus causing the gate driver and Damage to its packaging circuit. In addition, in order to integrate the step-up regulator 10 and the clipping wave generator 12 with different voltage processing in the traditional power management chip 1 , it must spend a lot of extra design cost, which is quite inconvenient.

Therefore, the present invention proposes a gate driver applied to a liquid crystal display device and an operation method thereof to solve the above problems.

Contents of the invention

The first embodiment according to the present invention is a gate driver. The gate driver is applied to a liquid crystal display device, and the gate driver includes multiple sets of channels and a chamfering control module. Each set of channels in the plurality of sets of channels includes a plurality of channels. The chamfering control module includes a plurality of chamfering control units, respectively connected and corresponding to the multiple groups of channels. If a shift temporary storage signal received by the chamfering control module corresponds to a channel, and the channel belongs to a group of channels in the multiple groups of channels, the chamfering control module starts the corresponding channel according to the shift temporary storage signal A chamfer control unit in the group of channels, so that a high-potential power signal input to the channel by the chamfer control unit starts to discharge to have a chamfered waveform.

In this specific embodiment, the gate driver further includes: a shift register module, configured to generate a plurality of shift register signals including the shift register signal, and the plurality of shift register signals corresponding to the plurality of channels respectively.

In this specific embodiment, the gate driver further includes: a first charge pump, used to receive a low-voltage power supply and generate the high-potential power supply signal according to the low-voltage power supply; and a second charge pump, used to receive the low-voltage power supply and A low potential power supply signal is generated based on the low voltage power supply.

Preferably, in the gate driver, the liquid crystal display device includes a power management chip connected to the first charge pump and the second charge pump for providing the low-voltage power supply to the first charge pump and the second charge pump Pump.

In this specific embodiment, in the gate driver, the corner-cutting control module further includes: a corner-cutting logic controller, which is used to determine that the channel corresponding to the shift register signal belongs to the group of the multiple groups of channels channel, and start the chamfering control unit corresponding to the group of channels according to the above judgment result.

In this particular embodiment, in the gate driver, the active switch of the chamfer control unit is connected to the channels of the set of channels corresponding to the chamfer control unit.

In this specific embodiment, in the gate driver, the chamfering control unit further includes a discharge node and a discharge path between the discharge node and ground, and when the active switch is turned on, the high potential power signal passes through the The discharge node and the discharge path start to discharge.

Preferably, in the gate driver, the chamfer control unit further includes a discharge resistor, the discharge resistor is located in the discharge path, and the discharge resistor can be used to adjust the chamfer depth of the waveform of the high potential power signal.

In this specific embodiment, in the gate driver, the chamfering control signal is based on the frequency of the liquid crystal display device.

In this specific embodiment, the gate driver activates or deactivates the corner-cutting control module according to the corner-cutting function start signal.

In this specific embodiment, the gate driver utilizes the shift register signal to control its partition chamfering function.

The second specific embodiment according to the present invention is also a gate driver. The difference from the gate driver in the first specific embodiment is that the gate driver in this embodiment is designed to match the duty cycle of the frequency signal of the system to the duty cycle of the chamfering control signal, so The original chamfering control signal can be directly replaced by the frequency signal of the system to further simplify the design of the panel system.

A third embodiment of the present invention is a method for operating a gate driver. The gate driver is applied to a liquid crystal display device. The gate driver includes multiple sets of channels and a corner-cutting control module. Each set of channels in the multiple sets of channels includes multiple channels. The corner-cutting control module includes multiple corner-cutting control modules. unit, the plurality of chamfering control units respectively correspond to the plurality of groups of channels.

The operation method of the gate driver includes the following steps: firstly, the chamfering control module receives a shift register signal. Next, it is determined that the channel corresponding to the shift register signal belongs to a group of channels in the plurality of groups of channels. After that, start a chamfering control unit corresponding to the group of channels among the plurality of chamfering control units according to the above judgment result. Then, the corner-cutting control unit turns on an active switch of the corner-cutting control unit according to the received corner-cutting control signal. Finally, a high-potential power signal input to the channel by the chamfering control unit starts to discharge to have a chamfered waveform.

In the operation method, the gate driver further includes a first charge pump and a second charge pump, the first charge pump receives a low-voltage power supply and generates the high-potential power supply signal according to the low-voltage power supply, and the second charge pump receives the low-voltage power supply power supply and generates a low-potential power supply signal based on the low-voltage power supply.

Preferably, the liquid crystal display device includes a power management chip for providing the low-voltage power supply to the first charge pump and the second charge pump.

In the operation method, the chamfering control unit further includes a discharge node and a discharge path between the discharge node and ground, and when the active switch is turned on, the high potential power signal starts through the discharge node and the discharge path to discharge.

Preferably, the chamfer control unit further includes a discharge resistor located in the discharge path, and the discharge resistor can be used to adjust the chamfer depth of the waveform of the high-potential power signal.

In the operation method, the clipping control signal is based on the frequency of the liquid crystal display device.

In the operation method, the chamfering control signal can be replaced by the frequency signal of the liquid crystal display device.

Preferably, the frequency signal is properly designed to have the same duty cycle as the angle-cutting control signal, so it can be used to replace the angle-cutting control signal.

In this operation method, the shift register signal is used to control the function of cutting corners of the partitions.

The advantages and spirit of the present invention can be further understood through the following detailed description of the invention and the accompanying drawings.

Description of drawings

FIG. 1 is a schematic diagram illustrating the operation of a power management chip and a gate driver of a conventional liquid crystal display device.

FIG. 2 shows an example of a clipping wave generator of a conventional power management chip.

FIG. 3 shows a timing diagram of the operation of a conventional chamfered wave generator.

FIG. 4 shows a functional block diagram of a gate driver according to a first embodiment of the present invention.

Fig. 5 shows a timing diagram of the operation of the first chamfering control unit and the second chamfering control unit in the chamfering control module in Fig. 4 .

Fig. 6 A shows the schematic diagram corresponding to the first group of passages and the second group of passages of the first chamfering control unit and the second chamfering control unit in the chamfering control module in Fig. 4; Fig. 6B shows corresponding to A schematic diagram of the operation mode of the second channel in the first group of channels in FIG. 6A .

FIG. 7A shows a functional block diagram of a gate driver in which the discharge switch is changed to NMOS; FIG. 7B shows a schematic diagram of the operation mode corresponding to the second channel in the first group of channels in FIG. 7A .

FIG. 8A shows a functional block diagram of the gate driver in FIG. 4 further comprising a first charge pump and a second charge pump; FIG. 8B shows a functional block diagram of a gate driver in which a frequency signal is used to replace the clipping control signal.

FIG. 9 shows a timing diagram of the operation of the first chamfering control unit and the second chamfering control unit in the chamfering control module in FIG. 8B .

FIG. 10 shows a flowchart of a gate driver operating method according to a third specific embodiment of the present invention.

Detailed ways

The first embodiment according to the present invention is a gate driver. In this embodiment, the gate driver is applied to a liquid crystal display device, but not limited thereto. Same as the prior art, the liquid crystal display device also includes a power management chip and a gate driver. However, it is worth noting that since the gate driver generates the chamfered output power to each gate in the present invention, when designing a power management chip, the chip designer only needs to consider the processing applicable to the boost regulator (such as 20V voltage processing), so the process and cost of chip design can be greatly simplified, and the flexibility of processing options can also be increased.

In addition, more importantly, the present invention divides the chamfering control module in the gate driver into multiple chamfering control units through the concept of partition control, and controls different groups of channels respectively, so as to reduce the load capacitance of the chamfering control module, and because The chamfering control module is built in the gate driver, so it can effectively avoid the disadvantage of IR voltage drop caused by the wire loading phenomenon in the traditional panel system.

Please refer to FIG. 4 , which shows a functional block diagram of a gate driver according to a first embodiment of the present invention. As shown in FIG. 4 , the gate driver 4 includes a shift register module 41 , an output enable control module 42 , a level offset module 43 , an output buffer module 44 , and a chamfer control module 45 . Wherein, the shift register module 41 is connected to the output enable control module 42 ; the output enable control module 42 is connected to the level offset module 43 ; the level offset module 43 is connected to the output buffer module 44 .

In this embodiment, the gate driver 4 includes n channels in total, and the n channels are sequentially divided into m groups of channels, wherein each group of channels includes r channels, that is, the first group of channels includes the first channel ~ The rth channel; the second group of channels includes the (r+1)th channel to the 2rth channel; and so on for the rest. n, m and r are all positive integers. For example, if n=400 and m=4, then r=400/4=100, but not limited thereto. As shown in Figure 4, the output buffer module 44 includes a first output buffer unit 441 to an mth output buffer unit 44m, corresponding to the first group of channels to the m group of channels respectively; the chamfering control module 45 includes the first chamfering control unit 451 to the m-th chamfering control unit 45m, thus respectively corresponding to the first group of channels to the m-th group of channels through the first output buffer unit 441 to the m-th output buffer unit 44m.

As shown in FIG. 4 , the signals received by the first chamfering control unit 451 include: the first shifted temporary storage signal S(1) to the rth shifted temporary storage signal S corresponding to the first channel to the rth channel respectively (r), the corner-cutting function activation signal GS_Ctrl, the corner-cutting control signal YVC, and the high-voltage potential VGG that control whether the first corner-cutting control unit 451 is turned on or not, and the first corner-cutting control unit 451 will pass through the first output buffer unit 441 Outputting the first high voltage potential VGH1 to its corresponding first group of channels. As for the second chamfering control unit 452 to the mth chamfering control unit 45m, it can be deduced in the same way, which will not be repeated here.

It should be noted that since the output enabling control module 42 , the level shifting module 43 and the output buffering module 44 included in the gate driver 4 are already known modules, details are not repeated here. Next, the modules such as the most important shift temporary storage module 41 and the chamfering control module 45 of the present invention and their functions will be introduced in detail.

Please refer to Fig. 5, Fig. 6A and Fig. 6B at the same time, Fig. 5 has shown the timing chart that the first chamfer control unit 451 and the second chamfer control unit 452 in the chamfer control module 45 operate; The first chamfer control unit 451 and the second chamfer control unit 452 in the angle control module 45 correspond to the schematic diagrams of the first group of passages and the second group of passages respectively; FIG. 6B shows the first group corresponding to FIG. 6A Schematic diagram of the mode of operation of the second channel in the channel.

As shown in the figure, at time T1, the first shift temporary storage signal S (1) received by the shift temporary storage module 45 from the shift temporary storage module 41 by the chamfering control module 45 changes from a low level to a high level, and the chamfering control module 45 changes from a low level to a high level. The module 45 will judge that the first channel corresponding to the first shift register signal S(1) belongs to the first group of channels, and therefore, the chamfering control module 45 will start the first chamfering control corresponding to the first group of channels Unit 451. When the first corner cutting control unit 451 is activated, the first corner cutting logic controller 4510 of the first corner cutting control unit 451 will respectively turn on the switch PS1 and turn off the switch PR1, so as to output the first output through the first output buffer unit 441. High voltage potential VGH1 to the first group of channels.

Then, when the time begins to enter the third time interval t3, because the angle-cutting control signal YVC just changes from a high level to a low level, at this time, the first angle-cutting logic controller 4510 will The switch PS1 is turned off and the switch PR1 is turned on, respectively.

As shown in Figure 5, when the switch PR1 is turned on, the corresponding gate output G1 of the first channel will start to discharge through the discharge node RE to obtain the first output power signal G(1) with a chamfered waveform until the output When the enable signal OE changes from a high level to a low level, the first output power signal G( 1 ) starts to be at the low voltage potential VGL. Actually, the discharge node RE can be connected to a discharge path (discharging path) grounded through a discharge resistor, but not limited thereto. Similarly, next, the gate output G2 of the second channel to the gate output Gr of the rth channel will also be respectively discharged during the third time interval t3 to obtain the second output power signal G(2) to the rth channel with a clipping waveform. r outputs the power signal G(r).

It should be noted that the time T2 shown in FIG. 5 is exactly at the junction of the rth output power signal G(r) and the (r+1)th output power signal G(r+1). The rth channel corresponding to the rth output power signal G(r) belongs to the first group of channels and is controlled by the first chamfering control unit 451, but the (r+1)th output power signal G(r+1) The corresponding (r+1)th channel belongs to the second group of channels and is controlled by the second chamfering control unit 452, that is, the rth channel and the (r+1)th channel belong to different chamfering control units. Therefore, The chamfering control module 45 will shift the temporary register signal S(r) or the (r+1)th shift register signal S(r+1) corresponding to the rth channel and the (r+1)th channel ) to switch the chamfer control unit, that is, turn off the first chamfer control unit 451 and turn on the second chamfer control unit 452 at time T2. As for the operation of the second chamfering control unit 452 is similar to that of the first chamfering control unit 451 , it will not be repeated here. The present invention mainly discloses a method for controlling the corner cutting function of a partition by using a shift register signal, but is not limited thereto.

Moreover, although the switch PR1 shown in FIG. 6A adopts a PMOS component, however, in practical applications, the discharge switch can also be changed to an NMOS component, such as the switch NR1 shown in FIG. 7A . As for FIG. 7B , it shows a schematic diagram corresponding to the operation mode of the second channel G2 in the first group of channels in FIG. 7A .

In addition, it can be seen from FIG. 8A that the gate driver 4 only needs to be provided with a low-voltage power supply VDD from the outside, and can self-boost the voltage through its internal first charge pump 46 and second charge pump 47 to form the output high-voltage potential VGG and low-voltage potential VGL. , so a chip design with a single supply can be achieved, which is quite convenient and saves design cost for panel system design.

The second specific embodiment according to the present invention is also a gate driver. Please refer to FIG. 8B , which shows a functional block diagram of the gate driver. Comparing the gate driver shown in FIG. 8B with that shown in FIG. 4, it can be seen that the difference between the two is that in order to further simplify the design of the panel system and reduce the types of signals, FIG. 8B replaces the frequency signal CLK in FIG. 4 with the system frequency signal CLK Chamfering control signal YVC. In fact, as long as the duty cycle of the frequency signal CLK of the system is properly designed to make it consistent with the duty cycle of the chamfering control signal YVC, the frequency signal CLK of the system can be directly used as the duty cycle of the chamfering control signal. use. As for FIG. 9 , it shows a timing diagram of the operation of the chamfering control module 45 in FIG. 8B . Comparing FIG. 9 with FIG. 5 , it can be seen that the difference between the two is only that the system frequency signal CLK is used in FIG. 9 to replace the clipping control signal YVC in FIG. 5 , so no further description is given.

To sum up, the gate driver of this embodiment not only has the advantages of avoiding the damage caused by the surge current and the chip design of a single power supply, but also can replace the angle-cutting control signal with the original frequency signal CLK of the system Therefore, the YVC can further simplify the design of the panel system, so as to enhance the market competitiveness of the liquid crystal display device using the gate driver.

A third embodiment of the present invention is a gate driver operating method. In this embodiment, the gate driver is arranged in a liquid crystal display device, the gate driver includes multiple sets of channels and a chamfering control module, each set of channels in the multiple sets of channels includes a plurality of channels, and the chamfering The control module includes multiple chamfering control units, and the multiple chamfering control units respectively correspond to the multiple groups of channels.

Please refer to FIG. 10 , which shows a flow chart of a gate driver operating method according to a third embodiment of the present invention. As shown in FIG. 10 , firstly, the method executes step S10 , the chamfering control module receives a shift register signal. Next, the method executes step S12 to determine that the channel corresponding to the shift register signal belongs to a group of channels in the plurality of groups of channels.

In practical application, as long as the duty cycle of the frequency signal of the system is properly designed to make it consistent with the duty cycle of the chamfer control signal, the original chamfer control signal can be directly replaced by the system frequency signal. Next, the method executes step S14 , starting a chamfering control unit corresponding to the group of channels among the plurality of chamfering control units according to the above judgment result. Then, in step S16, the chamfering control unit turns on an active switch of the chamfering control unit according to a received chamfering control signal. Actually, the active switch can be a PMOS component or an NMOS component. Finally, in step S18, the high-potential power signal input to the channel by the chamfering control unit starts to discharge to have a chamfered waveform. As for the detailed operation mode of the gate driver, reference may be made to the description of the above-mentioned first embodiment and related drawings, and details are not repeated here.

Compared with the prior art, the gate driver according to the present invention can effectively avoid the damage to the gate driver caused by the surge current formed when the traditional power management chip generates clipping waves, and also has the advantages of using a single power supply, reducing signal types and simplify the complexity of the original power management chip design. More importantly, the present invention divides the chamfer control module in the gate driver into multiple chamfer control units through the concept of partition control to reduce the load capacitance of the chamfer control module, and since the chamfer control module is built into the gate Pole driver, so it can effectively avoid the disadvantage of IR voltage drop caused by wire load phenomenon in traditional panel systems. Therefore, the gate driver of the present invention can greatly simplify the design process and cost of the overall panel display system, so as to enhance the market competitiveness of the panel display system using the gate driver.

Through the above detailed description of the preferred specific embodiments, it is hoped that the features and spirit of the present invention can be described more clearly, and the protection scope of the present invention is not limited by the preferred specific embodiments disclosed above. On the contrary, the intention is to cover various changes and equivalent arrangements within the protection scope of the patent application for this invention.

Explanation of main component symbols

S10～S18: Process steps G1～Gn: Channel gate

1: Power control chip 10: Boost regulator

12: Clipping wave generator 2, 46: The first charge pump

4: Gate driver 3, 47: Second charge pump

PR1, PS1, NR1: switch R1, R: resistor

RE: discharge node t1: first time interval

t2: second time interval T1, T2: time

t3: The third time interval 41: Shift temporary storage module

43: Level offset module 42: Output enable control module

44: Output buffer module 45: Chamfering control module

441～44m: output buffer unit 451～45m: chamfering control unit

DIO: input signal DOI: output signal

452: Active switch CLK: Frequency signal

OE: output enable signal YVC: chamfering control signal

VGG, VGH1～VGHm: high voltage potential

VGL: low voltage potential

VDD: low voltage power supply

G(1)～G(n): output power signal

S(1)～S(n): shift temporary storage signal

4510, 4520: chamfer logic controller.

Claims (22)

1. a gate drivers is arranged in the liquid crystal indicator, and said gate drivers comprises:

Many group passages, and each the group passage in said many group passages comprises a plurality of passages; And

The top rake control module comprises:

A plurality of top rake control modules; Connect respectively and corresponding to said many group passages; If the received shift register signal of said top rake control module is corresponding to a passage; And said passage belongs to one group of passage in said many group passages; Said top rake control module is promptly according to the top rake control module corresponding to said group of passage in the said a plurality of top rake control modules of said shift register signal enabling, and said top rake control module is opened the active switch of said top rake control module according to the top rake control signal that receives, and the high potential power signal that makes said top rake control module input to said passage thus begins to discharge and has the waveform of top rake.

2. gate drivers according to claim 1 further comprises:

The shift register module comprise said shift register signal at interior a plurality of shift register signals in order to generation, and said a plurality of shift register signal corresponds respectively to said a plurality of passage.

3. gate drivers according to claim 1 further comprises:

First charge pump is in order to receive low-tension supply and to produce said high potential power signal according to said low-tension supply; And

Second charge pump is in order to receive said low-tension supply and to produce the low potential power source signal according to said low-tension supply.

4. gate drivers according to claim 3; Wherein said liquid crystal indicator comprises power management chip; Be connected to said first charge pump and said second charge pump, in order to provide said low-tension supply to said first charge pump and said second charge pump.

5. gate drivers according to claim 1, wherein said top rake control module further comprises:

The top rake logic controller belongs to said group of passage in said many group passages in order to judge the pairing said passage of said shift register signal, and starts the said top rake control module corresponding to said group of passage according to above-mentioned judged result.

6. gate drivers according to claim 1, the said active switch of wherein said top rake control module is connected to corresponding to the said a plurality of passages in the said group of passage of said top rake control module.

7. gate drivers according to claim 1; Wherein said top rake control module further comprises discharge node and the discharge path between said discharge node and ground connection; When said active switch open, said high potential power signal begins to discharge through said discharge node and said discharge path.

8. gate drivers according to claim 7; Wherein said top rake control module further comprises discharge resistance; Said discharge resistance is positioned at said discharge path, and said discharge resistance can be in order to the top rake degree of depth of the waveform of adjusting said high potential power signal.

9. gate drivers according to claim 1, wherein said top rake control signal is a benchmark with the frequency of said liquid crystal indicator.

10. gate drivers according to claim 1, wherein said top rake control signal can use the frequency signal of said liquid crystal indicator to replace.

11. gate drivers according to claim 10, wherein said frequency signal is through fitting

Has identical work frequency (dutycycle) when design with said top rake control signal, so can be in order to replace said top rake control signal.

12. gate drivers according to claim 1 is according to top rake function on signal enabling or close said top rake control module.

13. gate drivers according to claim 1 utilizes said shift register signal to control its subregion top rake function.

14. the method for an operation gate driver; Said gate drivers is arranged in the liquid crystal indicator; Said gate drivers comprises many group passages and top rake control module, and each the group passage in said many group passages comprises a plurality of passages, and said top rake control module comprises a plurality of top rake control modules; Said a plurality of top rake control module corresponds respectively to said many group passages, and said method comprises the following step:

Said top rake control module receives the shift register signal;

Judge that the pairing said passage of said shift register signal belongs to one group of passage in said many group passages;

Start the top rake control module in said a plurality of top rake control module according to above-mentioned judged result corresponding to said group of passage; And

Said top rake control module is opened the active switch of said top rake control module according to the top rake control signal that receives, and the high potential power signal that makes said top rake control module input to said passage thus begins to discharge and has the waveform of top rake.

15. method according to claim 14; Wherein said gate drivers further comprises first charge pump and second charge pump; Said first charge pump receives low-tension supply and produces said high potential power signal according to said low-tension supply, and said second charge pump receives said low-tension supply and produces the low potential power source signal according to said low-tension supply.

16. method according to claim 15, wherein said liquid crystal indicator comprises power management chip, in order to provide said low-tension supply to said first charge pump and said second charge pump.

17. method according to claim 14; Wherein said top rake control module further comprises discharge node and the discharge path between said discharge node and ground connection; When said active switch open, said high potential power signal begins to discharge through said discharge node and said discharge path.

18. method according to claim 17, wherein said top rake control module further comprises discharge resistance, and said discharge resistance is positioned at said discharge path, and said discharge resistance can be in order to the top rake degree of depth of the waveform of adjusting said high potential power signal.

19. method according to claim 14, wherein said top rake control signal is a benchmark with the frequency of said liquid crystal indicator.

20. method according to claim 14, wherein said top rake control signal can use the frequency signal of said liquid crystal indicator to replace.

21. method according to claim 20, wherein said frequency signal have identical work frequency through suitably designing with said top rake control signal, so can be in order to replace said top rake control signal.

22. method according to claim 14 utilizes said shift register signal to control subregion top rake function.

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