CN102025350B - Pulse attenuation loop and delay measuring device - Google Patents
Pulse attenuation loop and delay measuring device Download PDFInfo
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- CN102025350B CN102025350B CN 200910195976 CN200910195976A CN102025350B CN 102025350 B CN102025350 B CN 102025350B CN 200910195976 CN200910195976 CN 200910195976 CN 200910195976 A CN200910195976 A CN 200910195976A CN 102025350 B CN102025350 B CN 102025350B
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Abstract
The invention provides a pulse attenuation loop and a delay measuring device. The pulse attenuation loop comprises a pulse attenuation chain and a charge pump, wherein the pulse attenuation chain is used for carrying out pulse attenuation on an input signal and comprises a plurality of pulse attenuation units which are serially connected, and the total quantity of the pulse attenuation units is greater than the quantity of pulse attenuation units attenuating the input signal to zero; the charge pump is used for adjusting the pulse attenuation width of each level of pulse attenuation unit of the pulse attenuation chain. The input signal is input into the pulse attenuation chain, output ends of a part of the pulse attenuation units of the pulse attenuation chain are connected with an input end of the charge pump, and an output end of the charge pump is connected with an input end of each level of pulse attenuation unit of the pulse attenuation chain to form negative feedback. The pulse attenuation loop and the delay measuring device of the invention can eliminate the influence of signal crosstalk on delay accuracy and can accurately and stably measure picosecond level delay.
Description
Technical field
The present invention relates to technical field of semiconductors, relate in particular to a kind of impulse attenuation loop and the delay measuring device that comprises described impulse attenuation loop.
Background technology
Delay locked loop (DLL, Delay Locked Loop) is widely used in high speed semiconductor memory, serial digital signal receiving circuit, the A/D change-over circuit etc.At present, the operating frequency of DLL is generally tens megahertzes to the hundreds of megahertz.For example, when the operating frequency of DLL was 400MHz, the delay of design was 1% of the DLL work period, also i.e. delay=2.5ns*1%=25ps.
In the prior art, the delay of measurement picosecond (＜25ps) can adopt two phase-locked loops (PLL, Phase Locked Loop) to measure, the frequency of described two phase-locked loops is different, between two phase-locked loops, set in advance certain delay, and the high phase-locked loop of frequency lags behind; By counter the default clock cycle is counted, when the waveform of the low phase-locked loop of the high phase-locked loop of frequency and frequency overlaps, during the delay disappearance that also namely sets in advance, can by the count value of counter, calculate delay to be measured.Because delay to be measured is very little, for guaranteeing certainty of measurement, the output frequency of two phase-locked loops should approach.For example, the frequency of a phase-locked loop is 200MHz, and the frequency of another phase-locked loop is 198MHz.But in this technical scheme, the frequency of two phase-locked loops is extremely approaching, because coupling is crosstalked very serious, frequency signal easily produces distortion between the frequency signal that extremely approaches.
In addition, application number provides a kind of quantization delay method of measurement and measurement mechanism of delay for the Chinese patent application of 97108677.X, utilize the signal transmission to need time and the fast phenomenon of signaling rate, adopting a plurality of delay unit devices to be connected to form time delay chain quantizes, the output of each delay unit connects respectively corresponding latch, and is connected with single-chip microcomputer by register.During test, during signal process transmission unit, the variation of its state reflects the numerical value of tested delay.
The patent No. provides another kind of method with two-stage cascade delay line transfer delay for the Chinese patent of ZL200510011713.9.This method of measurement is measured whole clock periodicity in the delay to be measured based on pulse counting method; Measure the delay of the not enough whole clock cycle part in the delay to be measured with first order delay line; To be delivered to second level delay line less than the delay of first order delay line resolution, and do further segmentation and measure; Calculate delay to be measured according to above measurement result.
In the measurement mechanism or method of prior art, do not consider that signal disturbs postponing the impact of precision.Clock signal, data-signal, control signal etc. are crosstalked mutually, cause postponing precision unstable, can not satisfy the high-precision requirement that picosecond postpones.
Summary of the invention
The problem that the present invention solves provides a kind of impulse attenuation loop and delay measuring device, and the energy eliminates signal crosstalk is on postponing the impact of precision, the delay of measuring accurately and stably picosecond.
For addressing the above problem, the invention provides a kind of impulse attenuation loop, comprise: the impulse attenuation chain, be used for input signal is carried out impulse attenuation, described impulse attenuation chain comprises the impulse attenuation unit of some grades of series connection, and the total amount of described impulse attenuation unit is greater than the quantity that with described attenuated input signal is zero impulse attenuation unit; Charge pump is for the impulse attenuation width of the impulse attenuations at different levels unit of regulating described impulse attenuation chain; The output of the partial pulse attenuation units of described at least impulse attenuation chain links to each other with the input of described charge pump, and described electric charge delivery side of pump links to each other with the input of the impulse attenuations at different levels unit of described impulse attenuation chain.
The present invention also provides a kind of delay measuring device, comprising: the impulse attenuation loop, be used for the second frequency signal from the outside is carried out impulse attenuation, and export the voltage control signal corresponding with the impulse attenuation width; Postpone detection module, reception is from the first input signal, the second input signal, the first frequency signal of outside, the cycle of described first frequency signal is identical with the pulse duration of described second frequency signal, and described delay detection module is exported the first count value, the first inhibit signal and the second inhibit signal according to described first frequency signal; Wherein, the pulse duration of described the first inhibit signal and described the first input signal, time difference between the described first frequency signal is corresponding, the pulse duration of described the second inhibit signal and described the second input signal, time difference between the described first frequency signal is corresponding, described the first inhibit signal, delay between the second inhibit signal and described the first input signal, delay between the second input signal is identical, and described the first count value is the maximum integer numerical value doubly of included first frequency signal period of the delay between described the first inhibit signal trailing edge and the second inhibit signal trailing edge, be zero, perhaps be zero with the numerical value of described maximum integer times between any one integer; The pulse duration attenuation module, receive the described voltage control signal of described first inhibit signal of described delay detection module output, described the second inhibit signal and the output of described impulse attenuation loop, according to described voltage control signal described the first inhibit signal and described the second inhibit signal are decayed the output attenuatoin result; The Delay computing module receives the attenuation results that described the first count value and described pulse duration attenuation module are exported, and calculates the delay between described the first input signal and the second input signal.
Described impulse attenuation loop comprises: the first impulse attenuation chain, be used for the second frequency signal is carried out impulse attenuation, described impulse attenuation chain comprises the impulse attenuation unit of some grades of series connection, and the total amount of the impulse attenuation unit of the first impulse attenuation chain is greater than the quantity that with described second frequency signal attenuation is zero impulse attenuation unit; Charge pump is for the impulse attenuation width of the impulse attenuations at different levels unit of regulating described the first impulse attenuation chain; The output of the partial pulse attenuation units of described at least the first impulse attenuation chain links to each other with the input of described charge pump, and described electric charge delivery side of pump links to each other with the input of every grade of impulse attenuation unit of described the first impulse attenuation chain.
Described delay detection module comprises counter, is used for recording described the first count value.
The pulse duration of described the first inhibit signal is the time interval of the rising edge of a pulse of the rising edge of a pulse of the first input signal and adjacent first frequency signal; The pulse duration of described the second inhibit signal is the time interval of the rising edge of a pulse of the rising edge of pulse of the second input signal and adjacent first frequency signal; The maximum integer that described the first count value is first frequency signal period numerical value doubly.
The pulse duration of described the first inhibit signal is the time interval of the rising edge of a pulse of the rising edge of a pulse of the first input signal and the first frequency signal adjacent with the rising edge of a pulse of the second input signal; The pulse duration of described the second inhibit signal is the time interval of the rising edge of a pulse of the rising edge of a pulse of the second input signal and adjacent first frequency signal; Described the first count value is zero.
Described pulse duration attenuation module comprises: the second impulse attenuation chain and the 3rd impulse attenuation chain, carry out impulse attenuation to described the first inhibit signal and the second inhibit signal respectively; Described the second impulse attenuation chain, the 3rd impulse attenuation chain include the impulse attenuation unit of some grades of series connection, and the total amount of described the second impulse attenuation chain and the attenuation units of the 3rd impulse attenuation chain is identical with the total amount of the attenuation units of described the first impulse attenuation chain; The attenuation results of described pulse duration attenuation module output is the Output rusults of every grade of attenuation units of the second impulse attenuation chain and the 3rd impulse attenuation chain; The electric charge delivery side of pump of described impulse attenuation loop links to each other with the input of described the second impulse attenuation chain and every grade of attenuation units of the 3rd impulse attenuation chain, and described the second impulse attenuation chain is identical with the width of the impulse attenuation of every grade of attenuation units of described the first impulse attenuation chain of the width of the impulse attenuation of every grade of attenuation units of the 3rd impulse attenuation chain.
A kind of delay measuring device is characterized in that, comprising: the impulse attenuation loop, be used for the second frequency signal from the outside is carried out impulse attenuation, and export the voltage control signal corresponding with the impulse attenuation width; Postpone detection module, receive the first input signal, the second input signal from the outside, the output delay signal, the pulse duration of described inhibit signal is identical with delay width between described the first input signal and the second input signal; The pulse duration attenuation module receives the described inhibit signal of described delay detection module output and the described voltage control signal of described impulse attenuation loop output, described inhibit signal is decayed the output attenuatoin result according to described voltage control signal; The Delay computing module receives the attenuation results that described pulse duration attenuation module is exported, and calculates the delay between described the first input signal and the second input signal.
Described impulse attenuation loop comprises: the first impulse attenuation chain, be used for described second frequency signal is carried out impulse attenuation, described the first impulse attenuation chain comprises the impulse attenuation unit of some grades of series connection, and the total amount of the impulse attenuation unit of the first impulse attenuation chain is greater than the quantity that with described second frequency signal attenuation is zero impulse attenuation unit; Charge pump is for the impulse attenuation width of the impulse attenuations at different levels unit of regulating described the first impulse attenuation chain; The output of the partial pulse attenuation units of described at least the first impulse attenuation chain links to each other with the input of described charge pump, and described electric charge delivery side of pump links to each other with the input of every grade of impulse attenuation unit of described the first impulse attenuation chain.
Described delay detection module comprises counter, is used for recording described the first count value.
Described pulse duration attenuation module comprises: the 4th impulse attenuation chain, carry out impulse attenuation to described inhibit signal; Described the 4th impulse attenuation chain comprises the impulse attenuation unit of some grades of series connection, and the total amount of the attenuation units of described the 4th impulse attenuation chain is identical with the total amount of the attenuation units of described the first impulse attenuation chain; The attenuation results of described pulse duration attenuation module output is the Output rusults of every grade of attenuation units of the 4th impulse attenuation chain; The electric charge delivery side of pump of described impulse attenuation loop links to each other with the input of every grade of attenuation units of described the 4th impulse attenuation chain, and the width of the impulse attenuation of every grade of attenuation units of described pulse duration attenuation module is identical with the width of the impulse attenuation of every grade of attenuation units of described the first impulse attenuation chain.
Described Delay computing module comprises pulse detection unit and at least one register, the output of the impulse attenuations at different levels unit of the impulse attenuation chain that each of described register and described pulse duration attenuation module comprise is corresponding, the output of described every grade of impulse attenuation unit, the corresponding positions of set register are detected in described pulse detection unit.
Compared with prior art, impulse attenuation loop of the present invention is sent to charge pump with the output of the partial pulse attenuation units of impulse attenuation chain, controls the impulse attenuation width of the outputs at different levels of described impulse attenuation chain by described charge pump, forms negative feedback.By negative feedback to being that the quantity of zero impulse attenuation unit locks with attenuated input signal.When signal cross-talk occured, the impulse attenuation width of the outputs at different levels of described impulse attenuation chain was adjusted in described negative feedback in real time, again realizes stable loop rapidly, to guarantee to postpone the Stability and veracity of precision.
Based on above-mentioned accurate and stable delay precision, delay measuring device of the present invention detects by postponing detection module, decay through pulse width attenuation module and to postpone between two input signals, described delay can be decomposed as required, by the Delay computing module, accurately calculate the delay between two input signals after the output signal of detection module.
Further, the included impulse attenuation loop of delay measuring device of the present invention is by the impulse attenuation element number of paired pulses decay chain and the adjustment of impulse attenuation width, and the delay precision of accurate and stable picosecond is provided.Based on above-mentioned delay precision, can measure accurately and stably the delay of picosecond.
Description of drawings
Fig. 1 is the annexation schematic diagram of delay measuring device of the present invention and external devices;
Fig. 2 is the principle schematic of delay measuring device of the present invention;
Fig. 3 is the structural representation of delay measuring device of the present invention;
Fig. 4 is the sequential chart of the impulse attenuation unit of delay measuring device of the present invention;
Fig. 5 is the structural representation of the first embodiment of delay measuring device of the present invention;
Fig. 6 is the sequential chart of the first embodiment of delay measuring device of the present invention;
Fig. 7 is the sequential chart of the second embodiment of delay measuring device of the present invention;
Fig. 8 is the sequential chart of the 3rd embodiment of delay measuring device of the present invention;
Fig. 9 is the sequential chart of the 4th embodiment of delay measuring device of the present invention;
Figure 10 is the structural representation of the 5th embodiment of delay measuring device of the present invention;
Figure 11 is the structural representation of the 6th embodiment of delay measuring device of the present invention;
Figure 12 is the structural representation of the 7th embodiment of delay measuring device of the present invention;
Figure 13 is the sequential chart of the 7th embodiment of delay measuring device of the present invention.
Embodiment
Delay measuring device of the present invention comprises the impulse attenuation loop, is that the quantity of zero impulse attenuation unit locks to the signal attenuation that inputs to described impulse attenuation loop, guarantees to postpone the accuracy of precision.Based on postponing accurately precision, other two input signals are decayed respectively, by being the quantity of zero impulse attenuation unit with described two attenuated input signals, calculate the delay between described two input signals.
Based on above-mentioned principle, below in conjunction with drawings and Examples the present invention is described in detail.
Fig. 1 is the annexation schematic diagram of delay measuring device of the present invention and external devices.As shown in Figure 1, the reference frequency signal 11 of crystal oscillator output inputs to phase-locked loop 18, after phase-locked loop 18 frequencys multiplication, generates the first frequency signal 12 with stable pulse width.Described first frequency signal 12 inputs to frequency divider 19, through frequency divider 19 frequency divisions, adjusts signal dutyfactor and pulse duration, the second frequency signal 13 behind the generation frequency division.Described second frequency signal 13, first frequency signal 12, the first input signal 15 and the second input signal 16 input to delay measuring device 20, after delayed measurement mechanism 20 detects, calculates, export the delay 17 between the first input signal 15 and the second input signal 16.
Fig. 2 is the principle schematic of delay measuring device of the present invention.See also Fig. 1 and Fig. 2, delay measuring device of the present invention comprises: impulse attenuation loop 29, according to attenuation level described second frequency signal pulse width is decayed to zero, and export the voltage control signal corresponding with the impulse attenuation width; Postpone detection module 210, according to the delay between described first frequency input the first input signal 15 and the second input signal 16; Pulse duration attenuation module 211, the pulse duration of the inhibit signal 26 of described delay detection module 210 outputs that are used for decaying; Delay computing module 212 is used for calculating the delay 17 between described the first input signal 15 and the second input signal 16.
Described the first input signal 15, the second input signal 16 and first frequency signal 12 input to and postpone detection module 210, and the delay between described the first input signal 15, the second input signal 16 is detected.The part in the integer section cycle that belongs to first frequency signal 12 in the described delay can be counted, count results exports Delay computing module 212 to as the first count value 27; Simultaneously, the corresponding output of remainder with not counting in the described delay exports pulse duration attenuation module 211 to as inhibit signal 26.Also can with 27 zero setting of the first count value, directly export the delay between the first input signal 15, the second input signal 16 to pulse duration attenuation module 211 as inhibit signal 26.
Pulse duration attenuation module 211 decays to zero according to the voltage control signal 25 that receives with described inhibit signal 26 pulsewidths.
Fig. 3 is the structural representation of delay measuring device of the present invention.See also Fig. 2 and Fig. 3, impulse attenuation loop 29 comprises the first impulse attenuation chain, is used for second frequency signal 13 is carried out impulse attenuation.Described the first impulse attenuation chain by n impulse attenuation unit U (1) ... U (N-1), U (N), U (N+1) ... U (n) is composed in series, corresponding output C
1... C
N-1, C
N, C
N+1... C
nThe total amount n of described impulse attenuation unit is greater than the quantity N that second frequency signal 13 is decayed to zero impulse attenuation unit.
Further, described impulse attenuation loop 29 also comprises charge pump 31, for the impulse attenuation width of the impulse attenuations at different levels unit of regulating described the first impulse attenuation chain.Described the first impulse attenuation chain of described second frequency signal 13 inputs, the impulse attenuations at different levels unit of described the first impulse attenuation chain carries out impulse attenuation step by step to second frequency signal 13, until second frequency signal 13 decays to zero.The impulse attenuation width of above-mentioned impulse attenuations at different levels unit is consistent.The output C of N-1 impulse attenuation unit
N-1Output C with N impulse attenuation unit
NInput to described charge pump 31.Work as C
N-1Signal is non-vanishing, C
NWhen signal is zero, belong to normal condition, charge pump 31 is failure to actuate; Work as C
N-1Signal is zero, C
NWhen signal also is zero, illustrate that the decay of the first impulse attenuation chain is too fast, the impulse attenuation width is larger, and 31 pairs of built-in capacitor discharges of charge pump reduce voltage control signal 25, thereby reduce the impulse attenuation width of impulse attenuations at different levels unit; Work as C
N-1Signal is non-vanishing, C
NWhen signal is also non-vanishing, illustrate that the first impulse attenuation chain decayed slowly, the impulse attenuation width is less, 31 pairs of built-in capacitor chargings of charge pump, and booster tension control signal 25, thus increase the impulse attenuation width of impulse attenuations at different levels unit.Described charge pump 31 is according to C
N-1And C
NSignal, to the built-in capacitance charge and discharge, regulation voltage control signal 25.By described voltage control signal 25, regulate the impulse attenuation width of impulse attenuations at different levels unit.Described charge pump 31 and the first impulse attenuation chain have formed negative feedback, thereby locking decays to second frequency signal 13 the quantity N of zero impulse attenuation unit, to generate precise and stable delay precision.
Further, described charge pump 31 also comprises low pass filter, and voltage control signal 25 is exported behind low pass filter filters out high frequency clutter.
Pulse duration attenuation module 211 comprises the second impulse attenuation chain and the 3rd impulse attenuation chain.Described the second impulse attenuation chain by n impulse attenuation unit U (1) ... U (N-1), U (N), U (N+1) ... U (n) is composed in series, corresponding output A
1... A
N-1, A
N, A
N+1... A
n, be used for the first inhibit signal 261 that decay postpones detection module 210; Described the 3rd impulse attenuation chain also by n impulse attenuation unit U (1) ... U (N-1), U (N), U (N+1) ... U (n) is composed in series, corresponding output B
1... B
N-1, B
N, B
N+1... B
n, be used for the second inhibit signal 262 that decay postpones detection module 210.
The first input signal 15, the second input signal 16 and first frequency signal 12 input to and postpone detection module 210.Described delay detection module 210 comprises counter, and the part in the integer section cycle that belongs to first frequency signal 12 in the described delay is counted, and count results exports Delay computing module 212 to as the first count value 27; Simultaneously, the corresponding output of remainder with not counting in the described delay exports pulse duration attenuation module 211 to as the first inhibit signal 261, the second inhibit signal 262.The pulse duration of described the first inhibit signal 261 and described the first input signal 15, time difference between the described first frequency signal 12 is corresponding, the pulse duration of described the second inhibit signal 262 and described the second input signal 16, time difference between the described first frequency signal 12 is corresponding, described the first inhibit signal 261, delay between the second inhibit signal 262 and described the first input signal 15, delay between the second input signal 16 is identical, and described the first count value 27 is the maximum integer numerical value doubly in included 12 cycles of first frequency signal of the delay between described the first inhibit signal 261 trailing edges and the second inhibit signal 262 trailing edges, be zero, perhaps be zero with the numerical value of described maximum integer times between any one integer.Relation between described the first inhibit signal 261, the second inhibit signal 262 and the first input signal 15, the second input signal 16 will describe in detail in an embodiment.
The first inhibit signal 261 decays to zero through the second impulse attenuation chain, and the second inhibit signal 262 decays to zero through the 3rd impulse attenuation chain.Because the output of the impulse attenuations at different levels unit of the second impulse attenuation chain, the 3rd impulse attenuation chain links to each other with the input of described Delay computing module 212, described Delay computing module 212 is according to the output A[n:1 of impulse attenuations at different levels unit], B[n:1], detect respectively first output signal on two impulse attenuation chains and be two impulse attenuation unit of zero, namely make the first inhibit signal 261 and the second inhibit signal 262 decay to respectively zero A
X, B
YThe quantity Y that described Delay computing module 212 decays to the quantity X of zero impulse attenuation unit in conjunction with the first count value 27, with the first inhibit signal 261, decay to the second inhibit signal 262 zero impulse attenuation unit calculates the delay 17 between the first input signal 15, the second input signal 16.
The attenuation principle of above-mentioned impulse attenuation unit as shown in Figure 4.Fig. 4 is the sequential chart of the impulse attenuation unit of delay measuring device of the present invention.Input is the input signal of input pulse attenuation units, and Output is the output signal of output impulse attenuation unit.The Input signal is after the decay of pulse attenuation units, and pulse duration is reduced to To by Ti, impulse attenuation width=Ti-To.The delay T of Input signal and Output signal rising edge
uThe delay T of＞Input signal and Output signal trailing edge
dThereby, make the pulse duration decay of Input signal.
In addition, as shown in figure 12, pulse duration attenuation module 211 includes only the 4th impulse attenuation chain, with 27 zero setting of the first count value, directly export the delay between the first input signal 15, the second input signal 16 to pulse duration attenuation module 211 as the 3rd inhibit signal 263, the relation between described the 3rd inhibit signal 263 and the first input signal 15, the second input signal 16 will describe in detail in an embodiment.
Fig. 5 is the structural representation of the first embodiment of delay measuring device of the present invention.In the present embodiment, the delay precision that delay measuring device requires is 20ps, and according to design requirement, second frequency signal 13 actual attenuation are that the quantity of zero impulse attenuation unit is set to N=250.By postponing the quantity N that precision and second frequency signal 13 actual attenuation are zero impulse attenuation unit, can determine that 12 cycles of first frequency signal are T=20ps*250=5ns, then frequency is 200MHz.For the pulse duration of second frequency signal 13 is identical with first frequency signal 12 cycle T, then second frequency signal 13 frequencies are 200MHz/4=50MHz, and duty ratio is 1: 3, and pulse duration is 5ns.
According to above-mentioned conclusion, be 2MHz with the set of frequency of the reference frequency signal 11 of crystal oscillator shown in Figure 1 output, duty ratio is 1: 1; The multiplier parameter of phase-locked loop 18 is 100, and duty ratio is 1: 1; The Frequency Dividing Factor of frequency divider 19 is 4, and duty ratio is 1: 3; The first impulse attenuation chain progression n=256 in the described impulse attenuation loop 29 (n＞N).
Analyze theoretically, second frequency signal 13 should be through after 250 impulse attenuation unit decay, and being attenuated is zero, also is C
249≠ 0, C
250=0.C
249, C
250As feedback signal input charge pump 31.
Work as C
249≠ 0, C
250=0 o'clock, consistent with theoretical value, charge pump 31 was failure to actuate.Work as C
249=0, C
250=0 o'clock, illustrate that the decay of the first impulse attenuation chain is too fast, the impulse attenuation width is larger, and 31 pairs of built-in capacitor discharges of charge pump reduce voltage control signal 25.Voltage control signal 25 links to each other with impulse attenuations at different levels unit, can control the impulse attenuation width of impulse attenuations at different levels unit.Can reduce the impulse attenuation width of impulse attenuations at different levels unit by reducing voltage control signal 25, impulse attenuation be slowed down, thereby reach theoretical value.Work as C
249≠ 0, C
250≠ 0 o'clock, illustrate that the first impulse attenuation chain decayed slowly, the impulse attenuation width is less, 31 pairs of built-in capacitor chargings of charge pump, booster tension control signal 25, thus increase the impulse attenuation width of impulse attenuations at different levels unit, impulse attenuation is accelerated, to reach theoretical value.Under the coordination of voltage control signal 25, every through an impulse attenuation unit, the time of decay is 1/250 second frequency signal 13 pulsewidth, namely T/250.Simultaneously, above-mentioned voltage control signal 25 also is provided to pulse duration attenuation module 211.
Described charge pump 31 comprises low-pass first order filter, and voltage control signal 25 is exported behind described low-pass first order filter filtering high frequency clutter.
The first input signal 15, the second input signal 16 and first frequency signal 12 input to and postpone detection module 210.The first inhibit signal 261 that 210 outputs of described delay detection module are corresponding with the first input signal 15, and second inhibit signal 262 corresponding with the second input signal 16.
In the present embodiment, the first input signal 15 is the pulse that a rising edge triggers; The pulse that the second input signal 16 triggers for another rising edge; First frequency signal 12 is the output frequency signal of described phase-locked loop 18, and frequency is 200MHz, and duty ratio is 1: 1.The present embodiment namely is the delay of measuring between the first input signal 15, the second input signal 16.
See also Fig. 6, in the present embodiment, described the first inhibit signal 261 is a pulse signal, and pulse duration is the time interval T1 of rising edge of the pulse of the rising edge of pulse of the first input signal 15 and adjacent first frequency signal 12.Described the second inhibit signal 262 also is a pulse signal, and pulse duration is the time interval T2 of rising edge of the pulse of the rising edge of pulse of the second input signal 16 and adjacent first frequency signal 12.The time interval of the trailing edge of the pulse of the trailing edge of the pulse of described the second inhibit signal 262 and described the first inhibit signal 261 is T3.Counter in the described delay detection module 210 T3 in the time numerical value to the integral multiple that comprises 12 cycles of first frequency signal count, count results M=3 is sent to Delay computing module 212 as the first count value 27, and this first count value 27 is the maximum integer numerical value doubly in 12 cycles of first frequency signal of the delay between the first input signal 15 and the second input signal 16.
Postponing detection module 210 is decomposed into the delay between the first input signal 15 and the second input signal 16: the maximum integer doubling time part-time T3 of first frequency signal 12 and less than the part-time T1-T2 of the one-period of first frequency signal 12.Therefore, the delay between the first input signal 15 and the second input signal 16 is T3+T1-T2.The cycle T of described integral multiple cycle portions time T 3=M* first frequency signal 12, wherein, M=3 is that counter in the described delay detection module 210 is to the first count value 27 of the maximum integer doubling time of first frequency signal 12 included in the described delay.Calculating to less than the part-time T1-T2 of the one-period of first frequency signal 12 is described in detail in connection with pulse duration attenuation module 211, Delay computing module 212.
Pulse duration attenuation module 211 comprises the second impulse attenuation chain and the 3rd impulse attenuation chain.Described the first inhibit signal 261 inputs the second impulse attenuation chain, described the second inhibit signal 262 inputs the 3rd impulse attenuation chain.
Described the second impulse attenuation chain by 256 impulse attenuation unit U (1) ... U (249), U (250), U (251) ... U (256) is composed in series, the corresponding output of every grade of attenuation units A
1... A
249, A
250, A
251... A
256, be used for described the first inhibit signal 261 pulsewidths are decayed to zero; Described the 3rd impulse attenuation chain also by 256 impulse attenuation unit U (1) ... U (249), U (250), U (251) ... U (256) is composed in series, the corresponding output of every grade of attenuation units B
1... B
249, B
250, B
251... B
256, be used for described the second inhibit signal 262 pulsewidths are decayed to zero.And, 256 impulse attenuation unit of described the second impulse attenuation chain, 256 impulse attenuation unit of the 3rd impulse attenuation chain all link to each other with 256 impulse attenuation unit of built-in the first impulse attenuation chain of impulse attenuation loop 29, are controlled by the voltage control signal 25 of the built-in charge pump 31 of impulse attenuation loop 29 simultaneously.Lifting or reduction by voltage control signal 25, can regulate simultaneously the impulse attenuation width of each impulse attenuation unit, also namely the impulse attenuation width of each impulse attenuation unit of the first impulse attenuation chain, the second impulse attenuation chain, the 3rd impulse attenuation chain is consistent.So that every impulse attenuation unit through second an impulse attenuation chain, the 3rd impulse attenuation chain, the time of decay is 1/250*T like this.
The output A[256:1 of 256 impulse attenuation unit of described the second impulse attenuation chain], the output B[256:1 of 256 impulse attenuation unit of described two impulse attenuation chains] all input to Delay computing module 212.In addition, described the first count value 27 is sent to Delay computing module 212.
Described Delay computing module 212 comprises pulse detection unit, the one 256 register, the 2 256 register.The output A[256:1 of described pulse detection unit paired pulses attenuation units], B[256:1] detect respectively.The output A[256:1 of the corresponding impulse attenuation of described the one 256 register unit]; The output B[256:1 of the corresponding impulse attenuation of the 2 256 register unit].The output of each impulse attenuation unit is detected in described pulse detection unit, and when the output of impulse attenuation unit was non-vanishing, the corresponding positions of the one 256 register or the 2 256 register then was set to 1; When the impulse attenuation unit was output as zero, the corresponding positions of the one 256 register or the 2 256 register then was set to 0.For example, if A
100≠ 0, then the 100th of the one 256 register the is 1, if B
101=0, then the 101st of the 2 256 register the is zero.Finish the detecting of output of all impulse attenuation unit of pulse-width attenuation module 211 when described pulse detection unit after, can learn according to the one 256 register, the 2 256 the value of register the first inhibit signal 261 is decayed to the quantity X of zero impulse attenuation unit, the second inhibit signal 262 decayed to the quantity Y of zero impulse attenuation unit.In the present embodiment, the value of the one 256 register=011111 then decays to the first inhibit signal 261 the quantity X=6 of zero impulse attenuation unit; If the value of the 2 256 register=01111 then decays to the first inhibit signal 261 the quantity Y=5 of zero impulse attenuation unit.Because every impulse attenuation unit through the second impulse attenuation chain or the 3rd impulse attenuation chain, the time of decay is T/250, and the first inhibit signal 261 pulse width T 1 are X/250*T so, and the second inhibit signal 262 pulse width T 2 are Y/250*T.
As shown in Figure 7, the second embodiment is that from the difference of the first embodiment the pulse duration of the first inhibit signal 261 and the second inhibit signal 262 is different.In the present embodiment, the pulse duration of described the first inhibit signal 261 is the time interval T1 of rising edge of rising edge and the pulse in 12 cycles of first frequency signal of being separated by of the pulse of the first input signal 15.The pulse duration of described the second inhibit signal 262 is the time interval T2 of rising edge of the pulse of the rising edge of pulse of the second input signal 16 and adjacent first frequency signal 12.The time interval of the trailing edge of the pulse of the trailing edge of the pulse of described the second inhibit signal 262 and described the first inhibit signal 261 is T3, and the counter in the described delay detection module 210 is counted 12 cycles of first frequency signal that comprise in the time at T3.In the present embodiment, count results M=2 is sent to Delay computing module 212 as the first count value 27.This first count value 27 is the numerical value of integral multiple in 12 cycles of first frequency signal of the delay between the first input signal 15 and the second input signal 16, between maximum integer numerical value and zero doubly.
Pulse duration attenuation module 211 comprises the second impulse attenuation chain that is comprised of 256 impulse attenuation units in series, and the 3rd impulse attenuation chain that is comprised of 256 impulse attenuation units in series.Described pulse duration attenuation module 211 receiver voltage control signals 25, under the adjusting of voltage control signal 25, so that every impulse attenuation unit through second an impulse attenuation chain, the 3rd impulse attenuation chain, the time of decay is T/250.
X=6 in the first embodiment, Y=5 is then in the present embodiment, X=256, Y=5 calculates and exports delay 17=(2+256/250-5/250) * 5ns between the first input signal 15 and the second input signal 16 by formula T3+T1-T2, with coming to the same thing of the first embodiment.
As shown in Figure 8, the 3rd embodiment is that from the difference of the first embodiment the pulse duration of the first inhibit signal 261 and the second inhibit signal 262 is different, and the impulse attenuation element number that described the second impulse attenuation chain, the 3rd impulse attenuation chain comprise is also different.The pulse duration of the first inhibit signal 261 is the time interval T1 of rising edge of the pulse of the rising edge of pulse of the first input signal 15 and the first frequency signal 12 adjacent with the rising edge of the pulse of the second input signal 16.The pulse duration of described the second inhibit signal 262 is the time interval T2 of rising edge of the pulse of the rising edge of pulse of the second input signal 16 and adjacent first frequency signal 12.The time interval of the trailing edge of the pulse of the trailing edge of the pulse of described the second inhibit signal 262 and described the first inhibit signal 261 is T3=0, and then count results M=0 is sent to Delay computing module 212 as the first count value 27.This first count value 27 is that the numerical value of integral multiple in 12 cycles of first frequency signal of the delay between the first input signal 15 and the second input signal 16 is zero.
Pulse duration attenuation module 211 comprises the second impulse attenuation chain that is comprised of 900 impulse attenuation units in series, and the 3rd impulse attenuation chain that is comprised of 900 impulse attenuation units in series.Described pulse duration attenuation module 211 receiver voltage control signals 25, under the adjusting of voltage control signal 25, so that every impulse attenuation unit through second an impulse attenuation chain, the 3rd impulse attenuation chain, the time of decay is T/250.
X=6 in first implements, Y=5 is then in the present embodiment, X=756, Y=5 calculates and exports delay 17=(0+756/250-5/250) * 5ns between the first input signal 15 and the second input signal 16 by formula T3-T2+T1, with coming to the same thing of the first embodiment.
It should be noted that, when the delay between the first input signal 15, the second input signal 16 is less than or equal to the one-period of first frequency signal 12, also can divide T3, T2, T1 according to the method for the first embodiment to the three embodiment, determine the pulse duration of the first inhibit signal 261 and the second inhibit signal 262.
The 4th embodiment of delay measuring device of the present invention is identical with the structure of the first embodiment, and structural representation as shown in Figure 5.The difference of the 4th embodiment and the first embodiment is, some signals of the first embodiment comprise that first frequency signal 12, the first input signals 15, the second input signals 16, the first inhibit signals 261, the second inhibit signals 262 are all rising edge and trigger; And the above-mentioned signal of the 4th embodiment is all the trailing edge triggering.
Fig. 9 is the sequential chart of the 4th embodiment of delay measuring device of the present invention.See also Fig. 5 and Fig. 9, in the present embodiment, the pulse duration of described the first inhibit signal 261 is the time interval T1 of trailing edge of the pulse of the trailing edge of pulse of the first input signal 15 and adjacent first frequency signal 12.The pulse duration of described the second inhibit signal 262 is the time interval T2 of trailing edge of the pulse of the trailing edge of pulse of the second input signal 16 and adjacent first frequency signal 12.The time interval of the rising edge of the pulse of the rising edge of the pulse of described the second inhibit signal 262 and described the first inhibit signal 261 is T3.Delay between the first input signal 15 and the second input signal 16 is T3+T1-T2.The computational methods of described delay, T3, T2, T1 are identical with the first embodiment.The pulse duration of the first inhibit signal 261 and the second inhibit signal 262 and the second impulse attenuation chain, the included impulse attenuation element number of the 3rd impulse attenuation chain can be identical with the second embodiment, the 3rd embodiment, do not repeat them here.
Some signals of the first embodiment to the four embodiment are all the rising edge triggering or trailing edge triggers.But the present invention is not limited to this, and described signal also can be that some signal is that rising edge triggers, and some signal is that trailing edge triggers.In integrated circuit (IC) design, for reducing the matching degree of design difficulty and raising integrated circuit, described signal generally all adopts identical triggering mode.
Figure 10 is the structural representation of the 5th embodiment of delay measuring device of the present invention.The difference of the 5th embodiment and the first embodiment is, the quantity of the input signal of the charge pump 31 that impulse attenuation loop 29 is built-in is different.In the first embodiment, the input signal of charge pump 31 is the output C of the 249th impulse attenuation unit of built-in impulse attenuation chain
249, the 250th impulse attenuation unit output C
250And in the 5th embodiment, the input signal of charge pump 31 is the output C of the 248th impulse attenuation unit
248, the 249th impulse attenuation unit output C
249, the 250th impulse attenuation unit output C
250, the 251st impulse attenuation unit output C
251C
248, C
249, C
250, C
251Input described charge pump 31 as feedback signal.
Analyzed in the first embodiment and learnt, in theory, after second frequency signal 13 was decayed through 250 impulse attenuation unit, being attenuated was zero, also is C
248≠ 0, C
249≠ 0, C
250=0, C
251=0.Work as C
248≠ 0, C
249≠ 0, C
250=0, C
251=0 o'clock, consistent with theoretical value, charge pump 31 was failure to actuate.Work as C
248=0, C
249=0, C
250=0, C
251=0 o'clock, illustrate that the decay of impulse attenuation chain is too fast, the impulse attenuation width is larger, and 31 pairs of built-in capacitor discharges of charge pump reduce voltage control signal 25, reduce the impulse attenuation width of impulse attenuations at different levels unit, impulse attenuation is slowed down, thereby reach theoretical value.Work as C
248≠ 0, C
249≠ 0, C
250≠ 0, C
251≠ 0 o'clock, illustrate that the impulse attenuation chain decayed slowly, the impulse attenuation width is less, 31 pairs of built-in capacitor chargings of charge pump, booster tension control signal 25, thus increase the impulse attenuation width of impulse attenuations at different levels unit, impulse attenuation is accelerated, to reach theoretical value.The 5th embodiment increases by two input signal C to described charge pump 31
248, C
251, make the detecting of 31 pairs of input signals of charge pump more directly perceived, make things convenient for, in time to built-in capacitor charge and discharge, accelerate the locking to the quantity that second frequency signal 13 is decayed to zero impulse attenuation unit according to negative-feedback signal.
The charge pump 31 of the 5th embodiment be input as C
248, C
249, C
250, C
251, but the present invention is not limited to this, and the input of described charge pump 31 can be C
248, C
249, C
250, perhaps C
249, C
250, C
251, perhaps C
247, C
248, C
249, C
250, C
251, C
252Deng.As long as the input of described charge pump 31 comprises C
249, C
250, the output of the impulse attenuation unit of arbitrary neighborhood all can be inputted, even C[256:1] the output of 256 impulse attenuation unit all can input to described charge pump 31.But input signal is too much, will strengthen the workload of 31 pairs of input signal detectings of described charge pump.Therefore, the quantity of better input signal is 2～4.
Figure 11 is the structural representation of the 6th embodiment of delay measuring device of the present invention.The difference of the 6th embodiment and the first embodiment is, the quantity difference of the input signal of Delay computing module 212.In the first embodiment, the output A[256:1 of 256 impulse attenuation unit of the second impulse attenuation chain of pulse duration attenuation module 211], the output B[256:1 of 256 impulse attenuation unit of the 3rd impulse attenuation chain] all input to described Delay computing module 212.In the 6th embodiment, the output A[250:1 of 250 impulse attenuation unit of the second impulse attenuation chain], the output B[250:1 of 250 impulse attenuation unit of the 3rd impulse attenuation chain] input to described Delay computing module 212.
By the first embodiment as can be known, second frequency signal 13 is decayed to the quantity N=250 of zero impulse attenuation unit.The pulse duration of described second frequency signal 13 is 5ns.The second impulse attenuation chain is used for decay the first inhibit signal 261, the three impulse attenuation chains and is used for decay the second inhibit signal 262.And the pulse duration of the first inhibit signal 261, the second inhibit signal 262 is all less than the one-period of first frequency signal 12.The frequency of described first frequency signal 12 is 200MHz, and the cycle is 5ns.Hence one can see that, and the pulse duration of the first inhibit signal 261, the second inhibit signal 262 is all less than 5ns.The built-in impulse attenuation chain of the second impulse attenuation chain, the 3rd impulse attenuation chain and impulse attenuation loop 29 is identical, and therefore, the quantity that the first inhibit signal 261, the second inhibit signal 262 is decayed to zero impulse attenuation unit must be less than 250.Hence one can see that, in the 4th embodiment, output A[250:1 with 250 impulse attenuation unit of the second impulse attenuation chain], the output B[250:1 of 250 impulse attenuation unit of the 3rd impulse attenuation chain] input to described Delay computing module 212, can realize the function of delay measuring device of the present invention.
Figure 12 is the structural representation of the 7th embodiment of delay measuring device of the present invention.The difference of the 7th embodiment and the first embodiment is, the quantity of the output of delay detection module 210, the impulse attenuation chain of pulse duration attenuation module 211, the input difference of Delay computing module 212.
Seeing also Figure 12 and Figure 13, in the 7th embodiment, postpone detection module 210 and only have an output signal, is the 3rd inhibit signal 263.The pulse duration of the 3rd inhibit signal 263 is with the first definite input signal 15 of the time interval T4 of the trailing edge of the pulse of the trailing edge of the pulse of the first input signal 15 and the second input signal 16, the delay between the second input signal 16.Correspondingly, pulse duration attenuation module 211 includes only the 4th impulse attenuation chain, is used for decay the 3rd inhibit signal 263; The output A[256:1 that also only has the 4th impulse attenuation chain] input to Delay computing module 212.In the present embodiment, the delay between the first input signal 15, the second input signal 16 is less than or equal to the cycle of first frequency signal 12, and the counter of described delay detection module 210 is disabled, and the first count value 27 is zero.The built-in pulse detection unit of Delay computing module 212 is to the signal A[256:1 of input] detect, the corresponding positions of the register that difference set is the one 256, can learn the quantity X ' that the 3rd inhibit signal 263 is decayed to zero impulse attenuation unit, delay T4 between the first input signal 15, the second input signal 16, the value that also is the result of calculation 17 of Delay computing module 212 is T=X '/250*5ns.
It should be noted that, delay between the first input signal 15, the second input signal 16 also is applicable to the delay measuring device of the 7th embodiment greater than the situation of the one-period of first frequency signal 12, directly the time interval T4 with the trailing edge of the pulse of the trailing edge of the pulse of the first input signal 15 and the second input signal 16 inputs the 4th impulse attenuation chain as the 3rd inhibit signal 263 pulse durations.The as required corresponding increase of impulse attenuation element number that this moment, the 4th impulse attenuation chain comprised.
If learn that in advance delay to be measured is less than the cycle of first frequency signal 12, can adopt the delay measuring device of the 7th embodiment, if learn that in advance delay to be measured is greater than the one-period of first frequency signal 12, can adopt the delay measuring device of the first embodiment, to reduce integrated circuit (IC) design and manufacture difficulty.
By delay measuring device of the present invention, can measure the delay between two input signals, postpone precision and reach picosecond.By introducing the impulse attenuation loop, guaranteed to postpone the accurate and stable of precision.The present invention can be applicable to delay locked loop etc. to be needed in the circuit that high-acruracy survey postpones.
Although the present invention with preferred embodiment openly as above; but it is not to limit claim; any those skilled in the art without departing from the spirit and scope of the present invention; can make possible change and modification, so protection scope of the present invention should be as the criterion with the scope that claim of the present invention was defined.
Claims (15)
1. impulse attenuation loop comprises:
The impulse attenuation chain is used for input signal is carried out impulse attenuation, and described impulse attenuation chain comprises the impulse attenuation unit of some grades of series connection, and the total amount of described impulse attenuation unit is greater than the quantity that with described attenuated input signal is zero impulse attenuation unit;
Charge pump is for the impulse attenuation width of the impulse attenuations at different levels unit of regulating described impulse attenuation chain;
The output of the partial pulse attenuation units of described at least impulse attenuation chain links to each other with the input of described charge pump, and described electric charge delivery side of pump links to each other with the input of the impulse attenuations at different levels unit of described impulse attenuation chain.
2. impulse attenuation loop as claimed in claim 1 is characterized in that, the described partial pulse attenuation units that links to each other with the input of described charge pump comprise at least output signal be zero impulse attenuation unit with and previous stage impulse attenuation unit.
3. impulse attenuation loop as claimed in claim 2 is characterized in that, the quantity of the described partial pulse attenuation units that links to each other with the input of described charge pump is 2 to 4.
4. impulse attenuation loop as claimed in claim 1 is characterized in that, described charge pump comprises low pass filter, is used for the high frequency clutter of the output signal of the described charge pump of filtering.
5. a delay measuring device is characterized in that, comprising:
The impulse attenuation loop is used for the second frequency signal from the outside is carried out impulse attenuation, exports the voltage control signal corresponding with the impulse attenuation width;
Postpone detection module, reception is from the first input signal, the second input signal, the first frequency signal of outside, the cycle of described first frequency signal is identical with the pulse duration of described second frequency signal, and described delay detection module is exported the first count value, the first inhibit signal and the second inhibit signal according to described first frequency signal; Wherein, the pulse duration of described the first inhibit signal and described the first input signal, time difference between the described first frequency signal is corresponding, the pulse duration of described the second inhibit signal and described the second input signal, time difference between the described first frequency signal is corresponding, described the first inhibit signal, delay between the second inhibit signal and described the first input signal, delay between the second input signal is identical, and described the first count value is the maximum integer numerical value doubly of included first frequency signal period of the delay between described the first inhibit signal trailing edge and the second inhibit signal trailing edge, be zero, perhaps be zero with the numerical value of described maximum integer times between any one integer;
The pulse duration attenuation module, receive the described voltage control signal of described first inhibit signal of described delay detection module output, described the second inhibit signal and the output of described impulse attenuation loop, according to described voltage control signal described the first inhibit signal and described the second inhibit signal are decayed the output attenuatoin result;
The Delay computing module receives the attenuation results that described the first count value and described pulse duration attenuation module are exported, and calculates the delay between described the first input signal and the second input signal.
6. delay measuring device as claimed in claim 5 is characterized in that, described impulse attenuation loop comprises:
The first impulse attenuation chain, be used for the second frequency signal is carried out impulse attenuation, described impulse attenuation chain comprises the impulse attenuation unit of some grades of series connection, and the total amount of the impulse attenuation unit of the first impulse attenuation chain is greater than the quantity that with described second frequency signal attenuation is zero impulse attenuation unit;
Charge pump is for the impulse attenuation width of the impulse attenuations at different levels unit of regulating described the first impulse attenuation chain;
The output of the partial pulse attenuation units of described at least the first impulse attenuation chain links to each other with the input of described charge pump, and described electric charge delivery side of pump links to each other with the input of every grade of impulse attenuation unit of described the first impulse attenuation chain.
7. delay measuring device as claimed in claim 5 is characterized in that, described delay detection module comprises counter, is used for recording described the first count value.
8. delay measuring device as claimed in claim 5 is characterized in that, the pulse duration of described the first inhibit signal is the time interval of the rising edge of a pulse of the rising edge of a pulse of the first input signal and adjacent first frequency signal; The pulse duration of described the second inhibit signal is the time interval of the rising edge of a pulse of the rising edge of pulse of the second input signal and adjacent first frequency signal; The maximum integer that described the first count value is first frequency signal period numerical value doubly.
9. delay measuring device as claimed in claim 5, it is characterized in that, the pulse duration of described the first inhibit signal is the time interval of the rising edge of a pulse of the rising edge of a pulse of the first input signal and the first frequency signal adjacent with the rising edge of a pulse of the second input signal; The pulse duration of described the second inhibit signal is the time interval of the rising edge of a pulse of the rising edge of a pulse of the second input signal and adjacent first frequency signal; Described the first count value is zero.
10. delay measuring device as claimed in claim 6 is characterized in that, described pulse duration attenuation module comprises:
The second impulse attenuation chain and the 3rd impulse attenuation chain carry out impulse attenuation to described the first inhibit signal and the second inhibit signal respectively;
Described the second impulse attenuation chain, the 3rd impulse attenuation chain include the impulse attenuation unit of some grades of series connection, and the total amount of described the second impulse attenuation chain and the impulse attenuation unit of the 3rd impulse attenuation chain is identical with the total amount of the impulse attenuation unit of described the first impulse attenuation chain;
The attenuation results of described pulse duration attenuation module output is the Output rusults of every grade of impulse attenuation unit of the second impulse attenuation chain and the 3rd impulse attenuation chain;
The electric charge delivery side of pump of described impulse attenuation loop links to each other with the input of described the second impulse attenuation chain and every grade of impulse attenuation unit of the 3rd impulse attenuation chain, and the width of described the second impulse attenuation chain and the impulse attenuation of every grade of impulse attenuation unit of the 3rd impulse attenuation chain is identical with the width of the impulse attenuation of every grade of impulse attenuation unit of described the first impulse attenuation chain.
11. a delay measuring device is characterized in that, comprising:
The impulse attenuation loop is used for the second frequency signal from the outside is carried out impulse attenuation, exports the voltage control signal corresponding with the impulse attenuation width;
Postpone detection module, receive the first input signal, the second input signal from the outside, the output delay signal, the pulse duration of described inhibit signal is identical with delay width between described the first input signal and the second input signal;
The pulse duration attenuation module receives the described inhibit signal of described delay detection module output and the described voltage control signal of described impulse attenuation loop output, described inhibit signal is decayed the output attenuatoin result according to described voltage control signal;
The Delay computing module receives the attenuation results that described pulse duration attenuation module is exported, and calculates the delay between described the first input signal and the second input signal.
12. delay measuring device as claimed in claim 11 is characterized in that, described impulse attenuation loop comprises:
The first impulse attenuation chain, be used for described second frequency signal is carried out impulse attenuation, described the first impulse attenuation chain comprises the impulse attenuation unit of some grades of series connection, and the total amount of the impulse attenuation unit of the first impulse attenuation chain is greater than the quantity that with described second frequency signal attenuation is zero impulse attenuation unit;
Charge pump is for the impulse attenuation width of the impulse attenuations at different levels unit of regulating described the first impulse attenuation chain;
The output of the partial pulse attenuation units of described at least the first impulse attenuation chain links to each other with the input of described charge pump, and described electric charge delivery side of pump links to each other with the input of every grade of impulse attenuation unit of described the first impulse attenuation chain.
13. delay measuring device as claimed in claim 11 is characterized in that, described delay detection module comprises counter, is used for record the first count value.
14. want 12 described delay measuring devices such as right, it is characterized in that, described pulse duration attenuation module comprises:
The 4th impulse attenuation chain carries out impulse attenuation to described inhibit signal;
Described the 4th impulse attenuation chain comprises the impulse attenuation unit of some grades of series connection, and the total amount of the impulse attenuation unit of described the 4th impulse attenuation chain is identical with the total amount of the impulse attenuation unit of described the first impulse attenuation chain;
The attenuation results of described pulse duration attenuation module output is the Output rusults of every grade of impulse attenuation unit of the 4th impulse attenuation chain;
The electric charge delivery side of pump of described impulse attenuation loop links to each other with the input of every grade of impulse attenuation unit of described the 4th impulse attenuation chain, and the width of the impulse attenuation of every grade of impulse attenuation unit of described pulse duration attenuation module is identical with the width of the impulse attenuation of every grade of impulse attenuation unit of described the first impulse attenuation chain.
15. such as claim 5 or 11 described delay measuring devices, it is characterized in that, described Delay computing module comprises pulse detection unit and at least one register, the output of the impulse attenuations at different levels unit of the impulse attenuation chain that each of described register and described pulse duration attenuation module comprise is corresponding, the output of every grade of impulse attenuation unit of detecting, described pulse detection unit, the corresponding positions of set register.
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| SG10201402890UA (en) * | 2014-06-04 | 2016-01-28 | Lantiq Deutschland Gmbh | Probabilistic digital delay measurement device |
| CN104467740B (en) * | 2014-12-24 | 2017-04-19 | 安徽一天电能质量技术有限公司 | Multi-channel digital filter based on FPGA |
| CN108134594B (en) * | 2016-11-30 | 2021-05-04 | 中芯国际集成电路制造(上海)有限公司 | Delay measurement circuit and delay measurement method of device to be measured |
| CN117434820B (en) * | 2023-12-19 | 2024-08-27 | 杭州谱育科技发展有限公司 | Time-to-digital converter and time-of-flight mass spectrometer |
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| US5598116A (en) * | 1994-10-31 | 1997-01-28 | Daewoo Electronics, Co. Ltd. | Apparatus for measuring a pulse duration |
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