CN102025332A - Gain control circuit and its gain control method - Google Patents

Abstract

The present invention discloses a gain control circuit and a gain control method thereof, which first continuously outputs a count value, then generates a ramp signal accordingly, and obtains an initial count value according to the ramp signal at a voltage value where a control voltage signal overlaps with the ramp signal, thereby determining the initial gain of the amplifier circuit. Afterwards, when the high and low voltages of the output signal of the amplifier circuit are respectively greater than and less than a preset upper and lower limit detection voltage, a detection signal is used to adjust the DC level of the ramp signal, and finally a count value less than the initial count value is obtained according to the ramp signal at the voltage value, thereby reducing the initial gain. The present invention utilizes a method of adjusting the DC level of the ramp signal to not only prevent the output signal of the audio amplifier circuit from being distorted, but also limit the output signal size of the audio amplifier circuit to protect the speaker or the ear.

Description

Gain control circuit and its gain control method

technical field

The invention relates to a control technology, in particular to a gain control circuit and a gain control method thereof.

Background technique

Analog electronic gain control can be achieved by a Gilbert cell. The basic conversion characteristic of a Gilbert cell is Y=kX, where Y is the output signal, X is the input signal, and k is a constant. It can be seen from the above formula that the amplification factor or signal gain can be defined as Y/X, and Y/X=k, so k is the gain of the output signal Y to the input signal X.

Please refer to FIG. 1 and FIG. 2(a) to FIG. 2(c) at the same time. Compared with the analog electronic gain control, the digital electronic gain control circuit has a larger dynamic range and more accurate audio amplifier circuit 10. The control of wherein Fig. 2 (a) is the output signal waveform figure of counter 18; No. 2 (b) figure is the sawtooth wave signal waveform figure that volume control voltage signal and sawtooth wave generator 20 produce, and sawtooth wave signal is according to counter 18 The output count value is generated; FIG. 2(c) is a waveform diagram of the latch signal output by the comparator 22. The basic principle of the digital electronic gain control circuit is to use a comparator 22 to compare the volume control voltage signal and the sawtooth wave signal. When the volume control voltage signal is equal to the voltage of the sawtooth wave signal, the comparator 22 outputs a latch signal to In the state temporary storage controller 24 , the content of the counter 18 is locked. The content of the counter 18 is used to control the values of the resistors 14 and 16 in the audio amplifier circuit 10 , and then determine the gain of the amplifier circuit 10 . However, under a certain fixed voltage gain condition, if the input signal of the amplifying circuit 10 is too large, the output signal of the amplifying circuit 10 may exceed the rated voltage and cause severe distortion. voltage, and its minimum voltage will be limited to the ground voltage.

Therefore, the present invention aims at the above problems and proposes a gain control circuit and a gain control method thereof, which solve the problems caused by the prior art.

Contents of the invention

The purpose of the present invention is to solve the technical problem that the existing electronic gain control circuit is prone to distortion.

The main purpose of the present invention is to provide a gain control circuit and its gain control method, which can not only prevent the output signal distortion of the audio amplifier circuit, but also limit the output of the audio amplifier circuit by adjusting the DC level of the ramp signal. Signal size to protect speakers or ears.

To achieve the above object, the present invention provides a gain control circuit, which is connected to an amplifying circuit, and the amplifying circuit outputs an output signal. The gain control circuit includes a counter, which continuously outputs a count value, and the counter is connected to a ramp (ramp ) generator, the ramp wave generator outputs a ramp wave signal according to the count value, and when the above ramp wave signal generator is a triangular wave signal generator or a sawtooth wave signal generator, the ramp wave signals output by the ramp wave signal generator are respectively Triangular wave signal or sawtooth wave signal. The amplifying circuit and the counter are connected to a processor, and the processor receives the ramp signal and a control voltage signal, and obtains the count value corresponding to the ramp signal from the counter as the first voltage value at which the control voltage signal and the ramp signal overlap. A count value is temporarily stored, and the gain of the amplifying circuit is determined by the first count value. There is also a voltage detector, which presets an upper and lower limit detection voltage, and receives the output signal, and outputs a detection signal when the high voltage of the output signal is greater than the upper limit detection voltage, or the low voltage of the output signal is lower than the lower limit detection voltage, The ramp wave generator and the voltage detector are connected to a DC level adjuster, which receives the detection signal to adjust the DC level of the ramp wave signal, so that the processor obtains from the counter a value corresponding to the ramp wave signal and less than the first count value. The count value is used as the second count value to update the first count value, and the gain of the amplifying circuit is reduced by the second count value.

Wherein the processor further includes: a comparator, which receives the ramp signal and the control voltage signal, and outputs a comparator when the control voltage signal and the ramp signal overlap at the voltage value a first latch signal, outputting a second latch signal when the control voltage signal and the ramp signal overlap at the voltage value after the DC level of the ramp signal is adjusted; and A state temporary storage controller, which is connected to the counter and the amplification circuit, and receives the first latch signal when the control voltage signal and the ramp signal overlap at the voltage value, to Obtain the count value corresponding to the ramp signal from the counter at the voltage value as the first count value and temporarily store it, and use the first count value to determine the gain of the amplifying circuit , or after the DC level of the ramp signal is adjusted, and when the control voltage signal and the ramp signal overlap at the voltage value, the second latch signal is received, and the The voltage value obtains the count value corresponding to the ramp signal and smaller than the first count value from the counter, so as to update the first count value as the second count value, and by using the The second count value decreases the gain of the amplifying circuit.

When the waveform slope of the ramp signal is positive or negative, the DC level adjuster increases or decreases the DC level of the ramp signal respectively, so as to further reduce the gain of the amplifying circuit.

Wherein when the high voltage of the output signal is greater than the upper limit detection voltage, the longer the time interval between the two time points where the output signal and the upper limit detection voltage intersect, the DC level of the ramp signal The higher the adjustment range is; when the low voltage of the output signal is greater than the lower limit detection voltage, the longer the time interval between the two time points where the output signal and the lower limit detection voltage are interleaved, the ramp wave The higher the adjustment range of the DC level of the signal is.

Wherein the control voltage signal is an analog signal; the counter is a ring counter (ringcounter); the amplifying circuit is an audio amplifier, and the control voltage signal is a volume control voltage signal, and the amplifying circuit receives an input signal and After it is amplified, the output signal is output.

The present invention also provides a gain control method, which receives an output signal from an amplifying circuit to control the gain of the amplifying circuit. The gain control method first outputs a count value continuously, then generates a ramp signal according to the count value, and then Receive the ramp wave signal and a control voltage signal, and obtain the count value corresponding to the ramp wave signal as the first count value at the overlapping voltage value of the control voltage signal and the ramp wave signal, and temporarily store it, and borrow the first count value Determines the initial gain of the amplifier circuit. After the initial gain is determined, if the high voltage of the output signal is greater than a preset upper limit detection voltage, or the low voltage of the output signal is lower than a preset lower limit detection voltage, the voltage detector outputs a detection signal, and the DC level regulator After receiving the detection signal, the DC level of the ramp signal is adjusted, and finally a count value corresponding to the ramp signal and smaller than the first count value is obtained from the voltage value to update the first count value as the second count value, and The initial gain is decreased by the second count value.

The step of receiving the ramp signal and the control voltage signal to obtain the first count value and determining the initial gain further includes the following steps: receiving the ramp signal and the control voltage signal, and outputting a first latch signal when the control voltage signal and the ramp signal overlap at the voltage value; The count value corresponding to the wave signal is temporarily stored as the first count value, and the initial gain is determined by the first count value.

Wherein the step of obtaining the second count value and thereby reducing the initial gain further includes the following steps: outputting a second latch signal; and receiving the second latch signal to obtain the voltage at the voltage value The count value corresponding to the ramp signal and smaller than the first count value is used as the second count value to update the first count value, and the initial gain is reduced by the second count value .

Wherein, when the waveform slope of the ramp wave signal is positive or negative, in the step of receiving the detection signal to adjust the DC level, respectively increase or decrease the DC level of the ramp signal, to reduce the initial gain.

Wherein when the high voltage of the output signal is greater than the upper limit detection voltage, the longer the time interval between the two time points where the output signal and the upper limit detection voltage intersect, the DC level of the ramp signal The higher the adjustment range is; when the low voltage of the output signal is less than the lower limit detection voltage, the longer the time interval between the two time points where the output signal and the upper limit detection voltage intersect, the ramp wave The higher the adjustment range of the DC level of the signal is.

The beneficial effect of the present invention is that by adjusting the DC level of the ramp signal, not only can the output signal of the audio amplifier circuit be prevented from being distorted, but also the output signal of the audio amplifier circuit can be limited to protect speakers or ears.

Description of drawings

Fig. 1 is the circuit block diagram of prior art;

Figure 2(a) to Figure 2(c) are the signal output by the counter in the prior art, the volume control voltage signal, the sawtooth wave signal with a positive slope, and the corresponding latch signal waveforms;

Fig. 3 is the circuit block diagram of the first embodiment of the present invention;

Fig. 4 (a) to Fig. 4 (b) are the signal output by the counter of the present invention, the volume control voltage signal, the sawtooth wave signal waveform diagram of positive slope;

FIG. 5 is a waveform diagram of an input signal and an output signal of an amplifying circuit in the first embodiment of the present invention;

Fig. 6 (a) to Fig. 6 (b) are the signal output by the counter of the present invention, the volume control voltage signal, the sawtooth wave signal waveform diagram of the negative slope;

Fig. 7 is the circuit block diagram of the second embodiment of the present invention;

Figure 8(a) to Figure 8(c) are the signals output by the counter, the volume control voltage signal, the positive slope sawtooth wave signal, and the corresponding latch signal waveform diagrams of the present invention;

FIG. 9 is a waveform diagram of an input signal and an output signal of an amplifying circuit in a second embodiment of the present invention;

Figure 10(a) to Figure 10(c) are the signals output by the counter, the volume control voltage signal, the sawtooth wave signal with a negative slope, and the corresponding latch signal waveform diagrams of the present invention;

Fig. 11 is an experimental waveform diagram of the volume control voltage signal, the positive slope sawtooth signal, and the output signal of the amplifier circuit of the present invention.

Explanation of reference signs:

10-amplification circuit; 12-amplifier; 14-resistance; 16-resistance; 18-counter; 20-sawtooth wave generator; 22-comparator; 24-status temporary storage controller; 26-amplification circuit; 30-resistor; 32-resistor; 34-ring counter; 36-sawtooth wave generator; 38-processor; 40-voltage detector; 42-DC level regulator; 44-comparator; 46-status temporary storage control device.

Detailed ways

The structural features of the present invention and the achieved effects are described below with preferred embodiment drawings and detailed descriptions:

The gain control circuit of the present invention is connected with an amplifying circuit and receives a control voltage signal to determine the gain of the amplifying circuit. In the following, the control voltage signal and the amplifying circuit are respectively taken as examples of the volume control voltage signal and the audio amplifying circuit to illustrate the circuit structure and operation of the present invention.

Please refer to Fig. 3, Fig. 4 (a) to Fig. 4 (b), wherein Fig. 3 is the circuit block diagram of the first embodiment; Fig. 4 (a) is the signal waveform diagram output by the counter; Fig. 4 (b) is positive Slope sawtooth signal and volume control voltage signal waveform diagram. The present invention is connected to an audio amplifier circuit 26, and the amplifier circuit 26 includes an amplifier 28, a resistor 30, and a resistor 32. The positive input terminal of the amplifier 28 receives a reference signal, and the negative input terminal is connected to a resistor 30 and a resistor 32 to receive an input signal. , the output end of the amplifier 28 is connected to the resistor 32, the amplifier 28 amplifies the input signal, and outputs an output signal at the output end of the amplifier 28. Since the resistance values of the resistor 30 and the resistor 32 are respectively Ri and Rf, the gain of the amplifying circuit 26 is -(Rf/Ri).

The present invention includes a ring counter (ring counter) 34 as a counter, and a ramp generator connected to it, the ramp generator generates a ramp (ramp) signal according to the count value continuously output by the counter 34, and the ramp generates The generator can be a sawtooth wave generator or a triangular wave generator, and the generated signal is a sawtooth wave signal or a triangular wave signal. In this embodiment, the ramp wave generator is the sawtooth wave generator 36 as an example. Because the count value output by the ring counter 34 is periodic, the period of the sawtooth wave signal is the same as the cycle of the count value. In this embodiment, the count value output by the ring counter 34 is cycled eight times as a cycle. The counting values are 000, 001, 010, 011, 100, 101, 110, 111 in sequence, and the counting value after the ninth time will start counting from 000, and the sawtooth wave signal will It will increase or decrease a fixed voltage range. When the ninth count value is output, the sawtooth wave signal will return to the original voltage value corresponding to the count value 000. In other words, each voltage value of the sawtooth wave signal corresponds to a count value. , and the waveform slope of the sawtooth signal can be set as positive or negative.

The sawtooth wave generator 36 and the resistors 30 and 32 of the amplifying circuit 26 are connected to a processor 38, and the processor 38 receives the sawtooth wave signal and a volume control voltage signal that is an analog signal, and alternates between the volume control voltage signal and the sawtooth wave voltage signal. When repeating, the count value corresponding to the sawtooth signal is obtained from the counter 34 as the first count value and temporarily stored, and the values of the resistors 30 and 32 are determined by the first count value, and then the gain of the amplifier circuit 26 is determined.

The output end of the amplifying circuit 26 is connected to a voltage detector 40, which presets an upper and lower limit detection voltage, and receives the output signal, and when the high voltage of the output signal is greater than the upper limit detection voltage, or the low voltage of the output signal is lower than the lower limit detection voltage , output a detection signal. The voltage detector 40 is connected to the sawtooth wave generator 36 through a DC level adjuster 42. The DC level adjuster 42 receives the detection signal to increase or decrease the DC level of the ramp wave signal, so that the processor 38 can read from the counter In step 34, a count value corresponding to the ramp wave signal and smaller than the first count value is obtained to update the first count value as the second count value, and the gain of the amplifying circuit 26 is reduced by the second count value.

Please refer to FIG. 5 at the same time. The operation of the first embodiment will be described below, and a sawtooth signal with a positive slope will be used as an example. Before the time point _t2 , the volume control voltage signal and the sawtooth wave signal overlap at a voltage value V _a , which corresponds to the time point _t1 in the first cycle waveform of the sawtooth wave signal, so the processor 38 will be at the moment t ₁ Take out the count value 100 corresponding to the voltage value V _a of the sawtooth signal from the counter 34 as the first count value and temporarily store it, and use it to determine the values of the resistors 30 and 32 to determine the initial gain of the amplifier circuit 26. Since the sawtooth wave signal and the volume control voltage signal overlap once in each period of the sawtooth wave signal, the action of determining the gain is also performed once in each period of the sawtooth wave signal. And because before the time point _t2 , the count value corresponding to the voltage point where the sawtooth wave signal overlaps with the volume control voltage signal is 100, so the gain of the amplifying circuit 26 also remains unchanged.

In other words, before the time point _t2 , the amplifying circuit 26 receives an original input signal whose high and low voltages are respectively +V ₁ and -V ₁ , and then outputs an original output signal according to the initial gain. In this example, the original output The high and low voltages of the signal are equal to the upper and lower limit detection voltages +V _ref and -V _ref of the voltage detector 40 .

After the time point _t2 , increase the original input signal so that the amplifying circuit 26 receives an increased input signal whose high and low voltages are respectively + _V2 and _-V2 , where + _V2 is greater than + _V1 , - V ₂ is smaller than -V ₁ . If the initial gain of the amplifying circuit 26 remains unchanged at this time, the amplifying circuit 26 will output an amplified output signal whose high and low voltages are respectively +V ₃ and -V ₃ , where +V ₃ is greater than +V _ref and -V ₃ is less than −V _ref , so the voltage detector 40 outputs a detection signal to the DC level regulator 42 to control the DC level regulator 42 to increase the DC level of the sawtooth wave signal.

The ramped sawtooth wave signal, from the waveform diagram, the voltage point where the sawtooth wave signal overlaps with the volume control voltage signal is located at the lower position of the sawtooth wave signal. After time point _t2 , this voltage point corresponds to The time point _t3 in the first cycle waveform of the sawtooth wave signal, so at this moment the processor 38 will take out the count value 010 corresponding to the voltage value _Va of the sawtooth wave signal and smaller than the first count value from the counter ₃₄ at t3, As the second count value, the first count value is updated accordingly, and the values of the resistors 30 and 32 are changed by the second count value, so as to reduce the initial gain of the amplifying circuit 26 .

Since the gain of the amplifying circuit 26 is reduced, the amplifying circuit 26 will output a modified output signal whose high and low voltages are respectively +V ₄ and -V ₄ , where +V ₄ is less than +V _ref and -V ₄ is greater than - V _ref , so that the output distortion can be reduced, and the output signal size of the audio amplifier circuit can be limited to protect the speaker or ears. It is worth mentioning that in the amplified output signal, the longer the time interval between the two time points where the output signal and the upper limit detection voltage intersect, that is, the longer the time interval between _t4 and _t5 , the sawtooth signal The higher the magnitude of the DC level adjustment, the lower the gain of the amplifying circuit 26 is reduced; or in the amplified output signal, the longer the time interval between the two time points where the output signal and the lower limit detection voltage intersect, that is, t The longer the time interval between ₆ and _t7 , the higher the adjustment range of the DC level of the sawtooth signal, and the lower the gain of the amplifying circuit 26 is reduced.

Please refer to Figure 3, Figure 5, Figure 6(a) to Figure 6(b) below, where Figure 6(a) is the signal waveform diagram output by the counter; Figure 6(b) is the negative slope sawtooth signal and volume control Voltage signal waveform diagram. Another operation of the first embodiment is described below, which is similar to the above-mentioned operation, and a sawtooth signal with a negative slope is used as an example. Before the time point _t2 , the volume control voltage signal and the sawtooth wave signal overlap at a voltage value V _a , which corresponds to the time point _t1 in the first cycle waveform of the sawtooth wave signal, so the processor 38 will be at the moment t ₁ Take out the count value 010 corresponding to the voltage value V _a of the sawtooth signal from the counter 34 as the first count value and temporarily store it, and use it to determine the values of the resistors 30 and 32 to determine the initial gain of the amplifier circuit 26.

In other words, before the time point _t2 , the amplifying circuit 26 receives an original input signal whose high and low voltages are respectively +V ₁ and -V ₁ , and then outputs an original output signal according to the initial gain. In this example, the original output The high and low voltages of the signal are equal to the upper and lower limit detection voltages +V _ref and -V _ref of the voltage detector 40 .

After the time point _t2 , increase the original input signal so that the amplifying circuit 26 receives an increased input signal whose high and low voltages are respectively + _V2 and _-V2 , where + _V2 is greater than + _V1 , - V ₂ is smaller than -V ₁ . If the initial gain of the amplifying circuit 26 remains unchanged at this time, the amplifying circuit 26 will output an amplified output signal whose high and low voltages are respectively +V ₃ and -V ₃ , where +V ₃ is greater than +V _ref and -V ₃ is less than −V _ref , so the voltage detector 40 outputs a detection signal to the DC level regulator 42 to control the DC level regulator 42 to lower the DC level of the sawtooth wave signal.

The sawtooth wave signal after adjustment, from the waveform diagram, the voltage point where the sawtooth wave signal overlaps with the volume control voltage signal is located at a higher position of the sawtooth wave signal. After time point _t2 , this voltage point corresponds to The time point _t3 in the first cycle waveform of the sawtooth wave signal, so at this moment the processor 38 will take out the count value 001 corresponding to the voltage value _Va of the sawtooth wave signal and less than the first count value from the counter ₃₄ at t3, As the second count value, the first count value is updated accordingly, and the values of the resistors 30 and 32 are changed by the second count value, so as to reduce the initial gain of the amplifying circuit 26 .

Since the gain of the amplifying circuit 26 is reduced, the amplifying circuit 26 will output a modified output signal whose high and low voltages are respectively +V ₄ and -V ₄ , where +V ₄ is less than +V _ref and -V ₄ is greater than - V _ref , so that the output distortion can be reduced, and the output signal size of the audio amplifier circuit can be limited to protect the speaker or ears. Similarly, in the amplified output signal, the longer the time interval between the two time points where the output signal intersects with the upper limit detection voltage, that is, the longer the time interval between _t4 and _t5 , the DC level of the sawtooth wave signal The higher the magnitude of the bit adjustment, the lower the gain of the amplifying circuit 26; or in the amplified output signal, the longer the time interval between the two time points where the output signal and the lower limit detection voltage intersect, that is, _t6 and t The longer the time interval between ₇ , the higher the adjustment range of the DC level of the sawtooth signal, and the lower the gain of the amplifying circuit 26 is reduced.

The second embodiment of the present invention will be introduced below. Please refer to FIG. 7 . The difference between it and the first embodiment is that a comparator 44 and a state register controller 46 are used to replace the processor. The comparator 44 is connected to the sawtooth wave generator 36, and receives the sawtooth wave signal and the volume control voltage signal, and outputs a first latch signal when the volume control voltage signal and the sawtooth wave voltage signal overlap at a voltage value V; After the DC level of the sawtooth wave signal is adjusted, and when the volume control voltage signal and the sawtooth wave voltage signal overlap at the voltage value V, a second latch signal is output. The state temporary storage controller 46 is connected to the comparator 44 and the resistors 30 and 32 of the amplifying circuit 26, and receives the first latch signal to obtain the count value corresponding to the voltage value V of the sawtooth signal from the counter 34 as the first count value and temporarily store it, and determine the gain size of the amplifying circuit 26 by the first count value; or receive the second latch signal to obtain from the counter 34 the value corresponding to the voltage value V of the sawtooth signal and smaller than the first count value The count value is used as the second count value to update the first count value, and the gain of the amplifying circuit 26 is reduced by the second count value.

The action of the second embodiment is described below, and a sawtooth wave signal with a positive slope is taken as an example, please refer to Figure 7, Figure 8(a) to Figure 8(c) and Figure 9 at the same time, where Figure 8(a) is the counter output The signal waveform diagram; Figure 8(b) is the waveform diagram of the positive slope sawtooth signal and the volume control voltage signal; Figure 8(c) is the latch signal waveform diagram.

Before the time point _t2 , the volume control voltage signal and the sawtooth wave signal overlap at the voltage value V _a , which corresponds to the time point _t1 in the first period waveform of the sawtooth wave signal, so the comparator 44 will output a The first latch signal is sent to the state temporary storage controller 46, so that the state temporary storage controller 46 takes out the count value 100 _{corresponding} to the voltage value Va of the sawtooth signal from the counter 34 at _t1 , as the first count value and temporarily Save it, and use it to determine the value of the resistors 30, 32 to determine the initial gain of the amplifying circuit 26. Since the sawtooth wave signal and the volume control voltage signal overlap once in each period of the sawtooth wave signal, the action of determining the gain is also performed once in each period of the sawtooth wave signal. And because before the time point _t2 , the count value corresponding to the voltage point where the sawtooth wave signal overlaps with the volume control voltage signal is 100, so the gain of the amplifying circuit 26 also remains unchanged.

In other words, before the time point _t2 , the amplifying circuit 26 receives an original input signal whose high and low voltages are respectively +V ₁ and -V ₁ , and then outputs an original output signal according to the initial gain. In this example, the original output The high and low voltages of the signal are equal to the upper and lower limit detection voltages +V _ref and -V _ref of the voltage detector 40 .

After the time point _t2 , increase the original input signal so that the amplifying circuit 26 receives an increased input signal whose high and low voltages are respectively + _V2 and _-V2 , where + _V2 is greater than + _V1 , - V ₂ is smaller than -V ₁ . If the initial gain of the amplifying circuit 26 remains unchanged at this time, the amplifying circuit 26 will output an amplified output signal whose high and low voltages are respectively +V ₃ and -V ₃ , where +V ₃ is greater than +V _ref and -V ₃ is less than −V _ref , so the voltage detector 40 outputs a detection signal to the DC level regulator 42 to control the DC level regulator 42 to increase the DC level of the sawtooth wave signal.

The ramped sawtooth wave signal, from the waveform diagram, the voltage point where the sawtooth wave signal overlaps with the volume control voltage signal is located at the lower position of the sawtooth wave signal. After time point _t2 , this voltage point corresponds to The time point _t3 in the first cycle waveform of the sawtooth wave signal, so at this moment the comparator 44 will output the second latch signal to the state temporary storage controller 46, so that the state temporary storage controller 46 is from the counter 34 at _t3 Take out the count value 010 corresponding to the voltage value V _a of the sawtooth signal and smaller than the first count value as the second count value and thereby update the first count value, and change the values of the resistors 30 and 32 by the second count value, To reduce the initial gain of the amplifying circuit 26.

Since the gain of the amplifying circuit 26 is reduced, the amplifying circuit 26 will output a modified output signal whose high and low voltages are respectively +V ₄ and -V ₄ , where +V ₄ is less than +V _ref and -V ₄ is greater than - V _ref , and the effect achieved by the second embodiment is the same as that of the first embodiment.

In addition, in the amplified output signal, the longer the time interval between the two time points where the output signal and the upper limit detection voltage intersect, that is, the longer the time interval between _t4 and _t5 , the DC level of the sawtooth wave signal The higher the adjustment range is, the lower the gain of the amplifying circuit 26 is reduced; or in the amplified output signal, the time interval between the two time points where the output signal and the lower limit detection voltage intersect is longer, that is, _t6 and _t7 The longer the time interval, the higher the adjustment range of the DC level of the sawtooth signal, and the lower the gain of the amplifying circuit 26 is reduced.

Please refer to Figure 7, Figure 9, Figure 10(a) to Figure 10(c) below, where Figure 10(a) is the signal waveform diagram output by the counter; Figure 10(b) is the negative slope sawtooth signal and volume control Waveform diagram of the voltage signal; Figure 10(c) is a waveform diagram of the latch signal. Another operation of the second embodiment is described below, which is similar to the above-mentioned operation, and a sawtooth signal with a negative slope is used as an example. Before the time point _t2 , the volume control voltage signal and the sawtooth wave signal overlap at the voltage value V _a , which corresponds to the time point _t1 in the first period waveform of the sawtooth wave signal, so the comparator 44 will output a The first latch signal is sent to the state temporary storage controller 46, so that the state temporary storage controller 46 takes out the count value 010 _{corresponding} to the voltage value Va of the sawtooth signal from the counter 34 at _t1 , as the first count value and temporarily Save it, and use it to determine the value of the resistors 30, 32 to determine the initial gain of the amplifying circuit 26.

In other words, before the time point _t2 , the amplifying circuit 26 receives an original input signal whose high and low voltages are respectively +V ₁ and -V ₁ , and then outputs an original output signal according to the initial gain. In this example, the original output The high and low voltages of the signal are equal to the upper and lower limit detection voltages +V _ref and -V _ref of the voltage detector 40 .

After the time point _t2 , increase the original input signal so that the amplifying circuit 26 receives an increased input signal whose high and low voltages are respectively + _V2 and _-V2 , where + _V2 is greater than + _V1 , - V ₂ is smaller than -V ₁ . If the initial gain of the amplifying circuit 26 remains unchanged at this time, the amplifying circuit 26 will output an amplified output signal whose high and low voltages are respectively +V ₃ and -V ₃ , where +V ₃ is greater than +V _ref and -V ₃ is less than −V _ref , so the voltage detector 40 outputs a detection signal to the DC level regulator 42 to control the DC level regulator 42 to lower the DC level of the sawtooth wave signal.

The sawtooth wave signal after adjustment, from the waveform diagram, the voltage point where the sawtooth wave signal overlaps with the volume control voltage signal is located at a higher position of the sawtooth wave signal. After time point _t2 , this voltage point corresponds to The time point _t3 in the first cycle waveform of the sawtooth wave signal, so at this moment the comparator 44 will output a second latch signal to the state temporary storage controller 46, so that the state temporary storage controller 46 is from the counter at _t3 34 Take out the count value 001 corresponding to the voltage value V _a of the sawtooth signal and smaller than the first count value as the second count value and thereby update the first count value, and change the values of the resistors 30 and 32 by the second count value , to reduce the initial gain of the amplifying circuit 26.

Since the gain of the amplifying circuit 26 is reduced, the amplifying circuit 26 will output a modified output signal whose high and low voltages are respectively +V ₄ and -V ₄ , where +V ₄ is less than +V _ref and -V ₄ is greater than - V _ref , and the effect achieved by the second embodiment is the same as that of the first embodiment.

In addition, in the amplified output signal, the longer the time interval between the two time points where the output signal and the upper limit detection voltage intersect, that is, the longer the time interval between _t4 and _t5 , the DC level of the sawtooth wave signal The higher the adjustment range is, the lower the gain of the amplifying circuit 26 is reduced; or in the amplified output signal, the time interval between the two time points where the output signal and the lower limit detection voltage intersect is longer, that is, _t6 and _t7 The longer the time interval, the higher the adjustment range of the DC level of the sawtooth wave signal, and the lower the gain of the amplifying circuit 26 is reduced.

Please refer to Figure 11, which is a waveform diagram obtained by using the circuit in Figure 7. The upper figure shows the volume control voltage signal and output signal. Before 18 milliseconds (ms), the volume control voltage signal continues to increase, and the output signal also continues to increase. Before nearly 18 milliseconds, the output signal is close to the upper limit detection voltage, so the output signal is slightly reduced after 18 milliseconds. At 18.9 milliseconds, the output signal exceeds the upper limit detection voltage. At this time, the volume control voltage signal no longer changes, but the output signal is greatly reduced. The lower figure in Figure 11 shows the volume voltage control voltage signal and the sawtooth wave signal, and its time axis is an enlarged view between 18 milliseconds and 20 milliseconds in the upper figure. When the time is about 18.2 milliseconds, because the output signal exceeds the upper limit detection voltage, The DC level of the sawtooth signal is raised, so that at about 18.86 milliseconds, the volume control voltage signal overlaps with the sawtooth signal at a lower count value, and the gain of the amplifier is reduced, so that the amplitude of the output signal is reduced. It can be seen from the figure below that after a long time, the DC level of the sawtooth signal slowly returns to the original DC level, so that the volume control voltage signal overlaps the sawtooth signal at a higher count value, and the output signal slows down. Slowly return to the original amplitude.

To sum up, the present invention uses the method of adjusting the DC level of the ramp signal to limit the output signal of the audio amplifier circuit to protect the speaker and the ears.

The above description of the present invention is illustrative rather than restrictive. Those skilled in the art understand that many modifications, changes or equivalents can be made to it within the spirit and scope of the claims, but they will all fall into within the protection scope of the present invention.

Claims (10)

1. a gain control circuit is characterized in that, this gain control circuit connects an amplifying circuit, and this amplifying circuit is exported an output signal, and this gain control circuit comprises:

One counter, it exports a count value continuously;

One ramp generator, it connects this counter, and exports a ramp signal according to this count value;

One processor, connect this amplifying circuit and this counter, and receive this ramp signal and one control voltage signal, and at the magnitude of voltage of this control voltage signal and this ramp signal crossover, from this counter, obtain this count value corresponding as first count value and temporary, and this first count value of mat determines the gain size of this amplifying circuit with this ramp signal;

One voltage detector, its default upper and lower limit detects voltage, and receives this output signal, and detects voltage at the high voltage of this output signal greater than this upper limit, or the low-voltage of this output signal is exported a detection signal when detecting voltage less than this lower limit; And

The accurate position of one direct current adjuster, connect this ramp generator and this voltage detector, and receive this detection signal, with the accurate position of the direct current of adjusting this ramp signal, make this processor from this counter, obtain corresponding and less than this count value of this first count value with this ramp signal, to upgrade this first count value as second count value, this second count value of mat reduces the gain of this amplifying circuit again.

2. gain control circuit as claimed in claim 1 is characterized in that, this processor more comprises:

One comparator, it receives this ramp signal and this control voltage signal, and at this control voltage signal and this ramp signal crossover during in this magnitude of voltage, export one first latch-up signal, after the accurate position of the direct current of this ramp signal is adjusted, during in this magnitude of voltage, export one second latch-up signal at this control voltage signal and this ramp signal crossover; And

One state is kept in controller, it connects this counter and this amplifying circuit, and at this control voltage signal and this ramp signal crossover during in this magnitude of voltage, receive this first latch-up signal, from this counter, to obtain this count value corresponding at this magnitude of voltage as this first count value and temporary with this ramp signal, and this first count value of mat determines the gain size of this amplifying circuit, or after the accurate position of the direct current of this ramp signal is adjusted, and at this control voltage signal and this ramp signal crossover during in this magnitude of voltage, receive this second latch-up signal, and from this counter, obtain corresponding and less than this count value of this first count value with this ramp signal at this magnitude of voltage, to upgrade this first count value as this second count value, this second count value of mat reduces the gain of this amplifying circuit again.

3. gain control circuit as claimed in claim 1 is characterized in that, when the waveform slope of this ramp signal was plus or minus, the accurate position of this direct current adjuster increased or downgrade the accurate position of direct current of this ramp signal respectively, with so that reduce the gain of this amplifying circuit.

4. gain control circuit as claimed in claim 1, it is characterized in that, when the high voltage of this output signal detects voltage greater than this upper limit, time interval between two time points that this output signal and this upper limit detection voltage interlock is longer, and then the amplitude of accurate adjustment of the direct current of this ramp signal is higher; When the low-voltage of this output signal detected voltage greater than this lower limit, the time interval between two time points that this output signal and this lower limit detection voltage interlock was longer, and then the amplitude of accurate adjustment of the direct current of this ramp signal is higher.

5. gain control circuit as claimed in claim 1 is characterized in that, this ramp signal generator is sawtooth signal generator or triangular signal generator, and the signal of its generation is respectively sawtooth signal or triangular signal; This control voltage signal is an analog signal; This counter is a ring counter; This amplifying circuit is an audio frequency amplifier, and this control voltage signal is volume control voltage signal, and this amplifying circuit receives an input signal and it is amplified after, export this output signal.

6. gain control method, the output signal that it receives amplifying circuit output, is characterized in that this gain control method comprises the following step to control the gain size of this amplifying circuit:

(A) export a count value continuously;

(B) produce a ramp signal according to this count value;

(C) receive this ramp signal and a control voltage signal, and at the magnitude of voltage of this control voltage signal and this ramp signal crossover, obtain this count value corresponding with this ramp signal as first count value and temporary, this first count value of mat determines the initial gain of this amplifying circuit again;

(D) detect voltage at the high voltage of this output signal greater than a default upper limit, or the low-voltage of this output signal is exported a detection signal, and is carried out next step when detecting voltage less than a default lower limit;

(E) receive this detection signal, with the accurate position of the direct current of adjusting this ramp signal; And

(F) obtain corresponding with this ramp signal and less than this count value of this first count value at this magnitude of voltage, upgrading this first count value as second count value, and this second count value of mat reduces this initial gain.

7. gain control method as claimed in claim 6 is characterized in that, this step (C) more comprises the following step:

Receive this ramp signal and this control voltage signal, and during in this magnitude of voltage, export one first latch-up signal at this control voltage signal and this ramp signal crossover; And

Receive this first latch-up signal, to obtain this count value corresponding with this ramp signal at this magnitude of voltage as this first count value and temporary, this first count value of mat determines this initial gain again.

8. gain control method as claimed in claim 6 is characterized in that, this step (F) more comprises the following step:

Export one second latch-up signal; And

Receive this second latch-up signal, obtaining corresponding with this ramp signal at this magnitude of voltage and less than this count value of this first count value, upgrading this first count value as this second count value, and this second count value of mat reduces this initial gain.

9. gain control method as claimed in claim 6 is characterized in that, when the waveform slope of this ramp signal is plus or minus, then in this step (E), increases or downgrade the accurate position of direct current of this ramp signal respectively, to reduce this initial gain.

10. gain control method as claimed in claim 6, it is characterized in that, when the high voltage of this output signal detects voltage greater than this upper limit, time interval between two time points that this output signal and this upper limit detection voltage interlock is longer, and then the amplitude of accurate adjustment of the direct current of this ramp signal is higher; When the low-voltage of this output signal detected voltage less than this lower limit, the time interval between two time points that this output signal and this upper limit detection voltage interlock was longer, and then the amplitude of accurate adjustment of the direct current of this ramp signal is higher.

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