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CN102024769B - 集成电路元件 - Google Patents

集成电路元件 Download PDF

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Publication number
CN102024769B
CN102024769B CN201010284468XA CN201010284468A CN102024769B CN 102024769 B CN102024769 B CN 102024769B CN 201010284468X A CN201010284468X A CN 201010284468XA CN 201010284468 A CN201010284468 A CN 201010284468A CN 102024769 B CN102024769 B CN 102024769B
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China
Prior art keywords
layer
copper
integrated circuit
metal layer
metallization structure
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CN102024769A (zh
Inventor
刘重希
黄见翎
何明哲
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

本发明一实施例提供一种集成电路元件，包括一半导体基板；一接垫部分，位于半导体基板上；以及一金属化结构，位于接垫部分上并与接垫部分电性连接，其中金属化结构包括一第一金属层，位于接垫部分上；一第一保护层，位于第一金属层上；以及一第二金属层，位于第一保护层上，其中第一保护层为一包含锗、硅、氮或前述的组合的含铜层。本发明有助于提高元件的可靠度以及增加使用寿命并降低制作成本。

Description

集成电路元件
技术领域
本发明涉及集成电路装置的制作方法，且特别涉及集成电路装置中的凸块结构(bump structure)的制作方法。
背景技术
现代的集成电路是由数以百万计的有源元件(例如晶体管)与电容所组成的。这些元件一开始彼此分离，但之后会彼此内连以形成功能电路(functional circuit)。典型的内连线结构包括横向的内连线(如金属线，导线)以及垂直的内连线(如导孔与接点)。内连线结构对于现代的集成电路的性能与密度的极限的影响性日益增加。在内连线结构的顶部上形成接垫，并使接垫暴露于各自的芯片表面。经由接垫可使芯片电性连接至封装基板或是另一芯片。接垫可用于打线接合工艺(wire bonding)或是倒装芯片接合工艺(flip-chip bonding)。由于晶片级芯片尺寸封装(Wafer level chip scalepackaging，WLCSP)的制作成本低且工艺相对简单，因此近来被广泛地使用。在典型的晶片级芯片尺寸封装工艺中，可于金属化层(metallization layer)上形成内连线结构，之后，可形成凸块下金属层(under-bump metallurgy，UBM)并安装焊料凸块。
在典型的凸块形成工艺中，可先形成凸块下金属层，然后，于凸块下金属层上形成凸块。凸块下金属层的工艺可包括形成一铜籽晶层(seed layer)，以及形成并图案化一位于铜籽晶层上的掩模，以使部分的铜籽晶层经由掩模的开口暴露出来。之后，进行一镀覆步骤以于铜籽晶层的外露的部分上镀一厚铜层。在形成与图案化掩模的过程中，可能会留下不需要的掩模残留物(通称为残渣，scum)，或是由掩模残留物所生成的图案化步骤的副产物。之后，进行一除残渣(descum)步骤以于铜镀覆之前移除残渣。传统工艺是利用效果强烈的四氟化碳(CF4)/氧气/氮气的除残渣工艺来移除残渣以及氧化物，然而，除残渣工艺会在晶片上残留残留氟离子，残留的氟离子会增加凸块下金属层在外界环境中氧化的速度，并且会向外扩散而污染其他周边的晶片。
此外，可以看出在除残渣步骤之后的等待时间(queue time，Q-time)相当短，有时候会少于12小时，其中等待时间是在铜镀覆之前个别的晶片可被储存而不会显著地劣化的时间。然而，在铜镀覆之前，可能需要四个工艺步骤，而这些工艺步骤可能需要较长的时间。在除残渣工艺后，即使尚在等待时间内，凸块下金属层仍然会被严重地氧化。若是等待时间届满而尚未进行铜镀覆工艺，则需要对个别的晶片再次除残渣(re-descum)以再次清洁(re-clean)晶片的表面。然而，再次除残渣会伤害掩模的轮廓与尺寸，也会伤害在金属表面上生成的导孔的形状与尺寸，因此导致凸块高度与凸块强度(bump strength)难以控制。这些挑战使得制作成本提高且凸块可靠度下降。
发明内容
为克服现有技术中的缺陷，本发明一实施例提供一种集成电路元件，包括一半导体基板；一接垫部分，位于半导体基板上；以及一金属化结构，位于接垫部分上并与接垫部分电性连接，其中金属化结构包括一第一金属层，位于接垫部分上；一第一保护层，位于第一金属层上；以及一第二金属层，位于第一保护层上，其中第一保护层为一包含锗、硅、氮或前述的组合的含铜层。
本发明一实施例提供一种集成电路元件，包括一半导体基板；一接垫部分，位于半导体基板上；一钝化层，位于接垫部分与半导体基板上，其中接垫部分包括一未被覆盖的部分，其未被钝化层所覆盖；一凸块下金属层，形成于接垫部分的未被覆盖的部分上；一保护层，位于凸块下金属层上；一含铜柱，形成于保护层上；以及一焊料层，位于含铜柱上，其中保护层为一含有锗、硅、氮或前述的组合的含铜层。
本发明一实施例提供一种集成电路元件，包括一半导体基板；一接垫部分，位于半导体基板上；一钝化层，位于接垫部分与半导体基板上，其中接垫部分包括一未被覆盖的部分，其未被钝化层所覆盖；一凸块下金属层，形成于接垫部分的未被覆盖的部分上；一保护层，位于凸块下金属层上；一含镍层，形成于保护层上；以及一焊料层，位于含镍层上，其中保护层为一含有锗、硅、氮或前述的组合的至少其中之一的含铜层。
本发明有助于提高元件的可靠度以及增加使用寿命并降低制作成本。
附图说明
图1A-图1H示出本发明一示范性的实施例的铜柱的工艺剖面图。
图2A-图2B示出本发明一示范性的实施例的铜柱的工艺剖面图。
图3A-图3C示出本发明一示范性的实施例的铜柱的工艺剖面图。
图4A-图4D示出本发明一示范性的实施例的铜柱的工艺剖面图。
图5A-图5C示出本发明一示范性的实施例的焊料凸块的工艺剖面图。
图6A-图6C示出本发明一示范性的实施例的焊料凸块的工艺剖面图。
其中，附图标记说明如下：
10～基板；
12～导电部分、接垫部分；
14～钝化层；
15～开口；
16～凸块下金属层、金属化层；
18～第一保护层、金属化层；
20～掩模层；
21～开口；
22～铜层、厚铜层、铜柱、金属化层；
22a～薄铜层；
24～盖层、金属化层；
26～焊料层；
26a～焊料凸块；
28、28”～介金属化合物层；
30～第二保护层；
32、32”、32a、32b～金属化结构、金属化层。
具体实施方式
为使本发明的上述目的、特征和优点能更明显易懂，下文特举一优选实施例，并配合附图，作详细说明如下。
在下文中，将详述许多特定的细节以使本公开可被彻底的了解。然而，本领域普通技术人员将可了解无需这些特定的细节即可执行本公开。在一些例子中，并未详细地描述公知的结构与工艺以避免不必要地模糊了本公开。
在全篇说明书中“一实施例”代表关于该实施例所述的一特定的特征、结构或是特性被包括在至少一实施例中。因此，在全篇说明书的各个地方，“在一实施例中”一词的意义是毋须皆与同一实施例有关。再者，可以任何适当的方法将特定的特征、结构或是特性组合成一或多个实施例。可以理解的是，下列附图并非按照比例示出，更确切地说，这些附图仅用以说明。
在此，图1A-图1H示出一示范性实施例的凸块的工艺剖面图。
在图1A中，一基板10例如可包括一半导体基板(例如是用于半导体集成电路制造中的半导体基板)，且可在其内及/或其上形成集成电路。半导体基板是指任何包括半导体材料的结构，半导体材料包括，但不限于，块状硅(bulk silicon)、半导体晶片、绝缘层上覆硅(silicon-on-insulator，SOI)基板或是硅锗基板。也可使用包括第三族、第四族与第五族的元素在内的其他半导体材料。在此使用的集成电路指的是具有多种个别的电路元件的电子电路(electronic circuit)，电路元件例如为晶体管、二极管、电阻、电容、电感以及其他的有源与无源半导体元件。基板10还包括层间介电层(inter-layerdielectric layer)以及位于集成电路上的金属化结构。在金属化结构中的层间介电层包括低介电常数(low-k)的介电材料、未掺杂的硅酸盐玻璃(un-dopedsilicate glass，USG)、氮化硅、氮氧化硅(silicon oxynitride)或是其他通常会使用的材料。低介电常数的介电材料的介电常数(k值，k value)可约小于3.9或是约小于2.8。金属化结构中的金属线可以是由铜或是铜合金所构成的。本领域普通技术人员将可了解金属化层的形成细节。
导电部分(conductive region)12为一形成于一顶层层间介电层中的顶金属化层，其为导电线路的一部分并具有一外露的表面，若是有需要，可对该外露的表面进行平坦化工艺，例如化学机械研磨(chemical mechanicalpolishing，CMP)。适于作为导电部分12的材料可包括，但不限定，例如铜、铝、铜合金或是其他容易移动的导电材料(mobile conductive material)，但其也可包括其他的材料，例如铜、银、金、镍、钨、前述的合金、及/或前述的多层。在一实施例中，导电部分12为一接垫部分12，其可用于接合工艺中以连接在个别芯片中的集成电路与外部的元件。
图1A也示出形成于基板10上的一钝化层(passivation layer)14。图案化钝化层14以形成一开口15，开口15暴露出一部分的导电部分12。在一实施例中，钝化层14是由无机材料所构成的，无机材料选自于未掺杂的硅酸盐玻璃、氮化硅、氮氧化硅、氧化硅及前述的组合。在另一实施例中，钝化层14是由一高分子层所构成的，其材质例如为环氧树脂(epoxy)、聚酰亚胺(polyimide)、苯环丁烯(benzocyclobutene，BCB)、聚苯恶唑(polybenzoxazole，PBO)及其相似物，但也可使用其他相对较软的(常为有机的)介电材料。
在图1B中，在前述的结构上形成一凸块下金属层16并使其电性连接导电部分12。凸块下金属层16形成在钝化层14与导电部分12的外露部上，并顺应性地设置于开口15的侧壁与底部上。在一实施例中，凸块下金属层16包括一扩散阻挡层(diffusion barrier layer)及/或一籽晶层。扩散阻挡层(也可称为粘着层，glue layer)是形成来覆盖开口15的侧壁与底部。扩散阻挡层可以是由钛所构成的，但其也可由其他的材料(例如氮化钛、钽、氮化钽或其相似物)所构成。扩散阻挡层的形成方法包括物理气相沉积(physicalvapor deposition，PVD)或是溅镀。籽晶层可为一铜籽晶层，其以物理气相沉积或是溅镀的方式形成在扩散阻挡层上。籽晶层可以是由铜合金所构成，铜合金包括银、铬、镍、锡、金或前述的组合。在一实施例中，凸块下金属层16为一铜/钛层。扩散阻挡层的厚度可约为1千～2千埃(Angstrom)，籽晶层的厚度可约等于3～7千埃，但其厚度也可大于或是小于前述厚度。本领域普通技术人员将可理解全篇说明书中所提及的尺寸皆仅用以举例说明，且尺寸将会随着集成电路的尺寸缩减而改变。
之后，在图1C中，一第一保护层18形成在凸块下金属层16上。第一保护层18是用来保护凸块下金属层16以使其免于在后续的工艺(例如光刻、烘烤及除残渣工艺)中受到化学侵袭及/或氧化。因此，第一保护层18也可被称为一抗氧化层(antioxidation layer)或是一氧化物阻挡层(oxide resistantlayer)。第一保护层18为一具有锗、硅、氮或前述组合的含铜层。在一实施例中，第一保护层18包括一氮化铜锗层(CuGeyNz layer)、一氮化铜硅层(CuSixNz layer)、一氮化铜硅锗层(CuSixGeyNz layer)或前述的组合。举例来说，第一保护层18的形成方法可包括通过将前述结构暴露于锗烷(GeH4)及/或硅烷(SiH4)且包含一额外的氨源气体的气氛中，然后进行一氨气等离子体处理(NH3 plasma treatment)，以选择性地在一铜层上形成(或成长、或沉积)至少一膜层(其包括铜、氮以及硅及/或锗)。
图1D示出在第一保护层18上形成一掩模层20并且将之图案化而具有一开口21，前述图案化的方法例如为曝光显影或是蚀刻，以暴露出第一保护层18的一部分用以形成凸块。在一实施例中，掩模层20的开口21位于钝化层14的开口15上。开口21的直径大于或等于开口15的直径。掩模层20可为一干膜(dry film)或是一光致抗蚀剂膜。在一实施例中，掩模层20为一干膜，且可由一有机材料(例如Ajinimoto buildup film，ABF)所构成。在另一实施例中，掩模层20是由光致抗蚀剂材料所构成。掩模层20的厚度可约大于5微米，或者甚至是约介于10微米与120微米之间。
然后，进行一烘烤工艺以固化掩模层20。可在一烘箱中进行烘烤工艺，工艺温度例如约等于130℃，且工艺时间约为1小时。残留物(未示出)可能会留在第一保护层18上，残留物可能是掩模层20的剩余的部分及/或在图案化掩模层的步骤中所产生的副产物。在一实施例中，在烘烤工艺之后，进行一除残渣步骤，以从第一保护层18上移除残留物。除残渣步骤的工艺气体可包括四氟化碳、氮气与氧气(此后称之为四氟化碳/氮气/氧气)。
请参照图1E，将一具有焊料可湿性(solder wettability)的导电材料部分填满于开口21中。在一实施例中，一铜层22形成于第一保护层18的外露部上以部分填满开口21。在本说明书中，“铜层”一词实质上包括一膜层，其包括纯铜、含有无法避免的杂质的铜以及含有少量的其他元素的铜合金，前述元素例如为钽、铟、锡、锌、锰、铬、钛、锗、锶(strontium)、铂、镁、铝或锆。铜层22的形成方法可包括溅镀、印刷(printing)、电镀、无电镀以及通常使用的化学气相沉积法。举例来说，可进行电化学镀(electro-chemical plating，ECP)来形成厚铜层22。在一示范性的实施例中，厚铜层22的厚度大于40微米。在其他实施例中，厚铜层22的厚度约为40～70微米，但厚铜层22的厚度也可以是大于或是小于前述数值。
然后，将一盖层(cap layer)24沉积于开口21中的厚铜层22上。盖层24可作为一阻挡层以防止厚铜层22中的铜扩散进入接合材料，例如焊料凸块(其用以接合基板10与外部的元件)。防止铜扩散可增加封装结构的可靠度与接合强度。盖层24可包括镍、锡、锡-铅、金、银、钯、铟、镍-钯-金、镍-金或是其他相似的材料或合金。在一实施例中，盖层24为以镀覆方式形成的一镍层、一金层或是一镍金层。在一示范性的实施例中，盖层24的厚度约为1～5微米，但其厚度也可大于或是小于前述厚度。之后，形成一焊料层26于盖层24上并使其位于开口21中。焊料层26可以是由锡(Sn)、锡银(SnAg)、锡-铅(Sn-Pb)、锡银铜(SnAgCu)(铜的重量百分比小于0.3％)、锡银锌(SnAgZn)、锡锌(SnZn)、锡铋-铟(SnBi-In)、锡-铟(Sn-In)、锡-金(Sn-Au)、锡铅(SnPb)、锡铜(SnCu)、锡锌铟(SnZnIn)、或锡银锑(SnAgSb)等所构成。在热退火的过程中焊料体积并未改变。
在图1F中，移除掩模层20。因此，暴露出第一保护层18的位于掩模层20下方的部分，并留下突出于第一保护层18的多层22、24、26堆叠结构。在本实施例中，掩模层20为一干膜，其可以碱性溶液移除。若是掩模层20是由光致抗蚀剂材料构成，则其可以湿式剥除工艺(wet stripping process)移除，湿式剥除工艺使用丙酮(acetone)、n-甲基吡咯烷酮(n-methylpyrrolidone，NMP)、二甲亚砜(dimethyl sulfoxide，DMSO)、胺乙氧基乙醇(aminoethoxy ethanol)及其相似物。然后，移除第一保护层18的外露部，之后，移除凸块下金属层16，以暴露出其下位于厚铜层22外围的钝化层14。因此，厚铜层22成为一铜突起结构(protrusion)。在一示范性的实施例中，就如同本领域普通技术人员所知的，移除凸块下金属层16的方法为干式蚀刻或湿式蚀刻，而移除的方法取决于凸块下金属层的金属(metallurgy)。举例来说，可使用一利用含氨基的酸(ammonia-based acid)的等向性湿式蚀刻(isotropic wet etching)，由于其工艺时间短故通常称为快速蚀刻(flashetching)。在下文中，铜突起结构也称为铜柱22，同时，金属化层24、22、18、16称为金属化结构32，金属化结构32突出于钝化层14并具有外露的侧壁。
图1G示出在焊料层26上进行一回焊工艺(reflow process)以于盖层24上形成一焊料凸块(solder bump)26a。在热循环(thermal cycling)的过程中，焊料层26中的锡容易移动而穿过裂缝或是其他的缺陷并与下层(例如盖层24及/或铜柱22)反应而形成一介金属化合物(intermetallic compound，IMC)，且可于焊料凸块26a与金属化结构32之间观察到此介金属化合物。在一实施例中，如图1H所示，介金属化合物层28形成于焊料凸块26a、盖层24以及铜柱22之间。若是盖层24包括镍，则可在界面形成一铜镍锡((Cu，Ni)xSny)介金属化合物层，其可具有可控制的厚度以及良好的粘着性。在介金属化合物形成的过程中可能会消耗盖层24。之后，切割基板10并将其封装至一封装基板(或另一芯片)上，在封装基板(或另一芯片)上的焊垫(pad)上安装有焊料凸块或是铜柱。
第一保护层18形成于凸块下金属层16与铜柱22之间以防止凸块下金属层的界面损坏，进而提升凸块的可靠度并扩大工艺容许度(processwindow)。由于第一保护层18可防止掩模层与导孔底部的金属表面损坏，因此，可使凸块下金属层具有优选的界面粘着性(interface adhesion)并减少产生于凸块下金属层中的孔洞(void)，如此一来，凸块的强度增加，凸块的高度变化减少，且凸块的共平面性(co-planarity)增加。再者，由于第一保护层18可防止金属氧化，因此，可减少焊料凸块与接垫之间的电性连接阻抗。此外，等待时间的限制可由少于12小时延长到大于24小时。加入凸块结构中的保护层18明显有助于提高元件的可靠度以及增加使用寿命(例如热循环、电力循环或是电迁移的表现)并降低制作成本。此外，在凸块下金属层、保护层与锡银铜接点(SAC joint)之间将可形成一均匀且平坦的介金属化合物层。
图2A与图2B示出一具有第二保护层30的铜柱结构的实施例剖面图，其中相同或相似于图1A至图1H的部分将不再赘述。请参照图2A，在形成焊料凸块26a之后，在金属化结构32的侧壁上形成一第二保护层30。第二保护层30也可形成在焊料凸块26a的表面上。第二保护层30可选择性地形成在金属化结构32的侧壁上，而不形成在钝化层14上。在一实施例中，第二保护层30为一含锡层。举例来说，可将凸块结构浸入一含锡的无电镀液中。一旦开始化学还原工艺，锡就会自动催化(autocatalytic)而沉积在突起结构上。无电镀液中的锡离子可通过溶液中的化学药剂而还原，并沉积在突起结构的表面上。由于镀覆反应仅发生在金属材料层的突起结构的表面上，因此，锡将不会镀覆在钝化层14的表面上。第二保护层30提供金属化结构32一密封的环境以防止金属化结构32氧化，且在后续的封装工艺中可提高金属化结构32与底胶(underfill)之间的粘着性。如图2B所示，在热循环的过程中，焊料层26中的锡易于移动以形成一介金属化合物层28，且可在焊料凸块26a与金属化结构32之间观察到介金属化合物层28。在一实施例中，介金属化合物层28形成在焊料凸块26a、盖层24以及铜柱22之间。介金属化合物层28为一铜镍锡((Cu，Ni)xSny)介金属化合物层，其可消耗部分或是整个盖层24。再者，第二保护层30中的锡容易移动以形成另一介金属化合物层28”，且可在金属化结构32的侧壁上观察到介金属化合物层28”。介金属化合物层28”为一铜锡介金属化合物层，其可消耗部分或是全部的第二保护层30。
图3A至图3C示出一实施例的凸块工艺的剖面图，其示出有非回焊的焊料层以及侧壁保护层，同时，其中相同或相似于图1A至图1H以及图2A至图2B的部分将不再赘述。请参照图3A与图3B，在移除掩模层20并蚀刻第一保护层18与凸块下金属层16之后，在金属化结构32的侧壁上形成第二保护层30，且不对焊料层26进行焊料回焊工艺。第二保护层30也可形成在焊料层26的表面上。在一实施例中，第二保护层30为一以浸锡工艺(tinimmersion process)形成的含锡层。如图3C所示，在热循环的过程中，可在焊料层26与金属化结构32之间观察到介金属化合物层28。在一实施例中，介金属化合物层28为一铜镍锡((Cu，Ni)xSny)介金属化合物层，其可消耗部分的盖层24。再者，可在金属化结构32的侧壁上观察到介金属化合物层28”。在一实施例中，介金属化合物层28”为一铜锡介金属化合物层，其可消耗部分或是全部的第二保护层30。
图4A至图4D示出一实施例的凸块工艺的剖面图，其并未于一铜柱上形成一盖层与一焊料层，其中相同或相似于图1A至图1H以及图2A至图2B的部分将不再赘述。请参照图4A与图4B，在掩模层20的开口21中形成厚铜层22之后，移除掩模层20，然后，蚀刻第一保护层18与凸块下金属层16的未被覆盖的部分以形成金属化结构32”。然后，在图4C中，第二保护层30形成在金属化结构32”的侧壁上。第二保护层30也可形成在突起结构的顶面上，也即在铜柱22的顶面上。在一实施例中，第二保护层30为一以浸锡工艺形成的含锡层。如图4D所示，在热循环的过程中，可在金属化结构32”的侧壁及/或顶面上观察到介金属化合物层28”。在一实施例中，介金属化合物层28”为一铜锡介金属化合物层，其可消耗部分或是全部的第二保护层30。
图5A至图5C示出一实施例的焊料凸块的工艺剖面图，其中相同或相似于图1A至图1H的部分将不再赘述。请参照图5A，一薄铜层22a设置于第一保护层18上并位于掩模层20的开口21中，之后，形成盖层24以及焊料层26。薄铜层22a的厚度小于铜柱22的厚度。薄铜层22a的厚度小于10微米。在一实施例中，薄铜层22a的厚度约为1～10微米，例如约为4～6微米，但前述厚度也可更大或是更小。薄铜层的形成方法可包括溅镀、印刷、电镀、无电镀以及常用的化学气相沉积法。之后，如图5B所示，在移除掩模层20之后，移除第一保护层18与凸块下金属层16的未被覆盖的部分以暴露出钝化层14。堆叠层24、22a、18、16可被称为金属化结构32a，其高度小于图1至图4所示出的金属化层32或32”。图5B也示出在焊料层26上进行回焊工艺以于盖层24上形成一焊料凸块26a。如图5C所示，在热循环的过程中，介金属化合物层28形成在焊料凸块26a与金属化结构32a之间。若是盖层24包括镍，则可在界面形成一铜镍锡介金属化合物层，其厚度可控制且具有良好的粘着性。在介金属化合物形成的过程中，可能会消耗盖层24。
图6A至图6C示出一实施例的焊料凸块的工艺剖面图，其中相同或相似于图5A至图5C的部分将不再赘述。请参照图6A，将盖层24沉积于掩模层20的开口21中的第一保护层18上，之后，在盖层24上形成焊料层26。如图6B所示，在移除掩模层20之后，蚀刻第一保护层18与凸块下金属层16的未被覆盖的部分，以暴露出钝化层14。堆叠层24、18、16可称为金属化结构32b，其高度小于图1至图4所示出的金属化层32或32”。之后，对焊料层26进行一焊料回焊工艺，以形成焊料凸块26a。如图6C所示，在热循环的过程中，会在焊料凸块26a与金属化结构32b之间形成介金属化合物层28。若是盖层24包括镍，则可在界面形成包含镍、锡及其他元素的介金属化合物层，介金属化合物层也许很薄且具有一平坦的表面。在介金属化合物形成的过程中，可能会消耗盖层24。
本发明虽以优选实施例公开如上，然其并非用以限定本发明的范围，任何所属技术领域中的普通技术人员，在不脱离本发明的精神和范围内，当可做些许的更动与润饰，因此本发明的保护范围当视随附的权利要求所界定的保护范围为准。

Claims (10)

1.一种集成电路元件，包括：
一半导体基板；
一接垫部分，位于该半导体基板上；以及
一金属化结构，位于该接垫部分上并与该接垫部分电性连接，其中该金属化结构包括：
一第一金属层，位于该接垫部分上；
一第一保护层，位于该第一金属层上；以及
一第二金属层，位于该第一保护层上，其中该第一保护层为氮化铜锗层、一氮化铜硅层、一氮化铜硅锗层或前述的组合。
2.如权利要求1所述的集成电路元件，其中该第一金属层包括钛层、铜层或前述的组合。
3.如权利要求1所述的集成电路元件，其中该第二金属层包括一含铜层，该含铜层的厚度大于40微米。
4.如权利要求1所述的集成电路元件，其中该第二金属层包括铜或镍，其中该第二金属层的厚度小于10微米。
5.如权利要求1所述的集成电路元件，其中该金属化结构还包括一位于第二金属层上的第三金属层。
6.如权利要求5所述的集成电路元件，其中该第三金属层包括镍。
7.如权利要求1所述的集成电路元件，还包括：
一第二保护层，位于该金属化结构的侧壁上。
8.如权利要求7所述的集成电路元件，其中该第二保护层包括锡。
9.如权利要求7所述的集成电路元件，还包括：
一焊料凸块，位于该金属化结构上并与该金属化结构电性连接。
10.如权利要求9所述的集成电路元件，还包括：
一介金属层，形成于该金属化结构与该焊料凸块之间。
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