CN102023927A - Flash memory control device and access method thereof - Google Patents

Abstract

The invention provides a flash memory control device and an access method thereof, wherein the method comprises the following steps: firstly, dividing the flash memory into at least one section according to a plurality of entity addresses of the flash memory; then, cutting out a data storage area and a blank queue area aiming at the section; then, establishing a corresponding lookup table according to a plurality of logical addresses of the flash memory, wherein the corresponding lookup table comprises a plurality of storage fields for storing the entity addresses of the data storage area; receiving an access command, wherein the access command writes stored data aiming at the target logic address; and finally, writing the stored data into the data block in the blank queue area, and updating the original entity address of the storage field corresponding to the target logical address in the corresponding lookup table into the entity address of the data block.

Description

Flash memory control device and access method thereof

technical field

The invention relates to a flash memory control device and an access method thereof, in particular to a flash memory wear leveling access method.

Background technique

Flash memory (flash memory) is a programmable (programmable) read only memory (read only memory, ROM), which allows multiple erasing and updating of stored data. This kind of flash memory is widely used in today's electronic products, and is commonly found in memory cards and flash drives as a medium for exchanging data between digital electronic products.

Usually, the flash memory is divided into multiple blocks, and each block is subdivided into many pages with the same capacity. Here, there is a limitation in the flash memory, that is, when updating data in the flash memory, it is necessary to erase the block where the address to be updated is located, and then write new data. However, there is a certain lifespan (erasing times) limit for erasing data on the flash memory. Moreover, a characteristic of flash memory is that the lifetime of each block in flash memory is independent. In order to effectively increase the service life of the flash memory, the prior art proposes a so-called wear leveling technology to make the times of erasing each block more even.

Please refer to FIGS. 1-3 , which are schematic diagrams of conventional wear-leveling access methods for flash memory. As shown in Figure 1, the flash memory 110 is divided into three partitions according to its physical addresses PBA0-PBA767, wherein the physical addresses PBA0-PBA255 are the first partition DIV0, the physical addresses PBA256-PBA511 are the second partition DIV1, and the physical addresses PBA512-PBA767 For the third division DIV2. Then, a corresponding lookup table 120 is established for the first partition DIV0 according to the logical addresses LBA0 - LBA255 . Since the first partition DIV0 includes 256 blocks (each physical address indicates a corresponding block). Wherein, the data stored in the lookup table 120 represents the corresponding relationship between the logical address and the physical address. In FIG. 1, the logical address LBA0 corresponds to the physical address PBA0.

Next, please refer to FIG. 2 , the existing wear leveling technology further includes establishing a blank queue area 130 , and the blank queue area 130 records physical addresses of blocks that have not been written into data. As shown in FIG. 2 , the corresponding lookup tables 120 on the left side of the figure are blank (not written), and the blank queue area 130 on the left side of the figure records that all physical addresses PBA0 ˜ PBAN are blank. However, after the access command 210 is executed, since the logical addresses LBA0-LBA2 are to be written, the flash memory provides physical addresses PBA0, PBA1, and PBA2 respectively corresponding to the logical addresses LBA0, LBA1, and LBA2 according to the records in the blank queue area 130 to store data. . Therefore, the storage fields corresponding to the logical addresses LBA0 , LBA1 , and LBA2 in the corresponding lookup table 120 on the right side of the figure are respectively stored in the physical addresses PBA0 , PBA1 , and PBA2 . The blank queue area 130 on the right side of the figure also removes the records of the original physical addresses PBA0 , PBA1 , and PBA2 .

Next, continue referring to FIG. 3 , at this time, the access command 310 is executed to update data for the logical addresses LBA1 and LBA2 . The physical addresses PBA3, PBA4 are provided according to the blank queue area 130 (as shown on the left side of the figure) to store data to be updated to the logical addresses LBA1, LBA2. And the physical addresses PBA0 and PBA1 are cleared and added to the blank queue area 130 (as shown on the right side of the figure).

This existing wear leveling technique requires a relatively large storage space because the physical addresses corresponding to the lookup table 120 and the flash memory must exist one-to-one, and the blank queue area 130 also requires a lot of storage space. In other words, this existing loss leveling technology requires relatively high cost.

Contents of the invention

The invention provides a flash memory access method, which effectively and evenly distributes the number of updates of each block in the flash memory.

The invention provides a flash memory control device, which effectively and evenly distributes the number of updates of each block in the flash memory.

The present invention proposes a flash memory access method. Firstly, the flash memory is divided into at least one segment according to multiple physical addresses of the flash memory. Next, a data storage area and a blank queue area are divided for the segment area. Then a corresponding lookup table is established according to the plurality of logical addresses of the flash memory, wherein the corresponding lookup table includes a plurality of storage fields for storing physical addresses of the data storage area. And, receiving an access command, wherein the access command writes the stored data for the target logical address. Finally, write the data stored in the data block in the blank queue area, and update the original physical address of the storage field corresponding to the target logical address in the lookup table to the physical address of the data block.

In an embodiment of the present invention, the above flash memory access method further includes clearing the original physical address corresponding to the data storage area that has been moved to the newly added blank block.

In an embodiment of the present invention, the above-mentioned blank queue area has a priority access order, and the priority access order of the data block is the highest.

In an embodiment of the present invention, the above flash memory access method further includes adding a newly added blank block to the blank queue area, and the priority access order of the newly added blank block is the lowest.

In an embodiment of the present invention, the above flash memory access method further includes removing data blocks from the empty queue area.

In an embodiment of the present invention, the above-mentioned corresponding lookup table is established in a storage device.

In an embodiment of the present invention, the above-mentioned storage device is a static memory or a dynamic memory.

In an embodiment of the present invention, the above flash memory access method further includes dynamically adjusting the storage capacity of the data storage area and the blank queue area.

The invention provides a flash memory control device for accessing flash memory, including a controller and a storage device. The controller is coupled to the flash memory. The controller divides the flash memory into at least one section according to multiple physical addresses of the flash memory, and divides a data storage area and a blank queue area for the section. The storage device is coupled to the controller and is used for establishing a corresponding lookup table according to a plurality of logical addresses of the flash memory. The corresponding lookup table includes a plurality of storage fields for storing the physical address of the data storage area. Wherein, when the controller receives the access command, and when the access command writes the stored data for the target logical address, the controller writes the stored data to the data block in the blank queue area, and puts the corresponding lookup table The original physical address of the storage field corresponding to the target logical address is updated to the physical address of the data block.

In an embodiment of the present invention, the above-mentioned flash memory control device further includes a transmission interface coupled to the controller for receiving access commands.

Based on the above, the present invention utilizes the preset corresponding lookup table and the blank queue area divided from the section area of the flash memory to update the data in the flash memory. Effective average number of updates for each block of flash memory. Moreover, there is no need for a corresponding lookup table equal to the total capacity of the flash memory, which effectively saves the area of the corresponding lookup table, thereby reducing costs.

In order to make the above-mentioned features and advantages of the present invention more comprehensible, the following specific embodiments are described in detail together with the accompanying drawings.

Description of drawings

1 to 3 are schematic diagrams of conventional wear leveling access methods for flash memory.

FIG. 4 is an action flowchart of an embodiment of the flash memory access method of the present invention.

5A-5B and FIG. 6 are operational schematic diagrams of an embodiment of the flash memory access method of the present invention.

FIG. 7 is a flash memory control device 700 according to an embodiment of the present invention.

Explanation of main reference signs:

110, 510, 740: flash memory; 120, 520: corresponding lookup table;

130, 512: blank queue area; 511: data storage area;

210, 310, 610: Access commands; 5121: Add a blank block;

700: flash memory control device; 710: controller;

720: storage device; 730: transmission interface;

ST0～ST3935: storage field;

PBA0～PBA8191, PBAN, PBAX: entity address;

DIV0～DIV2: partition; SEG0, SEG1: section;

LBA0～LBA255, LBAN, LBAm, LDIV0, LDIV15: logical address;

S410-S450: steps of the flash memory access method.

Detailed ways

Please refer to FIG. 4 below. FIG. 4 is an operation flow chart of an embodiment of the flash memory access method of the present invention. Please also refer to FIGS. 5A-5B and FIG. 6 at the same time. FIG. 5A-5B and FIG. 6 are operational diagrams of an embodiment of the flash memory access method of the present invention. In this embodiment, the steps include: firstly, dividing the flash memory into at least one section according to multiple physical addresses of the flash memory ( S410 ). As shown in FIG. 5A , the flash memory 510 has physical addresses PBA0 ˜ PBA8191 , and in this embodiment, each 4096 blocks (each physical address corresponds to a block) is divided into a segment. That is to say, PBA0-PBA4095 are divided into segment area SEG0, and PBA4096-PBA8191 are divided into segment area SEG1. Please pay special attention here that the number of sections does not necessarily have to be two as in this embodiment. In the present invention, the number of sections can be distinguished according to actual conditions (eg corresponding to the storage capacity of the lookup table), and is at least one.

Next, divide the data storage area and the blank queue area for the segment area (S420). As shown in FIG. 5A , the segment area SEG0 is divided into a data storage area 511 and a blank queue area 512 . Wherein, the data storage area 511 in this embodiment includes physical addresses PBA0-PBA3935, and the blank queue area 512 includes physical addresses PBA3936-PBA4095 as shown in FIG. 5B. Please note here that the division of the data storage area 511 and the blank queue area 512 shown in FIG. 5A and FIG. 5B is just an example, and does not limit the range of physical addresses included in the data storage area 511 and the blank queue area 512 . In fact, the division method of the data storage area 511 and the blank queue area 512 can be dynamically adjusted.

Then, a corresponding lookup table is established according to the plurality of logical addresses of the flash memory, wherein the corresponding lookup table includes a plurality of storage fields for storing physical addresses of the data storage area (S430). As shown in FIG. 5A , the corresponding lookup table 520 is established according to LBA0 ˜ LBA245 of logical addresses LDIV0 to LBA0 ˜ LBA245 of LDIV15 of the flash memory 510 . The corresponding lookup table 520 includes storage fields ST0 ˜ ST3935 , each of which stores physical addresses PBA0 ˜ PBA3935 in the data storage area 511 . For example, the data stored in the storage field ST0 corresponding to the LBA0 of the logical address LDIV0 in the lookup table 520 is the physical address PBA0, indicating that the LBA0 of the logical address LDIV0 corresponds to the physical address PBA0. It also indicates that when LBA0 of the logical address LDIV0 of the flash memory 510 is to be accessed, the physical address PBA0 of the flash memory 510 is actually accessed.

Here, the corresponding lookup table 520 is established in a storage device, and the storage device can be a dynamic memory or a static memory.

Please refer to Fig. 4 again, when receiving an access command (S440) for writing the stored data at the target logical address of the flash memory, then write the stored data to the data block in the blank queue area, and search the corresponding The original physical address of the storage field corresponding to the target logical address in the table is updated to the physical address of the data block (S450). That is to say, please refer to FIG. 6 , before receiving the access command 610 for storing data, the corresponding lookup table 520 stores physical addresses PBA0-PBA3935 of the data storage area 511, and the blank queue area 512 includes physical addresses PBA3936-PBA4095. When the access command 610 for storing data for the logical address LBA0 is received, one of the data blocks (the block with the physical address PBA3936 ) in the blank queue area 512 is provided for writing the stored data. At the same time, the original physical address (being physical address PBA0 ) corresponding to the storage field in LBA0 corresponding to the logical address LDIV0 in the lookup table 520 is also updated to the physical address PBA3936 .

In this way, in the corresponding lookup table 520 after the access command 610 is executed, the storage field corresponding to the LBA0 of the logical address LDIV0 records the physical address PBA3936, that is, the LBA0 of the logical address LDIV0 after the access command 610 is executed Changed to correspond to the physical address. In addition, the block with physical address PBA3936 in the blank queue area 512 before the access command 610 is executed is also removed from the blank queue area 512 after the access command 610 is executed.

Please note that after the access command 610 is executed, the block with the physical address PBA0 has no logical address corresponding to it. Therefore, the block with the physical address PBA0 can be cleared to be blank and become a newly added blank block 5121. And add the newly added blank block 5121 into the blank queue area 512 .

In addition, in order to sequentially select blocks from the blank queue area 512 to provide a deposit command to write deposit data. The blank queue area 512 has a priority access order. As shown in FIG. 6 , the block to the left of the blank queue area 512 has a higher priority access sequence. On the contrary, the block on the right of the blank queue area 512 has a lower priority access sequence. Moreover, when it is necessary to provide blocks from the blank queue area 512 for writing and storing data, the selected data block is the one with the highest priority access order in the blank queue area 512 . And the priority access sequence of newly added newly added blank blocks is the lowest.

From the above description, it is not difficult to find that this embodiment effectively evenly distributes the clearing and updating operations of the blocks of each physical address to achieve the requirement of equal wear.

An embodiment of the flash memory control device for accessing flash memory of the present invention is presented below for illustration, so that those skilled in the art can easily understand and implement the present invention.

Please refer to FIG. 7 , which shows a flash memory control device 700 according to an embodiment of the present invention. The flash memory control device 700 is coupled to the flash memory 740 and controls access to the flash memory 740 . The flash memory control device 700 includes a controller 710 , a storage device 720 and a transmission interface 730 . Wherein, the controller 710 is coupled to the flash memory 740 . And the controller 710 divides the flash memory into at least one segment area according to multiple physical addresses of the flash memory 740 , and divides the data storage area and the blank queue area for the segment area.

The storage device 720 is coupled to the controller 710 . The storage device 720 is used for establishing a corresponding lookup table according to a plurality of logical addresses of the flash memory, wherein the corresponding lookup table includes a plurality of storage fields. These storage fields are used to store the physical address of the data storage area.

In addition, when the controller 710 receives an access command for writing data into the target logic address, the controller 710 writes the data into the data block in the blank queue area, and puts the corresponding target logic in the corresponding lookup table The original physical address of the storage field of the address is updated to the physical address of the data block. In addition, the controller 710 also clears the newly added blank block corresponding to the original physical address in the data storage area and adds the newly added blank block to the empty queue area. The above data blocks are removed from the empty queue area.

The above details about the operation of the flash memory control device 700 have been introduced in detail in the description of the embodiment of the flash memory access method of the present invention. Therefore, details of the operation of the flash memory control device 700 will not be repeated here.

It should be noted that the flash memory controller 700 also includes a transmission interface 730 . The transmission interface 730 is coupled to the controller 710 for receiving an access command sent by a user to the flash memory 740 . Of course, the transmission interface 730 can also be used to transmit data stored in or read from the flash memory 740 . The functions and construction methods of this transmission interface are well known to those skilled in the art, and will not be repeated here.

To sum up, the present invention utilizes the set corresponding lookup table and the blank queue area divided from the flash memory to update the data of the flash memory. There is no need for a one-to-one correspondence lookup table with the physical address of the flash memory, and no additional memory is needed to establish a blank queue area. Effectively, under the minimum circuit area, the wear-level access operation of the flash memory is achieved.

Finally, it should be noted that: the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that: it can still be Modifications are made to the technical solutions described in the foregoing embodiments, or equivalent replacements are made to some of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the various embodiments of the present invention.

Claims (16)

1. flash memory access method comprises:

Cutting apart this flash memory according to a plurality of physical address of this flash memory is at least one joint district;

Be partitioned into a region of data storage and a blank formation region at this joint district;

Set up a corresponding look-up table according to a plurality of logical addresses of this flash memory, wherein should comprise a plurality of storage fields in the correspondence look-up table, in order to store the described physical address of this region of data storage;

Receive an access command, wherein this access command writes one at a target logic address and deposits data in; And

Write this and deposit the block of data to this blank formation region in, and the physical address that in this correspondence look-up table an original physical address of this storage field that should the target logic address is updated to this block.

2. flash memory access method according to claim 1 wherein also comprises:

Remove in this region of data storage a newly-increased blank block that should original physical address.

3. flash memory access method according to claim 2 wherein should have priority memory access order in the blank formation region, and this priority memory access of this block is in proper order for the highest.

4. flash memory access method according to claim 3 wherein also comprises:

Increase should newly-increased blank block to this blank formation region, and this priority memory access that should newly-increased blank block is minimum in proper order.

5. flash memory access method according to claim 1 wherein also comprises:

From this blank formation region, remove this block.

6. flash memory access method according to claim 1 wherein should be based upon in the storage device by the correspondence look-up table.

7. flash memory access method according to claim 6, wherein this storage device is static memory or Dram.

8. flash memory access method according to claim 1 wherein also comprises:

Dynamically adjust the memory capacity of this region of data storage and this blank formation region.

9. flash memory control device in order to access one flash memory, comprising:

One controller couples this flash memory, and it is at least one joint district that this controller is cut apart this flash memory according to a plurality of physical address of this flash memory, and is partitioned into a region of data storage and a blank formation region at this joint district; And

One storage device couples this controller, in order to set up a corresponding look-up table according to a plurality of logical addresses of this flash memory, wherein should comprise a plurality of storage fields in the correspondence look-up table, and described storage field is in order to store the described physical address of this region of data storage;

Wherein, when this controller receives an access command, and this access command is when writing this and deposit data at this target logic address, this controller writes this and deposits the block of data to this blank formation region in, and the physical address that in this correspondence look-up table an original physical address of this storage field that should the target logic address is updated to this block.

10. flash memory control device according to claim 9, wherein this controller also comprises:

Remove in this region of data storage a newly-increased blank block that should original physical address.

11. flash memory control device according to claim 10 wherein should have priority memory access order in the blank formation region, and this priority memory access of this block is in proper order for the highest.

12. flash memory control device according to claim 11, wherein this controller also comprises:

Increase should newly-increased blank block to this blank formation region, and this priority memory access that should newly-increased blank block is minimum in proper order.

13. flash memory control device according to claim 9, wherein this controller also comprises:

From this blank formation region, remove this block.

14. flash memory control device according to claim 9, wherein this storage device is static memory or Dram.

15. flash memory control device according to claim 9, wherein this controller also comprises:

Dynamically adjust the memory capacity of this region of data storage and this blank formation region.

16. flash memory control device according to claim 9 wherein also comprises:

One transmission interface couples this controller, in order to receive this access command.

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