CN102016614B - 选择性地使用或绕过远程管脚电子设备块来测试至少一个待测设备的方法和装置 - Google Patents
选择性地使用或绕过远程管脚电子设备块来测试至少一个待测设备的方法和装置 Download PDFInfo
- Publication number
- CN102016614B CN102016614B CN200980114118.4A CN200980114118A CN102016614B CN 102016614 B CN102016614 B CN 102016614B CN 200980114118 A CN200980114118 A CN 200980114118A CN 102016614 B CN102016614 B CN 102016614B
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- CN
- China
- Prior art keywords
- node
- test
- tester
- signal
- pin electronics
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Classifications
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3172—Optimisation aspects, e.g. using functional pin as test pin, pin multiplexing
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/31712—Input or output aspects
Landscapes
- Engineering & Computer Science (AREA)
- General Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Tests Of Electronic Circuits (AREA)
Abstract
Description
Claims (11)
Applications Claiming Priority (5)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US12/035,378 US8384410B1 (en) | 2007-08-24 | 2008-02-21 | Parallel test circuit with active devices |
US12/035,378 | 2008-02-21 | ||
US12/276,290 | 2008-11-21 | ||
US12/276,290 US7928755B2 (en) | 2008-02-21 | 2008-11-21 | Methods and apparatus that selectively use or bypass a remote pin electronics block to test at least one device under test |
PCT/US2009/034895 WO2009105762A2 (en) | 2008-02-21 | 2009-02-23 | Methods and apparatus that selectively use or bypass a remote pin electronics block to test at least one device under test |
Publications (2)
Publication Number | Publication Date |
---|---|
CN102016614A CN102016614A (zh) | 2011-04-13 |
CN102016614B true CN102016614B (zh) | 2014-07-16 |
Family
ID=40986254
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN200980114118.4A Active CN102016614B (zh) | 2008-02-21 | 2009-02-23 | 选择性地使用或绕过远程管脚电子设备块来测试至少一个待测设备的方法和装置 |
Country Status (6)
Country | Link |
---|---|
US (1) | US7928755B2 (zh) |
JP (1) | JP2011513713A (zh) |
KR (1) | KR20100120692A (zh) |
CN (1) | CN102016614B (zh) |
TW (1) | TWI463152B (zh) |
WO (1) | WO2009105762A2 (zh) |
Families Citing this family (14)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7898286B2 (en) * | 2009-02-11 | 2011-03-01 | International Business Machines Corporation | Critical path redundant logic for mitigation of hardware across chip variation |
KR101133030B1 (ko) * | 2010-12-08 | 2012-04-04 | 인텔릭스(주) | 디스크리트 자가 진단 시스템 |
KR101218096B1 (ko) | 2010-12-17 | 2013-01-03 | 에스케이하이닉스 주식회사 | 반도체 장치의 테스트 방법 및 반도체 장치의 테스트 시스템 |
TWI456216B (zh) * | 2012-07-19 | 2014-10-11 | Novatek Microelectronics Corp | 積體電路及其測試系統 |
US10161993B2 (en) | 2013-02-21 | 2018-12-25 | Advantest Corporation | Tester with acceleration on memory and acceleration for automatic pattern generation within a FPGA block |
US9952276B2 (en) | 2013-02-21 | 2018-04-24 | Advantest Corporation | Tester with mixed protocol engine in a FPGA block |
US11009550B2 (en) | 2013-02-21 | 2021-05-18 | Advantest Corporation | Test architecture with an FPGA based test board to simulate a DUT or end-point |
US10162007B2 (en) * | 2013-02-21 | 2018-12-25 | Advantest Corporation | Test architecture having multiple FPGA based hardware accelerator blocks for testing multiple DUTs independently |
US10976361B2 (en) | 2018-12-20 | 2021-04-13 | Advantest Corporation | Automated test equipment (ATE) support framework for solid state device (SSD) odd sector sizes and protection modes |
US11137910B2 (en) | 2019-03-04 | 2021-10-05 | Advantest Corporation | Fast address to sector number/offset translation to support odd sector size testing |
US11237202B2 (en) | 2019-03-12 | 2022-02-01 | Advantest Corporation | Non-standard sector size system support for SSD testing |
US10884847B1 (en) | 2019-08-20 | 2021-01-05 | Advantest Corporation | Fast parallel CRC determination to support SSD testing |
US11313903B2 (en) * | 2020-09-30 | 2022-04-26 | Analog Devices, Inc. | Pin driver and test equipment calibration |
US11662380B2 (en) * | 2021-05-13 | 2023-05-30 | Apple Inc. | Built-in self-test for die-to-die physical interfaces |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6275962B1 (en) * | 1998-10-23 | 2001-08-14 | Teradyne, Inc. | Remote test module for automatic test equipment |
US6275023B1 (en) * | 1999-02-03 | 2001-08-14 | Hitachi Electronics Engineering Co., Ltd. | Semiconductor device tester and method for testing semiconductor device |
CN1666110A (zh) * | 2002-07-08 | 2005-09-07 | 皇家飞利浦电子股份有限公司 | 具有测试单元的电子电路 |
Family Cites Families (13)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5471481A (en) | 1992-05-18 | 1995-11-28 | Sony Corporation | Testing method for electronic apparatus |
EP0882991B1 (en) | 1997-05-22 | 1999-03-17 | Hewlett-Packard Company | Decompression circuit |
JP2000065899A (ja) | 1998-08-14 | 2000-03-03 | Sony Corp | 半導体装置およびそのデータ書き換え方法 |
US6392427B1 (en) | 1998-12-21 | 2002-05-21 | Kaitech Engineering, Inc. | Testing electronic devices |
US6499121B1 (en) | 1999-03-01 | 2002-12-24 | Formfactor, Inc. | Distributed interface for parallel testing of multiple devices using a single tester channel |
US7124221B1 (en) | 1999-10-19 | 2006-10-17 | Rambus Inc. | Low latency multi-level communication interface |
TW440984B (en) | 2000-03-08 | 2001-06-16 | Via Tech Inc | Chip testing system and testing method |
JPWO2002057921A1 (ja) | 2001-01-19 | 2004-07-22 | 株式会社日立製作所 | 電子回路装置 |
US7395476B2 (en) | 2004-10-29 | 2008-07-01 | International Business Machines Corporation | System, method and storage medium for providing a high speed test interface to a memory subsystem |
US7312617B2 (en) | 2006-03-20 | 2007-12-25 | Microprobe, Inc. | Space transformers employing wire bonds for interconnections with fine pitch contacts |
US7590903B2 (en) | 2006-05-15 | 2009-09-15 | Verigy (Singapore) Pte. Ltd. | Re-configurable architecture for automated test equipment |
US7421632B2 (en) | 2006-05-31 | 2008-09-02 | Verigy (Singapore) Pte. Ltd. | Mapping logic for controlling loading of the select ram of an error data crossbar multiplexer |
JP2008042376A (ja) | 2006-08-03 | 2008-02-21 | Fujitsu Ltd | 双方向伝送回路及び送受信素子 |
-
2008
- 2008-11-21 US US12/276,290 patent/US7928755B2/en active Active
-
2009
- 2009-02-23 CN CN200980114118.4A patent/CN102016614B/zh active Active
- 2009-02-23 KR KR1020107021206A patent/KR20100120692A/ko not_active Ceased
- 2009-02-23 WO PCT/US2009/034895 patent/WO2009105762A2/en active Application Filing
- 2009-02-23 TW TW098105627A patent/TWI463152B/zh active
- 2009-02-23 JP JP2010547840A patent/JP2011513713A/ja active Pending
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6275962B1 (en) * | 1998-10-23 | 2001-08-14 | Teradyne, Inc. | Remote test module for automatic test equipment |
US6275023B1 (en) * | 1999-02-03 | 2001-08-14 | Hitachi Electronics Engineering Co., Ltd. | Semiconductor device tester and method for testing semiconductor device |
CN1666110A (zh) * | 2002-07-08 | 2005-09-07 | 皇家飞利浦电子股份有限公司 | 具有测试单元的电子电路 |
Also Published As
Publication number | Publication date |
---|---|
WO2009105762A3 (en) | 2009-12-30 |
US7928755B2 (en) | 2011-04-19 |
TW200941015A (en) | 2009-10-01 |
JP2011513713A (ja) | 2011-04-28 |
TWI463152B (zh) | 2014-12-01 |
KR20100120692A (ko) | 2010-11-16 |
CN102016614A (zh) | 2011-04-13 |
WO2009105762A2 (en) | 2009-08-27 |
US20090212799A1 (en) | 2009-08-27 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
C06 | Publication | ||
PB01 | Publication | ||
C10 | Entry into substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
ASS | Succession or assignment of patent right |
Owner name: ADVANTEST (SINGAPORE) PTE. LTD. Free format text: FORMER OWNER: VERIGY (SINGAPORE) PTE. LTD. Effective date: 20120426 |
|
C41 | Transfer of patent application or patent right or utility model | ||
TA01 | Transfer of patent application right |
Effective date of registration: 20120426 Address after: Singapore Singapore Applicant after: Verigy Pte Ltd Singapore Address before: Singapore Singapore Applicant before: Inovys Corp. |
|
C14 | Grant of patent or utility model | ||
GR01 | Patent grant | ||
ASS | Succession or assignment of patent right |
Owner name: ADVANTEST CORP. Free format text: FORMER OWNER: ADVANTEST (CHINA) CO., LTD. Effective date: 20150508 |
|
C41 | Transfer of patent application or patent right or utility model | ||
TR01 | Transfer of patent right |
Effective date of registration: 20150508 Address after: Tokyo, Japan, Japan Patentee after: ADVANTEST CORP Address before: Singapore Singapore Patentee before: Verigy Pte Ltd Singapore |