CN102014232A - Light-emitting device, print head and image forming device - Google Patents

Abstract

The invention discloses a light-emitting device, a print head and an image forming device. The light-emitting device includes: a self-scanning light-emitting element array including: light-emitting elements; memory elements; and switch elements; and a light-up controller supplying a transfer signal setting ON of the switch elements, a memory signal causing, in a case where a switch element corresponding to a light-emitting element forming a group is set at the ON state, a corresponding memory element to be temporarily changed from OFF to ON if the light-emitting element is to light up, and the corresponding memory element to be kept in OFF if the light-emitting element is not to light up, and then causing the memory element having been temporarily changed to the ON state to be temporarily set at ON again, and a light-up signal for each group, the light-up signal causing a light-emitting element to be set at ON after causing a memory element to be set at ON.

Description

Light emitting device, print head, and image forming apparatus

technical field

The invention relates to a light-emitting device, a driving method of a self-scanning light-emitting element array, a printing head, and an image forming device. the

Background technique

In an electrophotographic image forming apparatus such as a printer, copier or facsimile, an image is formed on recording paper in the following manner. First, an electrostatic latent image is formed on a uniformly charged photoreceptor by causing an optical recording unit to emit light to transfer image information to the photoreceptor. Subsequently, the electrostatic latent image is made visible by development with toner. Finally, the toner image is transferred and fixed onto the recording paper. In addition to an optical scanning recording unit that performs exposure by performing laser scanning in the first scanning direction using a laser beam, a recording device using an LED print head (LPH) below has been adopted as such an optical recording unit in recent years to adapt to light-reduction. The need for small device sizes. This LPH includes a large number of light emitting diodes (LEDs) arrayed in the first scanning direction as light emitting elements. the

Japanese Patent Application Laid-Open No. 2004-181741 describes a self-scanning light-emitting element array (SLED: self-scanning light-emitting device) chip in which a displacement portion and a light-emitting portion are separated from each other, and the chip has diode coupling. In the SLED chip of this structure, the thyristors in the shifting part do not have corresponding light-emitting thyristors connected thereto, so as to realize multiple light emission and interrupt data writing in progress. the

In a recording apparatus using an LPH with SLEDs, use of an SLED chip that realizes multiple light emission causes an increase in power consumption. the

An object of the present invention is to provide a light-emitting device using a self-scanning light-emitting element array that realizes multiple light emission, a driving method of the self-scanning light-emitting element array, a print head, and an image forming apparatus that suppress an increase in power consumption. the

Contents of the invention

According to the first aspect of the present invention, there is provided a light-emitting device, comprising: a self-scanning light-emitting element array; and a lighting controller, the self-scanning light-emitting element array comprising: a plurality of light-emitting elements arranged in a straight line; a plurality of memory elements , which is set to correspond to each light-emitting element and electrically connected to each light-emitting element, each memory element is set in any one of the on-state and the off-state, and the case of being set in the off-state In contrast, the plurality of memory elements make it easy for each light emitting element to be set in an on state when being set in an on state; and a plurality of switching elements provided corresponding to the respective memory elements and Electrically connected to the respective memory elements, each switching element is set in any one of an ON state and an OFF state, and the plurality of switching elements are set to allow sequential shifting of the ON state from one end side to the other. On one end side, the plurality of switching elements make it easy for each memory element to be set in the on state when being set in the on state compared to the case in the off state; the lighting controller includes : a transfer signal generating unit that provides a transfer signal to the plurality of switching elements, the transfer signal setting the plurality of switching elements thereby allowing a conduction state to sequentially move from one end side to the other end side; a memory signal generating unit which supplies a memory signal to a plurality of memory elements corresponding to a plurality of light emitting elements of one of a plurality of groups into which the plurality of light emitting elements are divided, at switches corresponding to the light emitting elements forming the group When an element is set in a conductive state, if it is desired to light up a light-emitting element corresponding to the switching element, the memory signal causes the memory element corresponding to the switching element set in the conductive state to temporarily From the off state to the on state, and if the light emitting element corresponding to the switching element is not intended to be lit, the memory signal causes the memory element corresponding to the switching element set in the on state to remain in the off state. an off state, and then temporarily set the memory element that has been temporarily turned on into the on state again in the on state; and a lighting signal generating unit that supplies a lighting signal to the plurality of light emitting elements for each group The lighting signal causes the light emitting element to be turned on to be set in an on state after the memory element corresponding to the light emitting element to be turned on is set in an on state. the

According to the second aspect of the present invention, in the first aspect of the light-emitting device, the self-scanning light-emitting element array further includes a plurality of canceling elements set to correspond to the respective memory elements and electrically connected to the respective memory elements. memory element, and the lighting controller further includes an erasing signal generating unit that provides an erasing signal to the plurality of erasing elements, and the light-emitting element to be lit in the group is set After the conduction state, the deactivation signal prevents the memory element corresponding to the desired light-emitting element from being set in the conduction state. the

According to a third aspect of the present invention, in any one of the first and second aspects of the light-emitting device, the self-scanning light-emitting element array further includes a plurality of holding elements, and the plurality of holding elements are arranged on each light-emitting element and each Between the memory elements thereby corresponding to each light emitting element and each memory element, and electrically connected to each light emitting element and each memory element, compared with the case of an off state, in the case where each memory element is set in an on state Next, the plurality of holding elements make it easy to turn on each light-emitting element, and the lighting controller further includes a holding signal generation unit that supplies a holding signal to the plurality of holding elements so that After the memory element corresponding to the light-emitting element in the group to be turned on is set in the conductive state, the hold signal causes the hold element corresponding to the memory element in the conductive state to be set in the conductive state. the

According to the fourth aspect of the present invention, there is provided a light-emitting device, including: a self-scanning light-emitting element array; and a lighting controller, the self-scanning light-emitting element array includes: a substrate; a plurality of light-emitting thyristors formed on the a plurality of memory thyristors formed on the substrate and arranged to correspond to the respective light-emitting thyristors and electrically connected to the respective light-emitting thyristors, and each memory thyristor is set in an on state and an off state. The plurality of memory thyristors change the respective threshold voltages of the plurality of light-emitting thyristors to values that, compared with the case of being set in the off state, become In the case of an on state, the value makes it easy for each light emitting thyristor to be set in an on state; and a plurality of transfer thyristors, which are formed on the substrate and arranged to correspond to each memory thyristor, and are electrically connected to each memory thyristors each of which is set in any one of an ON state and an OFF state, the plurality of transfer thyristors being set to allow the ON state to sequentially shift from one end side to the other end side, and changing the respective threshold voltages of the plurality of memory thyristors to values that allow the respective memory thyristors to be easily set at a conduction state; the lighting controller includes: a transfer signal generating unit that provides a transfer signal to the plurality of transfer thyristors, the transfer signal sets the plurality of transfer thyristors to allow the conduction state from one end side sequentially moving to the other end side; a memory signal generation unit that supplies a memory signal to a plurality of memory thyristors corresponding to a plurality of light emitting thyristors of one of a plurality of groups into which the plurality of light emitting thyristors are divided, at the same time as In case the transfer thyristors corresponding to the light emitting thyristors forming the group are set in a conduction state, if it is desired to turn on the light emitting thyristors corresponding to the transfer thyristors, the memory signal causes The memory thyristor corresponding to the transfer thyristor of the on state is temporarily changed from the off state to the on state, and if the light-emitting thyristor corresponding to the transfer thyristor is not to be lighted, the memory signal makes the same as set in the on state The memory thyristor corresponding to the transfer thyristor is kept in an off state, and then the memory thyristor that has been temporarily turned into an on state is temporarily set in an on state again; A lighting signal is supplied to the plurality of light-emitting thyristors, the lighting signal causes the light-emitting thyristor to be turned on to be turned on after setting a memory thyristor corresponding to the light-emitting thyristor to be turned on set in the on state. the

According to a fifth aspect of the present invention, in the fourth aspect of the light-emitting device, the self-scanning light-emitting element array further includes a plurality of cancellation diodes, and the plurality of cancellation diodes are arranged to correspond to the respective memory thyristors and electrically connected to the respective memory thyristors. thyristors, and the lighting controller further includes a cancellation signal generation unit that supplies cancellation signals to the plurality of cancellation diodes, and the light-emitting thyristors to be turned on in the group are set at After the conduction state, the deactivation signal prevents the memory thyristor corresponding to the light emitting thyristor to be turned on from being set in the conduction state. the

According to the sixth aspect of the present invention, in the fifth aspect of the light-emitting device, the canceling diodes of the self-scanning light-emitting element array are Schottky diodes. the

According to a seventh aspect of the present invention, in any one of the fourth to sixth aspects of the light-emitting device, the self-scanning light-emitting element array further includes a plurality of holding thyristors, and the plurality of holding thyristors are formed on the substrate , and disposed between each light-emitting thyristor and each memory thyristor so as to correspond to each light-emitting thyristor and each memory thyristor, and electrically connected to each light-emitting thyristor and each memory thyristor, the plurality of holding thyristors connects the plurality of light-emitting thyristors The respective threshold voltages of each of the light-emitting thyristors become values such that the respective light-emitting thyristors are easily set in the on-state when the plurality of memory thyristors are set in the on-state compared to the off-state. the on state, and the lighting controller further includes a holding signal generating unit that provides a holding signal to the plurality of holding thyristors so as to be in phase with the light-emitting thyristor to be turned on in the group. After the corresponding memory thyristor is set in the conducting state, the holding signal causes the holding thyristor corresponding to the memory thyristor in the conducting state to be set in the conducting state. the

According to an eighth aspect of the present invention, there is provided a driving method of a self-scanning light-emitting element array, the self-scanning light-emitting element array comprising: a plurality of light-emitting elements arranged in a straight line; Corresponding to and electrically connected to each light-emitting element, each memory element is set in any one of the on state and the off state, compared with the case of being set in the off state, the In the case of a state, the plurality of memory elements makes it easy to set each light emitting element in a conduction state; and a plurality of switch elements are arranged to correspond to each memory element and are electrically connected to each memory element, each switch element are set in any one of the on-state and the off-state, the plurality of switching elements are set to allow the on-state to move sequentially from one end side to the other end side, compared to the case of the off-state , the plurality of switching elements make it easy for each memory element to be set in a conductive state when being set in a conductive state, the driving method includes: supplying a transfer signal to the plurality of switching elements, causing the conduction states of the plurality of switching elements to sequentially shift from one end side to the other end side; supplying a memory signal to a plurality of light emitting elements corresponding to one of a plurality of groups into which the plurality of light emitting elements are divided a plurality of memory elements, and in a case where the switching elements corresponding to the light emitting elements forming the group are set in a conductive state, if it is desired to turn on the light emitting elements corresponding to the switching elements, the A memory signal temporarily changes a memory element corresponding to a switching element set in an on state from an off state to an on state, and if it is not desired to light up a light emitting element corresponding to the switching element, the memory signal causing the memory element corresponding to the switching element set in the on state to be kept in the off state, and then causing the memory element which has been temporarily turned into the on state to be temporarily set in the on state again; and for each group supplying a lighting signal to the plurality of light emitting elements, the lighting signal causes the light emitting element to be turned on to emit light after setting a memory element corresponding to the light emitting element to be turned on in a conductive state element is set in the conduction state. the

According to the ninth aspect of the present invention, in the eighth aspect of the driving method of the self-scanning light-emitting element array, the self-scanning light-emitting element array further includes a plurality of elimination elements, and the plurality of elimination elements are arranged to correspond to the respective memory elements and electrically connected to each memory element, and the driving method further includes: providing an erasing signal to the plurality of erasing elements, after the light-emitting element to be lighted in the group is set in a conduction state, the The cancel signal prevents the memory element corresponding to the desired light-emitting element from being set in a conductive state. the

According to the tenth aspect of the present invention, in any one of the eighth to tenth aspects of the driving method of the self-scanning light-emitting element array, the self-scanning light-emitting element array further includes a plurality of holding elements, and the plurality of holding elements Provided between each light emitting element and each memory element so as to correspond to each light emitting element and each memory element, and electrically connected to each light emitting element and each memory element, compared with the case of an off state, when each memory element is set The plurality of holding elements make it easy to light up each light-emitting element under the condition of being in the conduction state, and the driving method further includes: supplying a holding signal to the plurality of holding elements so as to be compatible with the group After the memory element corresponding to the light-emitting element to be turned on is set in the ON state, the hold signal causes the hold element corresponding to the memory element in the ON state to be set in the ON state. the

According to an eleventh aspect of the present invention, there is provided a print head, including: an exposure unit; and an optical unit, which exposes an image carrier and includes: a self-scanning light-emitting element array; and a lighting controller, the The self-scanning light-emitting element array includes: a plurality of light-emitting elements arranged in a straight line; a plurality of memory elements, which are arranged to correspond to each light-emitting element and electrically connected to each light-emitting element, and each memory element is set in a conduction state In either state of the off state, the plurality of memory elements make it easy for each light emitting element to be set in the case of being set in the on state as compared with the case of being set in the off state. a conduction state; and a plurality of switching elements, which are arranged to correspond to the respective memory elements and electrically connected to the respective memory elements, each switching element being set in any one of the conduction state and the off state, so The plurality of switching elements are set to allow the conduction state to sequentially move from one end side to the other end side, and in the case of being set in the conduction state, the plurality of switching elements making it easy for each memory element to be set in a conduction state; the lighting controller includes: a transfer signal generation unit that provides a transfer signal to the plurality of switch elements, the transfer signal sets the plurality of switches an element thereby allowing the conduction state to sequentially move from one end side to the other end side; a memory signal generating unit which supplies a memory signal to a plurality of light emitting elements corresponding to one of a plurality of groups into which the plurality of light emitting elements are divided; For the corresponding plurality of memory elements, in the case where the switching elements corresponding to the light emitting elements forming the group are set in a conductive state, if it is desired to turn on the light emitting elements corresponding to the switching elements, the The memory signal causes the memory element corresponding to the switching element set in the on state to temporarily change from the off state to the on state, and if the light emitting element corresponding to the switching element is not to be turned on, the memory a signal to keep the memory element corresponding to the switching element set in the on state in the off state, and then temporarily set the memory element which has been temporarily turned into the on state in the on state again; and the light-on signal a generation unit that supplies a lighting signal to the plurality of light emitting elements for each group, the lighting signal causing A light-emitting element to be lit is set in a conduction state; the optical unit causes light emitted from the exposure unit to converge on the image carrier. the

According to a twelfth aspect of the present invention, there is provided an image forming apparatus including: a charging unit that charges an image carrier; an exposure unit; an optical unit; a developing unit; The image carrier is exposed and includes a self-scanning light-emitting element array including: a plurality of light-emitting elements arranged in a straight line; a plurality of memory elements arranged to correspond to the respective light-emitting elements and electrically powered; Connected to each light-emitting element, each memory cell is set in any one of the on state and the off state, compared with the case of being set in the off state, in the case of being set in the on state In this case, the plurality of memory elements makes it easy for each light emitting element to be set in a conduction state; and a plurality of switch elements, which are arranged to correspond to and electrically connected to each memory element, each switch element being set in any one of the on-state and the off-state, the plurality of switching elements are set to allow the on-state to move sequentially from one end side to the other end side, compared to the case of the off-state, In the case of being set in a conduction state, the plurality of switching elements make it easy for each memory element to be set in a conduction state; the lighting controller includes: a transfer signal generating unit that provides a transfer signal to the plurality of switching elements, the transfer signal sets the plurality of switching elements so as to allow the conduction state to move sequentially from one end side to the other end side; a memory signal generating unit which supplies a memory signal to the plurality of The plurality of memory elements corresponding to the plurality of light emitting elements of one of the plurality of groups into which the light emitting elements are divided, in a case where the switching elements corresponding to the light emitting elements forming the group are set in a conductive state, If it is desired to turn on the light-emitting element corresponding to the switching element, the memory signal causes the memory element corresponding to the switching element set in the on state to temporarily change from the off state to the on state, and if not wanting to light up the light-emitting element corresponding to the switching element, the memory signal causes the memory element corresponding to the switching element set in the on-state to remain in the off-state, and then causes the memory element that has been temporarily turned on to be turned on. The memory element in the on state is temporarily set in the on state again; and a lighting signal generating unit which supplies a lighting signal to the plurality of light emitting elements for each group so that After the corresponding memory element is set in the conduction state, the light-on signal causes the light-emitting element to be lighted to be set in the conduction state; the optical unit causes the light emitted from the exposure unit to converge to the image on the carrier; the developing unit develops the electrostatic latent image formed on the image carrier; the transfer unit transfers the image developed on the image carrier to the transferred body. the

According to the first aspect of the present invention, an increase in power consumption of a light emitting device can be suppressed using a self-scanning light emitting element array realizing multiple light emission, compared to a case where the present structure is not employed. the

According to the second aspect of the present invention, it is possible to increase the light emission duty (light emission efficiency) compared to the case where the present structure is not employed. the

According to the third aspect of the present invention, the duty ratio of light emission can be further increased compared to the case where the present structure is not adopted. the

According to the fourth aspect of the present invention, an increase in power consumption of a light emitting device can be suppressed using a self-scanning light emitting element array realizing multiple light emission, compared to a case where the present structure is not employed. the

According to the fifth aspect of the present invention, compared with the case where the present structure is not employed, the duty ratio of light emission can be increased. the

According to the sixth aspect of the present invention, parasitic thyristor operation can be suppressed compared to the case where the present structure is not employed. the

According to the seventh aspect of the present invention, it is possible to further increase the light emission duty ratio compared to the case where the present structure is not adopted. the

According to the eighth aspect of the present invention, an increase in power consumption of the light emitting device can be suppressed using the self-scanning light emitting element array realizing multiple light emission, compared to the case where the present structure is not employed. the

According to the ninth aspect of the present invention, it is possible to increase the light emission duty ratio compared to the case where the present structure is not adopted. the

According to the tenth aspect of the present invention, the duty ratio of light emission can be further increased compared to the case where the present structure is not adopted. the

According to the eleventh aspect of the present invention, an increase in power consumption can be suppressed while reducing the size of the print head as compared with the case where the present structure is not employed. the

According to the twelfth aspect of the present invention, image formation can be accelerated while suppressing an increase in power consumption as compared with the case where the present structure is not employed. the

Description of drawings

Exemplary embodiment(s) of the invention are described in detail with reference to the following drawings, in which:

FIG. 1 shows an example of the overall structure of an image forming apparatus to which the first exemplary embodiment is applied;

FIG. 2 is a schematic diagram showing the structure of a print head to which the first exemplary embodiment is applied;

Figure 3 is a top view of the light emitting device;

4 is a schematic diagram showing the structure of the signal generation circuit in the light emitting device in the first exemplary embodiment and the wiring structure of the signal generation circuit and the light emitting chip;

5 is a schematic diagram illustrating a wiring structure of a light emitting chip in the first exemplary embodiment;

6 is a schematic diagram illustrating an outline of the operation of a light-emitting chip;

7 is a timing chart illustrating the operation of the light emitting chip in the first exemplary embodiment;

8 is a timing chart illustrating the operation of a light-emitting chip without applying the first exemplary embodiment;

FIG. 9 is a graph showing an example of a threshold voltage of a memory thyristor and a change in a gate terminal potential after the memory thyristor is turned off;

FIG. 10 is a timing chart illustrating the operation of the light emitting chip in the second exemplary embodiment;

11 is a schematic diagram showing the structure of a signal generating circuit in a light emitting device in a third exemplary embodiment and a wiring structure between the signal generating circuit and each light emitting chip;

12 is a schematic diagram illustrating a circuit structure of a light emitting chip in a third exemplary embodiment;

13 is a timing chart illustrating the operation of the light emitting chip in the third exemplary embodiment;

14 is a schematic diagram showing the structure of the signal generation circuit in the light emitting device in the fourth exemplary embodiment and the wiring structure between the signal generation circuit and each light emitting chip;

15 is a schematic diagram illustrating a circuit structure of a light emitting chip in a fourth exemplary embodiment;

16 is a timing chart illustrating the operation of the light emitting chip in the fourth exemplary embodiment;

17 is a schematic diagram showing the structure of the signal generating circuit in the light emitting device in the fifth exemplary embodiment and the wiring structure between the signal generating circuit and each light emitting chip;

18 is a schematic diagram illustrating a circuit structure of a light emitting chip in a fifth exemplary embodiment; and

Fig. 19 is a timing chart illustrating the operation of the light emitting chip in the fifth exemplary embodiment. the

Detailed ways

(image forming equipment)

Exemplary embodiments of the present invention will be described in detail below with reference to the accompanying drawings. the

<First Exemplary Embodiment>

FIG. 1 shows an example of the overall structure of an image forming apparatus 1 to which the first exemplary embodiment is applied. The image forming apparatus 1 shown in FIG. 1 is generally called a tandem type image forming apparatus. The image forming apparatus 1 includes an image forming processing unit 10 , an image output controller 30 and an image processor 40 . The image forming processing unit 10 forms an image from image data sets of different colors. The image output controller 30 controls the image forming processing unit 10 . The image processor 40 is connected to devices such as a personal computer (PC) 2 and the image reading apparatus 3, and performs predetermined image processing on image data received from the above devices. the

The image forming processing unit 10 includes an image forming unit 11 . The image forming unit 11 is composed of a plurality of engines arranged in parallel at equal intervals. Specifically, the image forming unit 11 is composed of four image forming units 11Y, 11M, 11C, and 11K. Each of the image forming units 11Y, 11M, 11C, and 11K includes a photosensitive drum 12 , a charging device 13 , a print head 14 , and a developing device 15 . An electrostatic latent image is formed on a photosensitive drum 12 as an example of an image carrier, and the photosensitive drum 12 holds a toner image. A charging device 13 as an example of a charging unit uniformly charges the surface of the photosensitive drum 12 with a predetermined potential. The print head 14 exposes the photosensitive drum 12 charged by the charging device 13 . The developing device 15 as an example of a developing unit develops the electrostatic latent image formed by the print head 14 . Here, the image forming units 11Y, 11M, 11C, and 11K have substantially the same configuration except for the color of the toner contained in the developing device 15 is different. The image forming units 11Y, 11M, 11C, and 11K form yellow (Y), crystal red (M), cyan (or cyan) (C) and black (K) toner images, respectively. the

In addition, the image forming processing unit 10 further includes a paper conveying belt 21 , a driving roller 22 , a transfer roller 23 , and a fixing device 24 . The paper conveyance belt 21 conveys the recording paper as the transferred body so that the toner images of different colors respectively formed on the photosensitive drums 12 of the image forming units 11Y, 11M, 11C, and 11K are transferred to the recording paper by multilayer transfer. on paper. The drive roller 22 is a roller that drives the paper conveying belt 21 . Each transfer roller 23 , which is an example of a transfer unit, transfers the toner image formed on the corresponding photosensitive drum 12 onto recording paper. The fixing device 24 fixes the toner image on the recording paper. the

In this image forming apparatus 1 , an image forming processing unit 10 performs an image forming operation in accordance with various control signals supplied from an image output controller 30 . Under the control of the image output controller 30, the image processor 40 performs image processing on the image data received from the personal computer (PC) 2 or the image reading device 3, and then supplies the resulting data set to the corresponding image forming unit 11. Subsequently, for example, in the black (K) image forming unit 11K, the photosensitive drum 12 is charged at a predetermined potential by the charging device 13 while rotating in the arrow A direction, and then the print head 14 is charged according to the image data supplied from the image processor 40. The photosensitive drum 12 is exposed to light by emitting light. Through this operation, an electrostatic latent image for a black (K) image is formed on the photosensitive drum 12 . Thereafter, the developing device 15 develops the electrostatic latent image formed on the photosensitive drum 12, and thus a black (K) toner image is formed on the photosensitive drum 12. Similarly, yellow (Y), magenta (M), and cyan (C) toner images are formed on the image forming units 11Y, 11M, and 11C, respectively. the

By the transfer electric field applied to the transfer roller 23 , the toner images of the respective colors formed on the photosensitive drums 12 in the respective image forming units 11 are sequentially electrostatically transferred to the recording sheet provided due to the movement of the paper conveying belt 21 . paper. Here, the sheet conveyance belt 21 moves in the arrow B direction. Through this operation, a composite toner image that is an overlapping color toner image is formed on the recording paper. the

Thereafter, the recording paper on which the composite toner image is electrostatically transferred is sent to the fixing device 24 . The composite toner image on the recording paper sent to the fixing device 24 is fixed onto the recording paper by the fixing device 24 through a fixing process using heat and pressure, and then output from the image forming apparatus 1 . the

(Print Head)

FIG. 2 is a schematic diagram showing the structure of the print head 14 to which the first exemplary embodiment is applied. The print head 14 includes a housing 61 , a light emitting portion 63 , a circuit board 62 and a rod lens array 64 . The light emitting section 63 has a plurality of LEDs (light emitting thyristors in the first exemplary embodiment). Mounted on the circuit board 62 are the light emitting section 63 , a signal generating circuit 100 (see FIG. 3 described later), and the like as an example of a lighting controller that drives the light emitting section 63 . The rod lens array 64 as an example of an optical unit condenses the light emitted from the light emitting portion 63 onto the surface of the photosensitive drum 12 . Here, the light emitting section 63, the signal generation circuit 100, and the circuit board 62 on which these elements are mounted will be referred to as a light emitting device 65 as an example of an exposure unit. the

The housing 61 is made of metal, for example, and supports a circuit board 62 and a rod lens array 64 . The housing 61 is arranged such that the light emitting point of the light emitting portion 63 is located on the focal plane of the rod lens array 64 . Furthermore, the rod lens array 64 is arranged along the axial direction of the photosensitive drum 12 (first scanning direction). the

(light emitting device)

FIG. 3 is a plan view of the light emitting device 65 . the

As shown in FIG. 3, the light emitting portion 63 of the light emitting device 65 is composed of 60 light emitting chips C1 to C60 arranged in two rows on the circuit board 62 along the first scanning direction. Here, 60 light emitting chips C1 to C60 are arranged in a zigzag pattern, with every adjacent two of the light emitting chips C1 to C60 facing each other. Note that the light-emitting chips C1 to C60 are described as light-emitting chips C ( C1 to C60 ) or light-emitting chips C if they are not distinguished. The same is true for other terms. the

All light emitting chips C ( C1 to C60 ) have the same structure. Each light-emitting chip C ( C1 to C60 ) has a light-emitting thyristor array (light-emitting element array) composed of light-emitting thyristors L1 , L2 , L3 . . . as examples of light-emitting elements, as will be described later. The light emitting thyristor array is arranged along the long side of the rectangle of the light emitting chip C. The light emitting thyristor array is arranged close to one of the long sides and such that the light emitting thyristors L1, L2, L3, . . . are formed at equal intervals. Here, odd-numbered light-emitting chips C1, C3, C5... and even-numbered light-emitting chips C2, C4, C6... are arranged to face each other. In addition, the light-emitting chips C1 to C60 are arranged such that the light-emitting thyristors are also arranged at equal intervals in the first scanning direction in the connection portion of the light-emitting chip C as indicated by a dotted line. the

Also, as described above, the light emitting device 65 includes the signal generation circuit 100 that drives the light emitting portion 63 . the

Note that the light-emitting thyristors L1 , L2 , L3 . . . are referred to as light-emitting thyristors L if they are not distinguished. the

4 is a schematic diagram showing the structure of the signal generating circuit 100 in the light emitting device 65 and the wiring structure of the signal generating circuit 100 and the light emitting chips C ( C1 to C60 ). Note that in FIG. 4 , the light-emitting chips C1 to C60 are not illustrated in a zigzag pattern because of describing a wiring structure. the

The image-processed image data set and various control signals are input to the signal generating circuit 100 from the image output controller 30 and the image processor 40 (see FIG. 1 ), whose illustration is omitted in the figure. Subsequently, the signal generation circuit 100 performs rearrangement of the image data set and correction of luminous intensity and the like based on the image data set and various control signals. the

The signal generating circuit 100 includes a lighting signal generating unit 110 that transmits lighting signals φI (φI1 to φI30) for supplying light-emitting thyristors L with electric power for light emission to the light-emitting chips C (C1 to φI30). C60). the

The signal generating circuit 100 includes a transfer signal generating unit 120 that transmits a first transfer signal φ1 and a second transfer signal φ2 to the light emitting chips C1 to C60 according to various control signals. Furthermore, the signal generation circuit 100 includes a memory signal generation unit 130 that transmits memory signals φm (φm1 to φm60 ) specifying light-emitting thyristors L to be lit according to the image data set. the

The circuit board 62 of the light emitting device 65 is provided with a power line 104 . The power supply line 104 is connected to a Vsub terminal (see FIG. 5 described later) of the light emitting chips C ( C1 to C60 ), and supplies a reference potential Vsub (for example, 0V). In addition, the circuit board 62 of the light emitting device 65 is provided with another power line 105 . The power supply line 105 is connected to a Vga terminal (see FIG. 5 described later) of the light emitting chips C ( C1 to C60 ), and supplies a power supply potential Vga (for example, −3.3 V) for power supply. the

Also, the circuit board 62 is provided with a first transfer signal line 106 and a second transfer signal line 107 . The first transfer signal line 106 and the second transfer signal line 107 respectively transmit the first transfer signal φ1 and the second transfer signal φ2 from the transfer signal generation unit 120 of the signal generation circuit 100 to the light emitting portion 63 . The first transfer signal line 106 and the second transfer signal line 107 are respectively connected in parallel to the φ1 terminal and the φ2 terminal of the light emitting chips C ( C1 to C60 ) (see FIG. 5 described later). the

Furthermore, the circuit board 62 is provided with 60 memory signal lines 108 ( 108_1 to 108_60 ). The memory signal line 108 transmits the respective memory signals φm (φm1 to φm60 ) from the memory signal generating unit 130 of the signal generating circuit 100 to the corresponding light-emitting chips C ( C1 to C60 ). The memory signal lines 108_1 to 108_60 are respectively connected to φm terminals of the light-emitting chips C1 to C60 (see FIG. 5 described later). That is, the memory signals φm (φm1 to φm60) are individually transmitted to the light emitting chips C (C1 to C60). the

Moreover, the circuit board 62 is also provided with 30 lighting signal lines 109 (109_1 to 109_30). The lighting signal line 109 transmits the respective lighting signals φI (φI1 to φI30 ) from the lighting signal generating unit 110 of the signal generating circuit 100 to the corresponding light-emitting chips C ( C1 to C60 ). Each of the lighting signal lines 109 ( 109_1 to 109_30 ) is connected to two φI terminals of two light-emitting chips C as a pair (see FIG. 5 described later). For example, the lighting signal line 109_1 is connected in parallel to the φI terminals of the light-emitting chips C1 and C2, and the lighting signal φI1 is commonly supplied to the φI terminals of the light-emitting chips C1 and C2. Similarly, the lighting signal line 109_2 is connected in parallel to the φI terminals of the light-emitting chips C3 and C4, and the lighting signal φI2 is commonly supplied to the φI terminals of the light-emitting chips C3 and C4. Other lighting signal lines also have similar structures. Thus, the number (30) of lighting signals φI is half the number (60) of light-emitting chips C. the

As described above, in the first exemplary embodiment, the reference potential Vsub, the power supply potential Vga, the first transfer signal φ1 and the second transfer signal φ2 are commonly sent to all the light emitting chips C ( C1 to C60 ). The memory signals φm (φm1 to φm60) are individually sent to the light-emitting chips C (C1 to C60). Each of the lighting signals φI (φI1 to φI30 ) is sent to corresponding two of the light-emitting chips C ( C1 to C60 ). the

With this configuration, the number of lighting signal lines 109 ( 109_1 to 109_30 ) is set to be smaller than the number of light-emitting chips C ( C1 to C60 ). the

The lighting signal line 109 is required to have low resistance in order to supply current for lighting (light emission) to the light-emitting thyristor L. For this reason, if the lighting signal line 109 is arranged as a wide wiring, the width of the circuit board 62 becomes large, hindering downsizing of the print head 14 . On the other hand, in order to narrow the width of the circuit board 62, if the signal line is configured to have multiple layers, this configuration prevents cost reduction of the print head 14. the

In the first exemplary embodiment, compared with the case where the lighting signal lines 109 are provided for the light-emitting chips C respectively, the number of lighting signal lines 109 is reduced, and thus the size of the print head 14 can be reduced and at a low cost. Printhead 14 is manufactured at a cost. the

On the other hand, in the first exemplary embodiment, the memory signal lines 108 are arranged such that the number of the memory signal lines 108 is equal to the number of the light-emitting chips C. As shown in FIG. As described later, it is only necessary that the memory signal line 108 supplies a current that maintains the conduction (ON) state of the memory thyristor M (see FIG. 5 described later). The current for maintaining the ON state of the memory thyristor M is smaller than the current for lighting (emitting light) the light-emitting thyristor L, and thus the width of the memory signal line 108 is set not to have a low resistance like the lighting signal line 109 is acceptable. the

In other words, reducing the number of lighting signal lines 109 can achieve downsizing of the print head 14 and manufacturing of the print head 14 at low cost. the

(light-emitting chip)

5 is a schematic diagram illustrating a wiring structure of light emitting chips C (C1 to C60) which are self-scanning light emitting element array (SLED) chips. Here, the light-emitting chip C1 is described as an example. However, the other light emitting chips C2 to C60 have the same structure as the light emitting chip C1. the

The light-emitting chip C1 (C) includes a transfer thyristor array (switching element array) consisting of transfer thyristors T1, T2, T3, . . . , M2, M3...A memory thyristor array (memory element array), and a light-emitting thyristor array (light-emitting element array) composed of light-emitting thyristors L1, L2, L3... that are also arranged in a row, these arrays are arranged on the substrate 80 superior. the

Here, similar to the light emitting thyristor L, the transfer thyristors T1 , T2 , T3 . . . are called transfer thyristors T if they are not distinguished. Similarly, memory thyristors M1 , M2 , M3 . . . are referred to as memory thyristors M if they are not distinguished. the

The light-emitting chip C1(C) includes coupling diodes Dc1, Dc2, Dc3... connecting each pair of each two of the transfer thyristors T1, T2, T3 and formed in numerical order. Also, the light emitting chip C1(C) includes connection diodes Dm1, Dm2, Dm3.... the

In addition, the light emitting chip C1(C) includes power line resistors Rt1, Rt2, Rt3..., power line resistors Rm1, Rm2, Rm3..., and resistors Rn1, Rn2, Rn3.... the

Here, similar to the light-emitting thyristor L, etc., if the coupling diodes Dc1, Dc2, Dc3..., the connection diodes Dm1, Dm2, Dm3..., the power line resistances Rt1, Rt2, Rt3..., the power line resistances Rm1, Rm2, Rm3 are not distinguished separately ..., and resistors Rn1, Rn2, Rn3..., they are respectively called coupling diode Dc, connection diode Dm, power line resistance Rt, power line resistance Rm, and resistance Rn. the

In the first exemplary embodiment, if the number of light-emitting thyristors L in the light-emitting thyristor array is set to 128, the number of transfer thyristors T and the number of memory thyristors M are also set to 128. Similarly, the number of connection diodes Dm, the respective numbers of power line resistors Rt and Rm, and the number of resistors Rn are also 128. Meanwhile, the number of coupling diodes Dc is 127, which is one less than the number of transfer thyristors T. the

Note that in FIG. 5 , only a portion mainly including transfer thyristors T1 to T8 , memory thyristors M1 to M8 , and light-emitting thyristors L1 to L8 is shown. In other sections, repeat in the same pattern as this section. the

The number of transfer thyristors T is not necessarily equal to the number of light emitting thyristors L, and may be greater than the number of light emitting thyristors L. the

Also, the light emitting chip C1(C) includes a start diode Ds. In order to prevent excessive current from flowing into the first transfer signal line 72 and the second transfer signal line 73, the light emitting chip C1(C) includes current limiting resistors R1 and R2. the

Note that the transfer thyristors T1 , T2 , T3 . . . are arranged in numerical order in FIG. 5 . Here, transfer thyristors T1 , T2 , T3 . . . are arranged from the left side in FIG. 5 , such as T1 , T2 , T3 . . . Similarly, memory thyristors M1 , M2 , M3 . . . and light-emitting thyristors L1 , L2 , L3 . . . are also arranged in numerical order from the left side of FIG. 5 . In addition, coupling diodes Dc1, Dc2, Dc3..., connection diodes Dm1, Dm2, Dm3..., power line resistors Rt1, Rt2, Rt3..., power line resistors Rm1, Rm2, Rm3..., and resistors Rn1, Rn2, Rn3... They are also numbered sequentially from the left in Figure 5. the

Next, electrical connections between elements in the light-emitting chip C1 (C) will be described. the

The anode terminals of the transfer thyristors T1, T2, T3..., the anode terminals of the memory thyristors M1, M2, M3... and the anode terminals of the light-emitting thyristors L1, L2, L3... are connected to the substrate 80 (common anode) of the light-emitting chip C1 (C) . These anode terminals are connected to the power supply line 104 (see FIG. 4 ) through the Vsub terminal provided on the substrate 80 . A reference potential Vsub is supplied to this power supply line 104 . the

The gate terminals Gt1, Gt2, Gt3... of the transfer thyristors T1, T2, T3... , T2, T3... set accordingly. The power line 71 is connected to the Vga terminal. The Vga terminal is connected to the power supply line 105 (see FIG. 4 ), and a power supply potential Vga is supplied to the Vga terminal. the

According to the array of transfer thyristors T, the cathode terminals of odd-numbered transfer thyristors T1 , T3 , T5 . . . are connected to the first transfer signal line 72 . The first transfer signal line 72 is connected to the φ1 terminal which is an input terminal of the first transfer signal φ1 through the current limiting resistor R1. A first transfer signal line 106 (see FIG. 4 ) is connected to this φ1 terminal, and a first transfer signal φ1 is supplied to this φ1 terminal. the

Meanwhile, according to the array of transfer thyristors T, cathode terminals of even-numbered transfer thyristors T2 , T4 , T6 . . . are connected to the second transfer signal line 73 . The second transfer signal line 73 is connected to the φ2 terminal which is the input terminal of the second transfer signal φ2 through the current limiting resistor R2. A second transfer signal line 107 (see FIG. 4 ) is connected to the φ2 terminal, and a second transfer signal φ2 is supplied to the φ2 terminal. the

The cathode terminals of the memory thyristors M1 , M2 , M3 . . . are connected to the memory signal line 74 through corresponding resistors Rn1 , Rn2 , Rn3 . . . The memory signal line 74 is connected to a φm terminal which is an input terminal of a memory signal φm (φm1 in the case of the light-emitting chip C1 ). A memory signal line 108 (see FIG. 4: memory signal line 108_1 in the case of the light-emitting chip C1) is connected to this φm terminal, and a memory signal φm (see FIG. 4: memory signal φm1 in the case of the light-emitting chip C1) is supplied to the φm terminal. the

The gate terminals Gt1, Gt2, Gt3 of the transfer thyristors T1, T2, T3... are connected to the storage thyristors M1, M2, M3... according to the one-to-one correspondence. One of the gate terminals Gm1, Gm2, and Gm3 having the same gate terminal Gt. In other words, the anode terminals of the connection diodes Dm1, Dm2, Dm3... are respectively connected to the gate terminals Gt1, Gt2, Gt3... of the transfer thyristors T1, T2, T3..., and the cathode terminals of the connection diodes Dm1, Dm2, Dm3... are respectively connected to the memory Gate terminals Gm1 , Gm2 , Gm3 . . . of the thyristors M1 , M2 , M3 . . . the

Here, if the gate terminals Gt1 , Gt2 , Gt3 . . . and the gate terminals Gm1 , Gm2 , Gm3 . . . are not distinguished, they are referred to as the gate terminal Gt and the gate terminal Gm, respectively. the

The respective gate terminals Gm1 , Gm2 , Gm3 . . . of the memory thyristors M1 , M2 , M3 . M1, M2, M3... are set accordingly. The power line 71 is connected to the Vga terminal. The Vga terminal is connected to the power supply line 105 (see FIG. 4 ), and a power supply potential Vga is supplied to the Vga terminal. the

In addition, the respective gate terminals Gm1, Gm2, Gm3, ... of the memory thyristors M1, M2, M3 ... are connected in a one-to-one relationship to the corresponding numbers of the light-emitting thyristors L1, L2, L3 ... that are the same as the connected gate terminals Gm. One gate terminal Gl1, Gl2, Gl3.... the

Each coupling diode Dc1, Dc2, Dc3... is connected between each pair of gate terminals Gt of the gate terminals Gt1, Gt2, Gt3... of the light-emitting thyristors L1, L2, L3... Two gate terminals Gt are formed in numerical order. In other words, each coupling diode Dc1 , Dc2 , Dc3 . . . is connected in series to corresponding two of the gate terminals Gt1 , Gt2 , Gt3 . . . The coupling diode Dc1 is connected such that its direction is the direction in which current flows from the gate terminal Gt1 to the gate terminal Gt2. Apply the same configuration to the other coupling diodes Dc2, Dc3, Dc4.... the

The cathode terminals of the light-emitting thyristors L1, L2, L3, . . . are connected to the lighting signal line 75, and the lighting signal line 75 is connected to φI terminal. The lighting signal line 109 (see FIG. 4: lighting signal line 109_1 in the case of the light-emitting chip C1) is connected to the φI terminal, and the lighting signal φI (see FIG. 4: the lighting signal in the case of the light-emitting chip C1 φI1) is supplied to the φI terminal. Note that, as shown in FIG. 4 , for the φI terminals of the other light-emitting chips C2 to C60 , lighting signals φI1 to φI30 are supplied to corresponding light-emitting chip pairs each consisting of two light-emitting chips C, respectively. the

The gate terminal Gt1 of the transfer thyristor T1 located on one end side of the transfer thyristor array is connected to the cathode terminal of the start diode Ds. Meanwhile, the anode terminal of the start diode Ds is connected to the second transfer signal line 73 . the

(Operation of the light emitting part) 

Next, the operation of the light emitting section 63 will be described. As shown in FIG. 4 , a pair of the first transfer signal φ1 and the second transfer signal φ2 is commonly supplied to the light-emitting chips C ( C1 to C60 ) constituting the light-emitting portion 63 . Meanwhile, memory signals φm (φm1 to φm60 ) based on image data sets are individually supplied to the light emitting chips C ( C1 to C60 ). The lighting signals φI (φI1 to φI30) are respectively supplied to corresponding light-emitting chip pairs each composed of two light-emitting chips C, so that each lighting signal φI is shared by the two light-emitting chips C constituting each pair, and Lighting signals φI (φI1 to φI30 ) are individually supplied to the light-emitting chips C constituting different pairs. the

The light-emitting chips C ( C1 to C60 ) perform sequential operations (lighting control) in parallel using a signal pair composed of the first transfer signal φ1 and the second transfer signal φ2 , so that the light-emitting thyristors L light up (emit light) and extinguish. Here, the sequential operation of causing the light-emitting thyristor L to turn on (emit light) and turn off is referred to as lighting control. the

Therefore, if the operation of the light-emitting chip C1 is described, the operation of the light-emitting portion 63 will be understood. Hereinafter, the operation of the light-emitting chip C will be described taking the light-emitting chip C1 as an example. (lighting control of light-emitting chip)

FIG. 6 is a schematic diagram illustrating an outline of the operation of the light-emitting chip C1 (C). the

In the first exemplary embodiment, lighting control is performed in the light-emitting chip C1 (C) using a group consisting of a plurality of light-emitting points (light-emitting thyristors L) set in advance. the

FIG. 6 shows a case where lighting control is performed using a set of eight light-emitting thyristors L. As shown in FIG. In other words, in the first exemplary embodiment, up to eight light-emitting thyristors L are simultaneously made to light up. First, in FIG. 6 , lighting control is performed on the eight light-emitting thyristors L1 to L8 as shown in group #A from the left side of the light-emitting chip C1 (C) (the point shown in FIG. 7 described later bright control period T(#A)). Next, lighting control is performed on the eight light-emitting thyristors L9 to L16 in group #B adjacent to group #A (lighting control period T(#B) shown in FIG. 7 described later). Subsequently, lighting control is performed on the eight light-emitting thyristors L17 to L24 shown as group #C. If the number of light-emitting thyristors L provided in the light-emitting chip C is 128, the lighting control of eight light-emitting thyristors L is repeated in a similar manner until the lighting control of the light-emitting thyristor L128 is performed. the

In other words, in the first exemplary embodiment, lighting control is sequentially performed on the groups #A, #B... in chronological order, and a plurality of light-emitting points ( The light-emitting thyristor L) performs lighting control. the

(drive waveform)

FIG. 7 is a timing chart illustrating the operation of the light-emitting chip C1 (C) in the first exemplary embodiment. In FIG. 7 , it is assumed that time is from time point (moment) a to time point y in alphabetical order. Here, the first transfer signal φ1, the second transfer signal φ2, the memory signal φm1, the lighting signal φI1, and the currents J(M1) to J flowing between the anode terminals and the cathode terminals of the respective memory thyristors M1 to M8 are shown. (M8) waveform. the

FIG. 7 shows a case where lighting control is performed for each group composed of eight light-emitting thyristors L shown in FIG. is the lighting control period T(#A) from time point c to time point y. Note that the lighting control period T(#A) is followed by the lighting control period T(#B) when the lighting control is performed on the light-emitting thyristors L9 to L16 in the group #B, and the lighting control period T(#B) in the group #C The lighting control period T(#C) when the thyristors L17 to L24 perform lighting control, and so on. the

FIG. 7 shows lighting up (emission of light) of the light-emitting thyristors L1, L2, L3, L5, and L8 of the eight light-emitting thyristors L1 to L8 in group #A and keeping light-emitting thyristor L4 of the eight light-emitting thyristors L1 to L8 , L6 and L7 are off. In other words, assume that printing of the image data set "11101001" is performed in the lighting control period T(#A). the

For each lighting control period (such as lighting control period T(#A), lighting control period T(#B)...), the first transfer signal φ1, the second transfer signal φ2 and the lighting signal φI1 (φI ) waveform. On the other hand, although the memory signal φm1 (φm) has a portion that changes depending on the image data set, the basic portion of the memory signal is changed every lighting control period such as lighting control period T(#A), lighting control period T(#A), lighting control period Repeat in T(#B)...). Therefore, these waveforms can be understood as long as the lighting control period T(#A) is described. Note that the period from time point a to time point c, which is a preceding period of the lighting control period T(#A), is a period for starting the operation of the light-emitting chip C1 (C). This period will be explained in the description of the operation. the

First, the waveforms of the first transfer signal φ1, the second transfer signal φ2, the memory signal φm1 (φm), and the lighting signal φI1 (φI) in the lighting control period T(#A) will be described. the

The first transfer signal φ1 has a low-level potential (hereinafter referred to as “L”) at the start time point c of the lighting control period T(#A), and changes from “L” to a high level at the time point f. A flat potential (hereinafter referred to as "H"), which then changes from "H" to "L" at time point i. At the time point k, the potential of the first transfer signal φ1 is kept at "L". Subsequently, the same waveform as the period from time point c to time point k is repeated three times in the period from time point k to time point w. At the time point w, the potential of the first transfer signal φ1 is “L”, and at the time point y which is the end time point of the lighting control period T(#A), the potential of the first transfer signal φ1 is kept at “L”. L". the

The second transition signal φ2 is "H" at time point c, changes from "H" to "L" at time point e, and then changes from "L" to "H" at time point j. At the time point k, the potential of the second transfer signal φ2 is kept at "H". Subsequently, the same waveform as the period from time point c to time point k is repeated three times in the period from time point k to time point w. At the time point w, the potential of the second transfer signal φ2 is "H", and at the time point y which is the end time point of the lighting control period T(#A), the potential of the second transfer signal φ2 is kept at "H". H". the

Here, in the case where the first transfer signal φ1 and the second transfer signal φ2 are compared with each other in the period from the time point c to the time point w, in the period from the time point c to the time point k, the first transfer signal φ1 Each of the and second transfer signals φ2 has potentials that alternately repeat "H" and "L" with a period in which both potentials are "L" inserted (for example, from time point e to time point f, or From time point i to time point j). There is no period in which the first transfer signal φ1 and the second transfer signal φ2 are “H” at the same time. The second transfer signal φ2 is a signal in which the first transfer signal φ1 is shifted rightward by a period corresponding to the period from time point f to time point j on the time axis. The period corresponding to the period from the time point f to the time point j is half the repetition period (twice the period of the period t1 described later) of each of the first transfer signal φ1 and the second transfer signal φ2. the

Next, the memory signal φm1 (φm) will be described. The period from time point c to time point g is the writing period T(M1) when the image data set is written into the memory thyristor M1, and the period from time point g to time point k is when the image data set is written into the memory The writing period T(M2) when the thyristor M2 is in. Similarly, in the lighting control period T(#A), there are provided writing periods T(M3) to T(M8) when image data sets are written into the respective memory thyristors M3 to M8. Note that if the writing periods T(M1) to T(M8) are not distinguished, they are referred to as writing periods T(M). the

These writing periods T(M1) to T(M8) are equal to the same period t1. the

According to the first bit "1" constituting the image data set "11101001", the potential of the memory signal φm1 (φm) changes from "H" to "L" at the start time point c of the writing period T(M1), at time Its potential changes from "L" to "H" at point d. Subsequently, its potential is kept at "H" until a time point g which is an end time point of the writing period T( M1 ). At the time point g which is the start time point of the writing period T(M2), according to the second bit "1" of the image data set "11101001", its potential is changed from "H" to "L" again, at the time point At h, its potential changes from "L" to "H". Subsequently, its potential is maintained at "H" until time point k which is the end time point of the writing period T( M2 ). In other words, the waveform in the writing period T(M1) is repeated in the writing period T(M2). Also, in the writing period T(M3) corresponding to the third bit "1" of the image data set "11101001", the same waveform is repeated. the

Meanwhile, at the time point m which is the start time point of the writing period T(M4), according to the fourth bit "0" of the image data set "11101001", its potential changes from "H" to a memory level potential (hereinafter Called "S"), at time point n, its potential changes from "S" to "H". Its potential is kept at "H" until the time point o which is the end time point of the writing period T ( M4 ). In other words, the change from "H" to "S" at time point m is different from the change from "H" to "L" at time points c, g, and k described above. Note that the memory level potential "S" is a potential between "H" and "L", indicating a potential level such that the memory thyristor M, which is turned off after being turned on, is ready to be turned on after a predetermined period of time, which will be described later. Describe it in detail. Note that the turning on and off of the thyristor will be specifically described. the

Subsequently, in the writing period T(M5), according to the fifth bit "1" of the image data set "11101001", the waveform in the writing period T(M1) is repeated. In the following writing period T(M6) and writing period T(M7), according to the sixth and seventh digits "0" of the image data set "11101001", the writing period T(M4) is repeated respectively waveform. the

Thereafter, the potential of the memory signal φm1 (φm) changes from “H” to “ L", at time point s, its potential changes from "L" to "S". Subsequently, at time point u, the potential changes from "S" to "H". At the end time point w of the writing period T ( M8 ), its potential is kept at "H". the

Subsequently, the potential of the memory signal φm1 (φm) is maintained at “H” until the time point y which is the end time point of the lighting control period T(#A). the

Note that the change of the memory signal φm1 (φm) from “H” to “L” or from “H” to “S” at each start time point of the above-mentioned writing period T(M1) to T(M8) Depending on the image data set for setting the light-emitting thyristors L (each having the same number as the corresponding memory thyristor M) to be turned on or off, the light-emitting thyristors L are simultaneously performed in the light-emitting control period T(#A). Light control. Specifically, when the image data set is "1" and the light-emitting thyristor L is caused to light (emit light), the potential of the memory signal φm1 (φm) changes from "H" to "L". Simultaneously, when the image data set is "0" and the light-emitting thyristor L is kept off (not emitting light), the potential of the memory signal φm1 (φm) changes from "H" to "S". the

As described above, at each start time point of the writing period T(M1) to T(M8), the potential of the memory signal φm1(φm) changes from “H” to “L” and “S” according to the image data set any of the The potential thereof is changed from any one of "L" and "S" to "H" after the elapse of the period t2 except in the writing period T ( M8 ). Note that, in the writing period T ( M8 ), after the period t2 elapses, its potential becomes "S". The operation in the writing period T(M8) will be described later. the

In the relationship between the memory signal φm1 (φm) and each of the first transfer signal φ1 and the second transfer signal φ2, when either of the first transfer signal φ1 and the second transfer signal φ2 is “L”, At each start time point of the writing period T( M1 ) to T( M8 ), the potential of the memory signal φm1 (φm) changes from “H” to any one of “L” and “S”. For example, at a time point c when the first transfer signal φ1 is “L” in the writing period T(M1), at a time point g when the second transfer signal φ2 is “L” in the writing period T(M2) At , the memory signal φm1 is "L". Meanwhile, at a time point m when the second transition signal φ2 is “L”, the memory signal φm1 is “S”. The same is true in the writing periods T(M3) and T(M5) to T(M8). the

The lighting signal φI1 (φI) is a signal to supply current to the light-emitting thyristor L for lighting (emission of light), which will be described later. the

The lighting signal φI is "H" at a start time point c of the lighting control period T(#A), and its potential becomes a light emission level potential (hereinafter referred to as "Le") at a time point t. Its potential changes from "Le" to "H" at time point x. Subsequently, at the end time point y of the lighting control period T(#A), its potential is kept at "H". the

Note that the light emission level potential "Le" represents the potential level (light emission level) at which the light emitting thyristor L specified to be lit according to the image data set is ready to be turned on, as will be described later. Turning on of the thyristor will be described later. the

(Basic operation of thyristor)

Before describing the operation of the light-emitting chip C1 (C), basic operations of the thyristors (transfer thyristor T, memory thyristor M, and light-emitting thyristor L) will be described. These thyristors (transfer thyristor T, memory thyristor M and light-emitting thyristor L) are semiconductor devices as follows: Each semiconductor device has three terminals, namely the anode terminal (anode), cathode terminal (cathode) and gate terminal (gate) . the

Hereinafter, as shown in FIG. 5, as an example, the reference potential Vsub supplied to the thyristor anode terminal (Vsub terminal) is set to 0 V (“H”), and the power supply potential Vga supplied to the Vga terminal is set to −3.3 V("L"). Each thyristor has a pnpn structure, wherein a p-type layer, an n-type layer, a p-type layer and an n-type layer (such as GaAs, GaAlAs, etc.) etc.), the diffusion potential (forward potential) Vd of the p-n junction was set to 1.3V. the

A thyristor having the above-described structure is turned on (sometimes referred to as conduction) when a potential lower than a threshold voltage (potential with a less negative value) is applied to the cathode terminal. When the thyristor is turned on, the thyristor enters a conducting state where current flows between its anode and cathode terminals. Here, the threshold voltage of the thyristor is a value obtained by subtracting the diffusion potential Vd from the gate terminal potential. Therefore, if the gate terminal potential of the thyristor is -1.3V, the diffusion potential vd is 1.3V, and thus the threshold voltage is -2.6V. Thus, when a potential less than -2.6V (<-2.6V) is applied to the cathode terminal, the thyristor turns on. the

Subsequently, when the thyristor is turned on, the potential of the gate terminal of the thyristor approaches the potential of the anode terminal. The anode terminal is set at the reference potential Vsub (0V), whereby the potential of the gate terminal becomes a potential close to 0V (to be precise -0.2V, as described later). Note that in the following description, the potential of the gate terminal of the thyristor that has been turned on is assumed to be 0V in a simple and understandable manner. the

Here, the cathode terminal of the thyristor has a diffusion potential Vd. The diffusion potential Vd is 1.3V, so the potential of the cathode terminal is -1.3V. the

Once the thyristor is turned on, the thyristor is in the conducting state while the potential at the cathode terminal is less than or equal to the potential at which the thyristor is conducting. When the thyristor is in the on state, even if the potential of the gate terminal changes variously, the on state of the thyristor does not change to the off (OFF) state. On the other hand, when the cathode terminal has a high potential (a potential greater than the threshold voltage (or an absolute value smaller than the threshold voltage) on the negative potential side, or a potential greater than or equal to 0 V) exceeding the on-state potential, the thyristor does not hold on state and off. the

Here, in the thyristor in the on state, the potential of the cathode terminal is -1.3V. Therefore, if the potential applied to the cathode terminal is less than or equal to -1.3V (≤ -1.3V), the ON state is maintained. At the same time, a high voltage exceeding -1.3V (>-1.3V) is applied to the cathode terminal, and the thyristor is turned off (called cutoff in some cases). In case the cathode terminal is set to "H" (0V) so that the anode and cathode terminals have the same potential, the thyristor is also turned off. When the thyristor is turned off, the thyristor enters a state (off state) in which conduction current does not flow between the anode terminal and the cathode terminal. the

As described above, in the ON state, the state in which ON current flows into the thyristor is maintained, and the thyristor does not turn off according to the potential of the gate terminal. In other words, by setting the on-state, the thyristor has a storage and hold function. the

As mentioned above, it is acceptable that the potential at which the thyristor is turned on is lower than the potential required to turn the thyristor on. the

Note that when turned on, the light-emitting thyristor L lights up (emits light), and when turned off, the light-emitting thyristor L turns off (does not emit light). the

As described above, the thyristor is turned on by changing the threshold voltage using the potential of the gate terminal, and turned off by changing the potential of the cathode terminal. the

(Operation of light-emitting chip)

Referring to FIG. 5 , operations of the light emitting portion 63 and the light emitting chip C are described based on the timing chart shown in FIG. 7 . the

(initial state)

At time point a in the timing chart shown in FIG. 7, the Vsub terminal provided on each substrate 80 of the light-emitting chips C (C1 to C60) of the light-emitting portion 63 is set at the reference potential Vsub (0 V) (“ H"). At the same time, each Vga terminal is set at the power supply potential Vga (-3.3 V) ("L") (see FIG. 4 ). the

Also, the transfer signal generating unit 120 of the signal generating circuit 100 sets the first transfer signal φ1 and the second transfer signal φ2 at “H”, and the memory signal generating unit 130 sets the memory signal φm (φm1 to φm60) at “H”. ”, and the lighting signal generation unit 110 sets the lighting signal φI (φI1 to φI30 ) at “H” (see FIG. 4 ). By this operation, the first transfer signal line 106 becomes “H”, whereby the first transfer signal line 72 of each light-emitting chip C becomes “H” through the φ1 terminal of each light-emitting chip C in the light-emitting portion 63 . Similarly, the second transfer signal line 107 becomes "H", whereby the second transfer signal line 73 of each light-emitting chip C becomes "H" through the φ2 terminal of each light-emitting chip C. The memory signal lines 108 ( 108_1 to 108_60 ) become “H”, whereby the memory signal line 74 of each light-emitting chip C becomes “H” through the φm terminal of each light-emitting chip C. In addition, the lighting signal line 109 ( 109_1 to 109_30 ) becomes “H”, whereby the lighting signal line 75 of each light-emitting chip C becomes “H” through the φI terminal of each light-emitting chip C. the

Hereinafter, the operation of the light-emitting chip C is described taking the light-emitting chip C1 as an example. The other light emitting chips C2 to C60 operate similarly to the light emitting chip C1 and simultaneously operate in parallel with the light emitting chip C1. the

Since the anode terminals of the transfer thyristors T1, T2, T3..., memory thyristors M1, M2, M3... and light-emitting thyristors L1, L2, L3... of the light-emitting chip C1 (C) are connected to the Vsub terminal, "H" is supplied to the Vsub terminal. (0V). the

Meanwhile, since the cathode terminals of odd-numbered transfer thyristors T1, T3, T5, . The second transfer signal line 73 is set at "H", so the anode terminal and the cathode terminal of the transfer thyristor T become "H". Therefore, each transfer thyristor T is in an off state. the

Similarly, since the cathode terminals of the memory thyristors M1 , M2 , M3 . . . are connected to the memory signal line 74 set at “H”, the anode terminal and the cathode terminal become “H”. Therefore, each memory thyristor M is in an off state. the

Also, since the cathode terminals of the light-emitting thyristors L1, L2, L3... The terminal becomes "H". Therefore, each light emitting thyristor L is in an off state. the

On the other hand, each of the gate terminal Gt of the transfer thyristor T, the gate terminal Gm of the memory thyristor M, and the gate terminal G1 of the light-emitting thyristor L is connected to the power supply line through any one of the power supply line resistances Rt and Rm. 71. The power supply line 71 is supplied with a power supply potential Vga through the Vga terminal. Therefore, the potentials of these gate terminals Gt, Gm, and G1 are the power supply potential Vga (−3.3 V) except for the case described later. the

As described above, the gate terminal Gt1 located at one end side of the transfer thyristor array in FIG. 5 is connected to the cathode terminal of the start diode Ds. The anode terminal of the start diode Ds is connected to the second transfer signal line 73 set at "H". Therefore, since the cathode terminal of the starting diode Ds connected to the gate terminal Gt1 is connected to the power supply line 71 through the power supply line resistance Rt, the anode terminal of the starting diode Ds is intended to have a potential of "L" (-3.3V). At the same time, the potential of the anode terminal is "H" (0 V), whereby the start diode D s enters a state where an electric field is applied to the start diode in the forward direction (forward bias state). As a result, the potential of the cathode terminal (gate terminal Gt1) of the start diode Ds becomes -1.3 V, which is obtained by subtracting the diffusion voltage Vd (1.3 V) from "H" (0 V) set for the anode terminal of the start diode Ds. V) and obtained. the

Therefore, as described above, the threshold voltage of the transfer thyristor T1 becomes -2.6V, which is obtained by subtracting the diffusion potential Vd (1.3V) from the potential of the gate terminal Gt1 (-1.3V). the

Note that the gate terminal Gt2 of the transfer thyristor T2 adjacent to the transfer thyristor T1 is connected to the gate terminal Gt1 through the coupling diode Dc1, whereby the potential of the gate terminal Gt2 becomes -2.6 V, which is obtained by switching from the gate terminal It is obtained by subtracting the diffusion potential Vd (1.3V) of the coupling diode Dc1 from the potential of Gt1 (-1.3V). Therefore, the threshold voltage of the transfer thyristor T2 becomes -3.9V. the

Note that the gate terminal Gt3 of the transfer thyristor T3 is connected to the gate terminal Gt2 of the transfer thyristor T2 through the coupling diode Dc2, whereby the potential of the gate terminal Gt3 is calculated to be -3.9V according to the calculation method described above. However, the gate terminal Gt3 is connected to the power supply potential Vga ("L": -3.3V) through the power supply line resistance Rt3. Therefore, the value of the potential of the gate terminal Gt3 is not less than -3.3V, and is therefore -3.3V. Therefore, the threshold voltage of the transfer thyristor T3 is -4.6V. The threshold voltages of the transfer thyristors T whose respective numbers are not less than 4 are similarly set. the

Similarly, the gate terminal Gm1 of the memory thyristor M1 (and the gate terminal Gl1 of the light-emitting thyristor L1) is connected to the gate terminal Gt1 through the connection diode Dm1, whereby the gate terminal Gm1 of the memory thyristor M1 (and the gate terminal Gl1) The potential of becomes -2.6V, which is obtained by subtracting the diffusion voltage Vd (1.3V) of the connection diode Dm1 from the potential of the gate terminal Gt1 (-1.3V). Therefore, the threshold voltage of the memory thyristor M1 (light-emitting thyristor L1) becomes -3.9V. the

Note that the gate terminal Gm2 of the memory thyristor M2 (and the same for the gate terminal G12 of the light-emitting thyristor L2) is connected to the gate terminal Gt1 through the coupling diode Dc1 and the connection diode Dm2. However, the gate terminal Gm2 is connected to the power supply line 71 through the power supply line resistance Rm2. Therefore, similarly to the case of the transfer thyristor T3 described above, the potential of the gate terminal Gm2 of the memory thyristor M2 (and the gate terminal G12 of the light emitting thyristor L2 as well) becomes -3.3V. Therefore, the threshold voltage of the memory thyristor M2 (light-emitting thyristor L2) becomes 4.6V. The threshold voltages of the memory thyristors M (and light-emitting thyristors L) whose respective numbers are not less than 3 are similarly set. the

Note that even if the threshold of the thyristor changes, the first transfer signal φ1, the second transfer signal φ2, the memory signal φm1(φm), and the lighting signal φI1(φI) are “H” (0V), whereby all the transfer thyristors T, memory Both the thyristor M and the light-emitting thyristor L are in an off state. the

When the potential of the first transfer signal φ1 changes from “H” (0 V) to “L” (−3.3 V) at time point b, the transfer thyristor T1 having a threshold voltage of −2.6 V is turned on. However, the odd-numbered transfer thyristors T after the transfer thyristor T3 are supplied with the transfer signal φ1, the threshold voltage is −4.6 V, and thus these transfer thyristors T are not turned on. In addition, since the second transfer signal φ2 is "H" (0V), the transfer thyristor T2 whose threshold voltage is -3.9V is not turned on. Even-numbered transfer thyristors T whose respective numbers are not less than 4 are not turned on because the threshold voltage of these transfer thyristors is -4.6V. the

Note that at time point b, since the potentials of the memory signal φm1 (φm) and the lighting signal φI1 (φI) are kept at “H”, neither the memory thyristor M nor the light-emitting thyristor L is turned on. In other words, at time point b, only the transfer thyristor T1 is switched on. the

When the transfer thyristor T1 is turned on, as described above, the potential of the gate terminal Gt1 becomes "H" (0 V) which is the potential of the anode terminal. In addition, the potential of the cathode terminal (first transfer signal line 72 ) of the transfer thyristor T1 becomes -1.3 V, which is obtained by subtracting the diffusion potential Vd (1.3 V) from the anode terminal potential "H" (0 V). . the

Therefore, the potential of the anode terminal of the coupling diode Dc1 becomes 0 V which is the potential of the gate terminal Gt1, and the potential of the gate terminal Gt2 which is the cathode terminal of the coupling diode Dc1 is −2.6 V, whereby the coupling diode Dc1 enters the forward direction. bias state. In this state, the potential of the gate terminal Gt2 becomes -1.3V, which is obtained by subtracting the diffusion potential Vd (1.3V) of the coupling diode Dc1 from the potential of the gate terminal Gt1 (0V). Therefore, the threshold voltage of the transfer thyristor T2 becomes -2.6V. the

The potential of the gate terminal Gt3 connected to the gate terminal Gt2 of the transfer thyristor T2 through the coupling diode Dc2 can be calculated using the method described above, which becomes -2.6V. Therefore, the threshold voltage of the transfer thyristor T3 becomes -3.9V. The potential of the gate terminal Gt of each of the transfer thyristors T not less than 4 after the transfer thyristor T3 is maintained at the power supply potential Vga (-3.3 V), whereby the threshold voltage of each of the transfer thyristors T of not less than 4 is maintained at -4.6 V. the

When the transfer thyristor T1 is turned on and the potential of the gate terminal Gt1 becomes "H" (0 V), the connection diode Dm1 is forward biased. Therefore, the potential of the gate terminal Gm1 (the same goes for the gate terminal Gl1) becomes -1.3 V by subtracting the diffusion voltage Vd (1.3 V) of the connection diode Dm1 from the potential (0 V) of the gate terminal Gt1. ) and obtained. Therefore, the threshold voltage of the memory thyristor M1 (and the light-emitting thyristor L1 as well) becomes -2.6V. the

Note that the potential of the gate terminal Gm2 (the same goes for the gate terminal G12) of the memory thyristor M2 adjacent thereto becomes −2.6 V because the gate terminal Gm2 passes through the coupling diode Dc1 and the connection diode Dm2 connected in series to each other. connected to the gate terminal Gt1 for sake. Therefore, the threshold voltage of the memory thyristor M2 (and the light-emitting thyristor L2 as well) becomes -3.9V. the

In addition, the potential of the gate terminal Gm of the memory thyristor M (gate terminal G1 of the light-emitting thyristor L) of each number not less than 3 is maintained at −3.3 V equal to the power supply potential Vga. Therefore, the threshold voltages of the memory thyristors M (light-emitting thyristors L) whose respective numbers are not less than 3 are maintained at -4.6V. the

As described above, immediately after the time point b (indicating a time point after the state of the thyristor or the like changes according to the change in the signal potential at the time point b), only the transfer thyristor T1 is in the ON state. the

(operating status)

When the potential of the memory signal φm1 (φm) changes from “H” (0 V) to “L” (−3.3 V) at time point c, the memory thyristor M1 having a threshold voltage of −2.6 V is turned on. However, the memory thyristor M2 and the memory thyristors M each numbered not less than 3 are not turned on because the threshold voltage of the memory thyristor M2 is -3.9V and the threshold voltage of the memory thyristors M each numbered not less than 3 is -4.6V for the sake. the

In other words, the memory thyristor M turned on at time point c is only the memory thyristor M1. the

Then, as shown in the current J(M1), the turn-on current Jo flows into the already turned-on memory thyristor M1. the

When the memory thyristor M1 is turned on, similarly to the case of the transfer thyristor T1, the potential of the gate terminal Gm1 becomes "H" (0 V). Subsequently, since the gate terminal Gl1 of the light-emitting thyristor L1 is connected to the gate terminal Gm1, the threshold voltage of the light-emitting thyristor L becomes -1.3V. the

Note that since the gate terminal Gm2 of the memory thyristor M2 (the gate terminal G12 of the light-emitting thyristor L2) is connected to the gate terminal Gt2 which becomes -1.3V through the forward-biased connection diode Dm2, the gate terminal of the memory thyristor M2 The potential of the sub Gm2 (the gate terminal G12 of the light emitting thyristor L2) is 2.6V. Therefore, the threshold voltage of the memory thyristor M2 (light-emitting thyristor L2) becomes -3.9V. the

However, since the voltage of the gate terminal Gm (gate terminal G1) is -3.3V, the threshold voltage of the memory thyristors M (light-emitting thyristors L) whose respective numbers are not less than 3 is -4.6V. the

Therefore, at the time point c, the memory thyristors M whose respective numbers are not less than 2 are not turned on. the

In addition, since the lighting signal φI1 (φI) is “H” (0 V), no light-emitting thyristor L is turned on. the

Therefore, immediately after the time point c, the transfer thyristor T1 and the memory thyristor M1 are kept in the on state. the

Note that, as described above, the potential of the cathode terminal of the memory thyristor M1 that has been turned on becomes -1.3V, which is obtained by subtracting the diffusion voltage Vd (1.3V) from the potential of the anode terminal (0V). However, since the memory thyristor M1 is connected to the memory signal line 74 through the resistance Rn1, the potential of the memory signal line 74 is kept at "L" (-3.3V). the

The operations of the thyristors (transfer thyristor T, memory thyristor M, and light emitting thyristor L) and diodes (coupling diode Dc and connection diode Dm) of the light emitting chip C1 (C) have been described above, respectively. However, the operations of the thyristors and diodes will be described below. the

Specifically, when a thyristor is turned on, the potential of the gate terminal (gate terminal Gt, gate terminal Gm, and gate terminal G1) of the thyristor becomes “H” (0 V). the

Then, the threshold voltage of the thyristor is 1.3V for the thyristor whose gate terminal is connected to the gate terminal at potential "H" (0V) without any diode. the

In addition, the potential of the gate terminal connected to the gate terminal at the potential "H" (0 V) through one stage of forward biased diode (one diode) becomes -1.3 V by changing the potential from "H" ( 0V) minus the diffusion potential Vd (1.3V). Therefore, the threshold voltage of the thyristor having this gate terminal becomes -2.6V. the

Also, the potential of the gate terminal connected to the gate terminal at potential "H" (0 V) through two stages of forward-biased diodes (two diodes connected in series to each other) becomes -2.6 V, which is obtained by Obtained by subtracting twice the diffusion voltage Vd (1.3V) from "H" (0V). Therefore, the threshold voltage of the thyristor having this gate terminal becomes -3.9V. the

In addition, the gate terminal connected to the gate terminal at the potential "H" (0V) through three or more stages of diodes is supplied with the power supply potential Vga (-3.3V) through the power supply line resistance (Rt or Rm), and thus Still affected by the gate terminal at potential "H" (0V). Therefore, the potential of the gate terminal is kept at the power supply potential Vga (-3.3V). Therefore, the threshold voltage of the thyristor having this gate terminal becomes -4.6V. the

Thyristors connected to the gate terminal of potential "H" (0 V) without any diode, and whose gate terminal is connected to the gate terminal of potential "H" (0 V) through a forward-biased diode of one stage The thyristor turns on at potential "L" (-3.3V) or less (or greater in absolute value). Meanwhile, the thyristor whose gate terminal is connected to the gate terminal of potential "H" (0V) through two or more stages of forward biased diodes is not turned on at potential "L" (-3.3V). the

So the only concerns are thyristors whose gate terminal is connected to a potential "H" (0V) without a diode through any diode, and whose gate terminal is connected to a potential "H" through a primary forward biased diode ” (0V) to the gate terminal of the thyristor. the

Hereinafter, only a thyristor whose gate terminal is connected to a gate terminal at potential "H" (0 V) without any diode at each timing, and whose gate terminal is connected to a potential of "H" (0V) gate terminal of the thyristor connected. At each timing, descriptions of thyristors that are not turned on, potentials of gate terminals of these thyristors, and changes in threshold voltages thereof will be omitted. the

Referring back to FIG. 7 , other operations of the light emitting chip C1 (C) will be described. the

At a time point d, the potential of the memory signal φm1 (φm) changes from “L” to “H”. Subsequently, since the anode terminal and the cathode terminal of the memory thyristor M1 have the same potential "H", the memory thyristor M1 is turned off. Therefore, current stops flowing into memory thyristor M1 as shown in current J(M1). the

Since the gate terminal Gm1 is connected to the power supply potential Vga (-3.3V) through the power supply line resistance Rm1, the potential of the gate terminal Gm1 starts to change from "H" (0V) to the power supply potential Vga (-3.3V). In other words, the charges accumulated in the parasitic capacitance of the gate terminal Gm1 are discharged through the power supply line resistance Rm1. the

Immediately after the point in time d, only the transfer thyristor T1 remains in the conducting state. the

At the time point e, the potential of the second transfer signal φ2 is changed from "H" to "L". Subsequently, the transfer thyristor T2 whose threshold power supply is -2.6V is turned on. the

When the transfer thyristor T2 is turned on, the potential of the gate terminal Gt2 increases to "H" (0V). Also, the threshold voltage of the transfer thyristor T3 connected to the gate terminal Gt2 through a forward-biased diode (coupling diode Dc2) of one stage becomes -2.6V. Similarly, the threshold voltages of both the memory thyristor M2 and the light emitting thyristor L2 connected to the gate terminal Gt2 through the primary diode (connection diode Dm2 ) become -2.6V. the

At this time, the transfer thyristor T1 remains in the on state. Therefore, the potential of the first transfer signal line 72 connected to the cathode terminals of the odd-numbered transfer thyristors T1, T3, . Therefore, the transfer thyristor T3 is not turned on. the

Immediately after the point in time e, both transfer thyristors T1 and T2 are in the conducting state. the

At the time point f, the potential φ1 of the first transfer signal φ1 changes from “L” to “H”. Subsequently, the cathode terminal and the anode terminal of the transfer thyristor T1 become the same potential "H". Therefore, the transfer thyristor T1 is no longer kept in the conducting state, and is thus turned off. the

At this time, the gate terminal Gt1 of the transfer thyristor T1 starts to change toward the power supply potential Vga (-3.3 V) because the gate terminal Gt1 is connected to the power supply line 71 through the power supply line resistance Rt1. With this change, the coupling diode Dc1 between the transfer thyristor T1 and the transfer thyristor T2 becomes reverse biased. Therefore, the potential "H" (0 V) of the gate terminal Gt2 no longer affects the gate terminal Gt1 . the

In other words, as described above, the potential "H" (0 V) does not affect the gate terminal connected to it through the reverse biased diode. the

Immediately after the time point f, the transfer thyristor T2 remains in the conducting state. the

At a time point g, the potential of the memory signal φm1 (φm) changes from “H” (0 V) to “L” (−3.3 V). Subsequently, since the threshold voltage of the memory thyristor M2 is -2.6V, the memory thyristor M2 is turned on. the

The gate terminal Gm1 starts changing from "H" (0 V) to the power supply potential Vga (−3.3 V) at the time point d. This potential change is determined by a time constant defined by the parasitic capacitance of the gate terminal Gm1 and the power supply line resistance Rm1. At the time point g, if the potential of the gate terminal Gm1 is maintained at a potential of -2 V or more, the threshold voltage of the memory thyristor M1 is -3.3 V or more. Therefore, at the time point g when the potential of the memory signal φm1 (φm) changes from “H” to “L” (−3.3V), if the potential of the gate terminal Gm1 is kept at −2 V potential or more, the memory Thyristor M1 is also turned on. the

When the memory thyristors M1 and M2 are turned on, the conduction current Jo flows into the memory thyristors M1 and M2 as shown in the currents J(M1) and J(M2). Subsequently, the potentials of the gate terminals Gm1 and Gm2 become "H" (0 V). the

In other words, immediately after the time point g, the transfer thyristor T2 and the memory thyristors M1 and M2 are in a conductive state. the

Subsequently, when the potential of the memory signal φm1 (φm) changes from “L” to “H” at the time point h, the potentials of the anode terminals and the cathode terminals of the memory thyristors M1 and M2 both become “H”, and thus the memory Both thyristors M1 and M2 are turned off. Similar to the case of time point d, the potentials of the gate terminals Gm1 and Gm2 start to change from "H" (0 V) toward the power supply potential Vga (−3.3 V). Therefore, current does not flow into memory thyristors M1 and M2, as shown in currents J(M1) and J(M2). the

Immediately after the time point h, the transfer thyristor T2 remains in the conducting state. the

When the potential of the first transfer signal φ1 changes from “H” to “L” at the time point i, the transfer thyristor T3 having a threshold voltage of −2.6 V is turned on. Subsequently, the potential of the gate terminal Gt3 increases to "H" (0 V). In addition, the threshold voltage of the transfer thyristor T4 connected to the gate terminal Gt3 through a one-stage forward-biased diode (coupling diode Dc3 ) becomes -2.6V. Similarly, the threshold voltage of the memory thyristor M3 (memory thyristor L3 ) whose gate terminal Gm3 (gate terminal G13 ) is connected to the gate terminal Gt3 through a first-stage diode (connection diode Dm3 ) becomes -2.6V. the

At this time, since the transfer thyristor T2 is kept in the on state, the second transfer signal line 73 connected to the cathode terminals of the even-numbered transfer thyristors T2, T4, . (-1.3V) potential. Therefore, the transfer thyristor T4 is not turned on. the

Immediately after time point i, the two transfer thyristors T2 and T3 remain in the conducting state. the

At time point j, the potential of the second transfer signal φ2 changes from "L" to "H". Subsequently, since the potentials of both the cathode terminal and the anode terminal of the transfer thyristor T2 become "H", the transfer thyristor T2 does not remain in the on state, and thus the transfer thyristor T2 turns off. the

At this time, since the gate terminal Gt2 of the transfer thyristor T2 is connected to the power supply line 71 through the power supply line resistance Rt2, the potential of the gate terminal Gt2 starts to change from "H" (0V) to the power supply potential Vga (-3.3V). Subsequently, the coupling diode Dc2 between the transfer thyristor T2 and the transfer thyristor T3 becomes reverse biased, and thus the gate terminal Gt3 which has become "H" (0 V) does not affect the gate terminal Gt2 . the

Immediately after the time point j, the transfer thyristor T3 remains in the conducting state. the

The writing period T( M1 ) is repeated from the writing period T( M3 ) from the time point k to the time point m. As described in the operation at time point g, at time point k, the potentials of the gate terminals Gm1 and Gm2 of the memory thyristors M1 and M2 are -2 V or more, and the threshold voltage of the memory thyristors M1 and M2 is -3.3 V or larger. Therefore, at time point k, if the memory signal φm1 (φm) changes from “H” (0V) to “L” (-3.3V), the memory thyristors except the memory thyristor M3 whose threshold voltage is -2.6V M1 and M2 are also ready to be switched on. Then, as shown in the currents J(M1), J(M2) and J(M3), the conduction current Jo flows into the memory thyristors M1, M2 and M3. The potentials of the gate terminals Gm1, Gm2, and Gm3 become 0V. the

In other words, immediately after the time point k, the transfer thyristor T3 and the memory thyristors M1 , M2 and M3 are kept in the on state. The threshold voltage of the memory thyristor M4 is -2.6V. the

Subsequently, when the potential of the memory signal φm1 (φm) changes from “L” (-3.3V) to “H” (0V) at time point l, the memory thyristors M1, M2, and M3 are turned off, and current does not flow into the memory In thyristors M1 , M2 and M3 this is shown in currents J(M1 ), J(M2) and J(M3). In addition, the potentials of the gate terminals Gm1 , Gm2 , and Gm3 of the memory thyristors M1 , M2 , and M3 start to change from 0 V to the power supply potential Vga (−3.3 V). the

Next, the writing period T( M4 ) from time point m to time point o will be described. At a time point m, the potential of the memory signal φm1 (φm) changes from “H” to “S”. At time point m, the threshold voltage of the memory thyristor M4 is -2.6V. However, unlike "L", "S" is set at a potential when the memory thyristor M whose threshold voltage is -2.6V is not turned on. For example, "S" is set at -2.5V. the

However, the potentials of the gate terminals Gm1 , Gm2 , and Gm3 of the memory thyristors M1 , M2 , and M3 start changing from 0 V to −3.3 V at time point 1 . Subsequently, at a time point m, if the potentials of these gate terminals Gm1, Gm2, and Gm3 are -1.2 V or more, the threshold voltages of the memory thyristors M1, M2, and M3 become -2.5 V or more. Therefore, when the memory signal φm1 (φm) changes from “H” to “S” (−2.5V) at time point m, the memory thyristors M1 , M2 and M3 are turned on again. However, as described above, the memory thyristor M4 is not turned on. the

Since the potential of the memory signal φm1 (φm) is “S”, the current flowing into the memory thyristors M1, M2, and M3 that have been turned on becomes the holding current Js smaller than the conduction current Jo, as in the current J(M1 ), J(M2) and J(M3). Note that since the memory thyristor M4 is in the off state, no current flows into the memory thyristor M4 as shown in Current J(M4). the

Therefore, immediately after the time point m, the transfer thyristor T4 and the memory thyristors M1 , M2 and M3 are in a conductive state. the

As described above, at the time point m, the memory thyristors M1 , M2 , and M3 are set in the on state, and the memory thyristor M4 is set in the off state. the

In other words, by setting the potential voltage "S" other than "H" and "L" for the memory signal φm, when the potential of the memory signal φm is changed from "H" to "S", it is made to turn off after being turned on. The memory thyristor M that was turned off is turned on again, while the memory thyristor M that has not been turned on remains off. That is, by using these two levels "S" and "L" according to circumstances, whether to turn on the memory thyristor M is selected. the

Therefore, when the potential of the memory signal φm1 (φm) changes from “H” to “L”, or from “H” to “S”, the memory thyristor M (for example, the memory thyristors M1 , M2 , which are turned off after being turned on) and M3) the potential of the gate terminal Gm becomes above a certain value obtained by adding the diffusion potential Vd (1.3V) to "S" (in the case of "S" being -2.5V , the value is -1.2V). the

The next writing period T( M5 ) from the time point o to the time point p repeats the writing period T( M3 ), but the transfer thyristor T and the memory thyristor M have different numbers. Similarly, the writing period T( M6 ) from the time point p to the time point q and the writing period T( M7 ) from the time point q to the time point r repeat the writing period T( M4 ). Therefore, its detailed description is omitted. the

The time point r and subsequent periods will be described next. the

At a time point r, the potential of the memory signal φm1 (φm) changes from “H” (0 V) to “L” (−3.3 V). Subsequently, since the threshold voltage of the memory thyristor M8 in the writing period T(M7) is -2.6V, the memory thyristor M8 is turned on. The potentials of the gate terminals Gm1, Gm2, Gm3, and Gm5 of the memory thyristors M1, M2, M3, and M5 are maintained at a voltage of -1.2 V or more, whereby the threshold voltage of the memory thyristors M1, M2, M3, and M5 is -2.5 V V or greater. Therefore, at time point r, the memory thyristors M1 , M2 , M3 and M5 are turned on. the

In other words, immediately after the time point r, the transfer thyristor T8 and the memory thyristors M1 , M2 , M3 and M5 are in a conductive state. the

For the current flowing into the memory thyristor M, at the time point r, the conduction current Jo flows into the memory thyristors M1, M2, M3, M5 and M8, which is as in the currents J(M1), J(M2), J(M3 ), J(M5) and J(M8). At the same time, no current flows into memory thyristors M4, M6 and M7, as shown in currents J(M4), J(M6) and J(M7). the

At a time point s, the potential of the memory signal φm1 (φm) changes from “L” to “S”. Since the cathode voltage of the memory thyristors M in the on state is -1.3V, the memory level potential "S" (-2.5V) keeps these memory thyristors M in the on state. the

At this time, the holding current Js flows into the memory thyristors M1, M2, M3, M5, and M8 as shown in the currents J(M1), J(M2), J(M3), J(M5) and J(M8). Show. At the same time, no current flows into the memory thyristors M4, M6 and M7 which are in the OFF state. the

The potentials of the gate terminals Gm1 , Gm2 , Gm3 , Gm5 , and Gm8 of the memory thyristors M1 , M2 , M3 , M5 , and M8 in the on state are “H” (0 V). Therefore, the threshold voltage of the light-emitting thyristors L1 , L2 , L3 , L5 , and L8 whose gate terminals Gl1 , Gl2 , Gl3 , Gl5 , and Gl8 are respectively connected to the respective gate terminals Gm1 , Gm2 , Gm3 , Gm5 , and Gm8 is −1.3V. Meanwhile, since the gate terminals Gm4, Gm6, and Gm7 of the respective memory thyristors M4, M6, and M7 in the off state are connected to the power supply potential Vga (-3.3 V) through the respective power supply line resistances Rm4, Rm6, and Rm7, the gate terminals Gm4, Gm6 and Gm7 are kept at -3.3V. Therefore, the threshold voltage of the light-emitting thyristors L4, L6, and L7 connected to the respective gate terminals Gl4, Gl6, and Gl7 to the respective gate terminals Gm4, Gm6, and Gm7 is -4.6V. the

Since the transfer thyristor T8 is in the on state, the potential of the gate terminal Gt8 is 0V. The light-emitting thyristor L9 (not shown in the figure) disposed adjacent to the light-emitting thyristor L8 and connected to the gate terminal Gt8 through two stages of forward-biased diodes (coupling diode Dc8 and connection diode Dm9 not shown in the figure) The potential of the gate terminal G19 (not shown in the figure) is -2.6V. Therefore, the threshold voltage of the light-emitting thyristor L9 is -3.9V. In addition, since the potential of the gate terminal G1 of each of the light-emitting thyristors L not smaller than 10 is equal to the power supply potential Vga (-3.3V), the threshold voltage of these light-emitting thyristors L is -4.6V. the

In other words, the threshold voltage of the light-emitting thyristors L1, L2, L3, L5 and L8 is -1.3V, the threshold voltage of the light-emitting thyristors L4, L6 and L7 is -4.6V, the threshold voltage of the light-emitting thyristor L9 is -3.9V, and each number The threshold voltage of the light-emitting thyristor L not less than 10 is -4.6V. the

Subsequently, the memory signal φm1 (φm) is maintained at the potential “S” until the time point u. During this period, the memory thyristors M1 , M2 , M3 , M5 and M8 are kept in the on state. the

In the above description, the potential of the memory signal φm1 (φm) is changed from “H” to “L” at the time point r of the writing period T(M8), thereby causing the light-emitting thyristors L1, L2, L3, and L5 to light up. In addition, the light-emitting thyristor L8 is also turned on. However, without causing the light-emitting thyristor L8 to light up, the potential of the memory signal φm1 (φm) changes from “H” to “S” at the start time point r of the writing period T( M8 ). the

Here, in order to describe the potential "Le" of the lighting signal φI1 (φI), the threshold voltage of the light-emitting thyristor L8 without causing the light-emitting thyristor L8 to light will be described. the

Without causing the light-emitting thyristor L8 to light, the potential of the memory signal φm1 (φm) changes from “H” (0 V) to “S” (−2.5 V) at the time point r. However, since the threshold voltage of the memory thyristor M8 is -2.6V, the memory thyristor M8 is not turned on. Meanwhile, as described above, since the potentials of the gate terminals Gm1, Gm2, Gm3, and Gm5 of the memory thyristors M1, M2, M3, and M5 are kept at -1.2 V or more, the threshold values of the memory thyristors M1, M2, M3, and M5 The voltage is -2.5V or greater. Therefore, at time point r, the memory thyristors M1 , M2 , M3 and M5 are turned on. Subsequently, the gate terminals Gm1, Gm2, Gm3, and Gm5 of the memory thyristors M1, M2, M3, and M5 all become 0V. Thus, the threshold voltages of the light-emitting thyristors L1, L2, L3, and L5 all become −1.3 V because the gate terminals Gl1, Gl2, Gl3, and Gl5 connected to the respective gate terminals Gm1, Gm2, Gm3, and Gm5 are all becomes 0V for sake. the

Since the transfer thyristor T8 is in an on state, the potential of its gate terminal Gt8 is 0V. In addition, since the gate terminal G18 of the light-emitting thyristor L8 is connected to the gate terminal Gt8 through the one-stage forward bias diode (connection diode Dm8), the potential of the gate terminal G18 becomes -1.3V. Therefore, the threshold voltage of the light emitting thyristor L8 becomes -2.6V. That is, in some cases, it was found that the threshold voltage of the light-emitting thyristor L that was not lit became -2.6V. the

Note that, except for the light-emitting thyristor L8, the threshold voltages of the other light-emitting thyristors L are the same as those in the above case where the light-emitting thyristor L8 is also turned on. the

Specifically, the threshold voltage of the light-emitting thyristor L1, L2, L3 and L5 is -1.3V, the threshold voltage of the light-emitting thyristor L4, L6 and L7 is -4.6V, the threshold voltage of the light-emitting thyristor L8 is -2.6V, and the threshold voltage of the light-emitting thyristor L9 The threshold voltage of the light-emitting thyristor L is -3.9, and the threshold voltage of each light-emitting thyristor L whose number is not less than 10 is -4.6V. the

During this period, the memory thyristors M1, M2, M3, and M5 are kept in the on state. the

As described above, the threshold voltage of the light-emitting thyristor L to be turned on is -1.3V, and the threshold voltage of the light-emitting thyristor L not to be turned on is -2.6V or less (≦-2.6). the

Therefore, in order to light the light-emitting thyristor L to be lit, the lighting level potential "Le" of the lighting signal φI1 (φI) is set at a value between more than -2.6V and not more than -1.3V (- 2.6<"Le"≤-1.3). the

At a time point t, the potential of the lighting signal φI1 (φI) changes from “H” to “Le”. Subsequently, the light-emitting thyristors L1, L2, L3, L5, and L8 are turned on and lighted (emit light) because their threshold voltage is -1.3V. At this time, since the current drive is given to the lighting signal φI1 (φI), the potential of the lighting signal line 75 does not become the potential of the cathode terminal of the light-emitting thyristor L in the on state, and the plurality of light-emitting thyristors L are simultaneously turned on. light up. the

However, since the threshold voltage of the light-emitting thyristors L other than these light-emitting thyristors L is -2.6V or less, they are not turned on and lit (no light is emitted).

Therefore, immediately after the time point t, the transfer thyristor T8 and the memory thyristors M1, M2, M3, M5, and M8 are kept in a conducting state, while the light-emitting thyristors L1, L2, L3, L5, and L8 are kept in a lighted (conducting) state. state. the

At time point u, the potential of the memory signal φm1 (φm) changes from “S” to “H”. Subsequently, since both the cathode terminal and the anode terminal of the memory thyristors M1, M2, M3, M5 and M8 become potential "H", the memory thyristors M1, M2, M3, M5 and M8 are no longer kept in the conduction state, and by Therefore they are turned off. Therefore, no current flows into the memory thyristors M1 , M2 , M3 , M5 and M8 as shown in currents J(M1 ) to J(M8). the

At the same time point u, the potential of the first transfer signal φ1 changes from "H" to "L". Subsequently, the transfer thyristor T9 with a threshold voltage of -2.6V is turned on. Also, the threshold voltage of the transfer thyristor T10 is set at -2.6V. In addition, since the potential of the gate terminal Gt9 (not shown in FIG. 5 ) of the transfer thyristor T9 (not shown in FIG. 5 ) becomes 0 V, thereby the Shown)) The potential of the gate terminal Gm9 (not shown in FIG. 5) of the memory thyristor M9 (not shown in FIG. 5) connected to the gate terminal Gt9 becomes −1.3 V, and the threshold voltage of the memory thyristor M9 becomes -2.6V. At this time, even if the memory signal φm1 (φm) is kept at the potential "S", the memory thyristor M9 is not turned on. In addition, even if the potential of the memory signal φm1 (φm) becomes “H”, the memory thyristor M9 is not turned on. the

Immediately after the time point u, the transfer thyristors T8 and T9 are kept in the on state, and the light-emitting thyristors L1 , L2 , L3 , L5 , and L8 are kept in the lighted (on) state. the

Note that in the first exemplary embodiment, at the time point u, the potential change of the memory signal φm1 (φm) from “S” to “H” and the potential of the first transfer signal φ1 from “H” to “L” Changes happen simultaneously. As described above, even if the potential of the memory signal φm1 (φm) is “S” or “H”, the memory thyristor M9 is not turned on. Therefore, there is no problem even if any of these changes are made first. the

At the time point v, the potential of the second transfer signal φ2 changes from "L" to "H". Subsequently, the potentials of both the cathode terminal and the anode terminal of the transfer thyristor T8 become "H", so the transfer thyristor T8 is no longer kept in the on state, and thus the transfer thyristor T8 is turned off. the

Immediately after the time point v, the transfer thyristor T9 remains in the ON state, and the light-emitting thyristors L1 , L2 , L3 , L5 , and L8 remain in the lighted (conducting) state. the

At the time point x, the potential of the lighting signal φI1 (φI) changes from “Le” to “H”. Subsequently, since the potentials of the cathode terminals and the anode terminals of the light-emitting thyristors L1, L2, L3, L5, and L8 both become "H", the light-emitting thyristors L1, L2, L3, L5, and L8 are no longer kept in the conduction state, and They are thus switched off and extinguished. In other words, the light-emitting thyristors L1 , L2 , L3 , L5 , and L8 have been turned on during the period from the time point t to the time point x (light-emitting period t4 ). the

Immediately after the time point x, the transfer thyristor T9 remains in the conducting state. the

At a time point y, the potential of the memory signal φm1 (φm) changes from “H” to “L”. Subsequently, the memory thyristor M9 having a threshold voltage of -2.6V is turned on. the

The period from the time point y is the lighting control period T(#B) when the group #B (light-emitting thyristors L9 to L16 ) shown in FIG. 6 is driven. The lighting control period T(#B) repeats the lighting control period (#A) except for the memory signal φm1 (φm) set according to the image data set. In other words, the time point y of the lighting control period T(#B) corresponds to the time point c of the lighting control period T(#A). The subsequent lighting control period T(#C)... is the same as above. the

In the first exemplary embodiment, according to the image data set "11101001", the light-emitting thyristors L1, L2, L3, L5, and L8 are caused to light up (emit light) simultaneously in the light-emitting period t4 of the light-up control period T(#A) . the

The above description will be summarized below. the

In the first exemplary embodiment, the transfer thyristor T has a period (for example, a period from time point e to time point f) in which both Each of the adjacent transfer thyristors T enters the conduction state, and the transfer thyristors T are set to change from the off state to the conduction state and from the conduction state to the off state in numerical order. In other words, the conduction state is changed according to the number sequence of the transfer thyristor array. the

During a period in which either one of the first transfer signal φ1 and the second transfer signal φ2 has a potential “L”, only one transfer thyristor T is in the on state (for example, from time point f to time point i in FIG. 7 During the time period, only the transfer thyristor T2 is in the conduction state). the

When the transfer thyristor T enters the conduction state, the potential of its gate terminal Gt increases to "H" (0V), and the threshold voltage of the memory thyristor M connected to the gate terminal Gm increases (-2.6V). At the timing when only one transfer thyristor T is in the on state (for example, time points c, g, and k in FIG. 7), if the potential of the memory signal φm is set at “L” (−3.3 V), there is The increased threshold voltage of the memory thyristor M turns on. Subsequently, the potential of the gate terminal Gm increases to "H" (0 V). Meanwhile, if the potential of the memory signal φm is set at “S” (−2.5V) between “H” and “L”, the memory thyristor M having an increased threshold voltage is not turned on. the

Thereafter, the memory thyristor M that has been turned on is turned off. Thereby, the potential of the gate terminal Gm of the memory thyristor M which is turned off after being turned on changes from "H" (0 V) to "L" (−3.3 V). However, before the potential of the gate terminal Gm is lower than the predetermined potential (-1.2V), the potential of the memory signal φm is made to become "L" (-3.3V) or "S" (-2.5V) again, thereby making the connection The memory thyristor M which was switched off after being switched on is switched on again (for example at times g, k and m). the

As described above, at the timing when only one transfer thyristor T is in the on state, in the case where the light-emitting thyristor L is turned on according to the image data set (for example, in the case of the image data set "1"), the memory signal φm The potential becomes "L" (-3.3 V), while the potential of the memory signal φm becomes "S" ( -2.5V). Therefore, only the memory thyristor M having the same number as the light-emitting thyristor L corresponding to the image data set "1" (causing lighting up) is turned on. the

If the already switched-on memory thyristor M is switched off, it is switched on again. Accordingly, the position (number) of the light-emitting thyristor L that caused lighting is stored. At this time, the number of light-emitting thyristors L to be turned on may be plural. At the time point (time point r in the first exemplary embodiment) at which the writing period T(M) corresponding to the predetermined number of digits ends, all the memory thyristors M corresponding to the light-emitting thyristor L causing lighting are turned on. . the

When the memory thyristor M is in the ON state, the threshold voltage of the light-emitting thyristor L having the same number as the memory thyristor M increases (to -1.3V). Therefore, by changing the potential of the lighting signal φI from "H" to "Le", the light-emitting thyristor L having the same number as the memory thyristor M in the on state is turned on and lit (emits light). the

In other words, the memory thyristor M has a function (latch function) of storing the position (number) at which the light-emitting thyristor L is turned on according to the image data set. the

The potential "L" of the memory signal φm is used as a signal for storing the position (number) of the light-emitting thyristor L that is lit according to the image data set, and the potential "S" of the memory signal φm is used as a memory that turns on and then turns off. Signal to turn on the thyristor M again (refresh signal). However, the potential "S" does not cause the other memory thyristors M to turn on. In other words, the stored information that the memory thyristor M has turned on is held until the light-emitting thyristor L is turned on and lights up (emits light). the

Note that when the light-emitting thyristor L is turned on (emits light), the memory thyristor M does not need to store the position (number) of the light-emitting memory L to be turned on any more. In order to reset the stored information of the memory thyristor M (the history of turning on the memory thyristor L), it is only necessary to make the threshold voltage of the memory thyristor M low (<−3.3 V), that is, to make the potential of the gate terminal Gm low ( <-2V), thereby preventing the memory thyristor M, which was turned off after being turned on, from being turned on again even if the potential of the memory signal φm becomes "L" (-3.3V). As described above, the potential of the gate terminal Gm changes according to the time constant defined by the parasitic capacitance of the gate terminal Gm and the power supply line resistance Rm. Therefore, for example, the reset period t5 (from the time point u to the time point y in FIG. 7 ) after setting the potential of the memory signal φm at "H" to "L" again can be set longer , so that the potential of the gate terminal Gm becomes lower. the

The driving method in the first exemplary embodiment is so-called dynamic driving. Refreshing is repeated while the potential (charge) of the gate terminal Gm of the memory thyristor M is not lower than the threshold voltage. By this operation, the memory thyristor M that has been turned on continues to be stored. the

Note that since the threshold voltage of the memory thyristors M which are not turned on remains at -3.9V or -4.6V as described above, these memory thyristors M remain in the off state. the

The cathode terminals of the memory thyristors M are connected through respective resistors Rn to a memory signal line 74 supplied with a memory signal φm. Although the cathode terminal of the memory thyristor M in the on state has a potential obtained by subtracting the diffusion potential Vd (1.3 V) from the anode terminal (0 V), the memory signal line 74 can be held at the memory signal φm by using the resistor Rn. potential. Therefore, a plurality of memory thyristors M can be brought into an on state at the same time. the

Note that in the circuit of FIG. 4, the lighting signal φI can be driven by a current. In addition, in order to suppress variation in the amount of light emitted from the light-emitting points (light-emitting thyristors L), the current value to be supplied may be made to vary according to the number of light-emitting points (light-emitting thyristors L) that simultaneously cause lighting. In the above description, it is described that the lighting signal φI is supplied by current driving, and when a plurality of light-emitting thyristors L are turned on for one light-emitting period t4, a current corresponding to the number of light-emitting thyristors L is supplied. the

In contrast, when the lighting signal φI is driven (voltage driven) at a predetermined voltage, the current flowing in the light-emitting thyristor L that lights up (lights up) becomes constant. In this case, in order to light up a plurality of light-emitting thyristors L in one light-emitting period, it is only necessary to provide a resistor between the lighting signal line 75 and each cathode terminal of the light-emitting thyristor L, as between the memory signal line 74 and each cathode terminal. The resistors Rn are set between the memory thyristors M to be the same. If this is not the case, the potential of the lighting signal line 75 becomes a potential (−1.3 V) obtained by subtracting the diffusion potential Vd from the potential of the anode terminal of one light-emitting thyristor L in the on state. Therefore, the other light-emitting thyristor L is no longer switched on and does not light up. the

If the lighting signal φI is driven with a current, it is acceptable not to provide a resistance between the lighting signal line 75 and each cathode terminal of the light-emitting thyristor L. In this case, using the power supply potential V, the diffusion potential Vd, and the external resistance R, the current flowing into the light-emitting chip C is defined as I=(V-Vd)/R. Therefore, the current flowing into each of the plurality of light-emitting thyristors L that are simultaneously lit (lit) for one light-emitting period t4 has a value obtained by dividing 1 by the number of light-emitting thyristors L that are lit (lit). Thus, depending on the number of light-emitting thyristors L that are simultaneously lit (lighted) in one light-emitting period, the current flowing into each light-emitting thyristor L is different, and thus, the light intensity of each light-emitting thyristor L is different. In order to avoid this, the current value to be supplied can be changed according to the number of light-emitting thyristors L which cause lighting. the

The number of light-emitting thyristors L simultaneously caused to be turned on in one light-emitting period t4 is obtained by using the image data set provided to the light-emitting chip C, and thus the current value can be set according to the number of light-emitting thyristors L simultaneously turned on. the

The current flowing into the memory thyristor M will be described using FIG. 7 . Note that the lighting control period T(#A) from time point c to time point y is described here. the

As described above, by changing the potential of the memory signal φm from "H" to "L" at the time point c, the memory thyristor M1 is turned on. Subsequently, at a time point d, the memory thyristor M1 is turned off by changing the potential of the memory signal φm from “L” to “H”. In other words, during the period t2 from time point c to time point d when the potential of the memory signal φm is “L”, the memory thyristor M1 enters the conduction state, and conduction current Jo flows into the memory thyristor M1 . The memory thyristor M1 is switched on again at the point in time g and switched off at the point in time h. Also during this period, the conduction current Jo flows into the memory thyristor M1. The same operation is repeated during the period from time point k to time point 1. By changing the potential of the memory signal φm from “H” to “S” at the time point m, the memory thyristor M1 is turned on, and then by changing the potential of the memory signal φm from “S” to “ H", so that the memory thyristor M1 is turned off. During this period, the holding current Js smaller than the on-current Jo flows into the memory thyristor M1 because the potential of the cathode terminal of the memory thyristor M1 is "S". Similarly, during the period t2 from the respective time points o, p, q, and r, the ON current Jo, the holding current Js, the holding current Js, and the ON current Jo flow into the memory thyristor M1, respectively. Therefore, the period from the time point c to the time point s includes 5 periods in which the conduction current Jo flows into the memory thyristor M1, and 3 periods in which the sustain current Js flows in the memory thyristor M1. the

Similarly, for the memory thyristor M2, the period from the time point c to the time point s includes 4 periods during which the conduction current Jo flows into the memory thyristor M2 and 3 periods during which the holding current Js flows into the memory thyristor M2. the

Similarly, for the memory thyristor M3, the period from the time point c to the time point s includes 3 periods during which the conduction current Jo flows into the memory thyristor M3 and 3 periods during which the holding current Js flows into the memory thyristor M3. the

Similarly, for the memory thyristor M5, the period from the time point c to the time point s includes 2 periods during which the conduction current Jo flows into the memory thyristor M5 and 2 periods during which the holding current Js flows into the memory thyristor M5. the

For the memory thyristor M8, the period from the time point c to the time point s includes 1 period in which the conduction current Jo flows into the memory thyristor M8. the

On the other hand, for the memory thyristors M4, M6, and M7, neither the conduction current Jo nor the holding current Js flows into the memory thyristors during the period from the time point c to the time point s. the

Therefore, for the memory thyristors M1 to M8, there are 15 periods in which the conduction current Jo flows into the memory thyristors, and 11 periods in which the sustain current Js flows into the memory thyristors. the

Note that in the lighting control period T(#A), the period from the time point s to the time point u in which the holding current Js flows into the memory thyristor is ignored. the

Assume that "L" is set at -3.3V, "S" is set at -2.5V, period t1 (same as writing period T(M1)) is set at 100 ns, and period t2 is set at 10 nanoseconds. In addition, the resistance Rn connected to each cathode terminal of the memory thyristor M was set to 1 kΩ. The potential of the cathode terminal of the memory thyristor M in the ON state is -1.3V, which is obtained by subtracting the diffusion potential Vd (1.3V) from the potential of the anode terminal ("H" (0V)). the

Therefore, a voltage of -2V (=(-3.3V)-(-1.3V)) is applied across the resistance Rn during the period in which the on-current Jo flows into the memory thyristor M. Therefore, the on-current Jo becomes 2mA (=2V/1kΩ). the

At the same time, -1.2V (=(-2.5V)-(-1.3V)) is applied across the resistance Rn during the period in which the sustain current Js flows into the memory thyristor M. Therefore, the holding current Js becomes 1.2 mA (=1.2 V/1 kΩ). the

Therefore, the energy consumed by the memory thyristor M and the resistor Rn in the period from time point c to time point s is calculated to be 1.32 nanojoules (=15 times×10 nanoseconds×2mA×3.3V+11 times×10 nanoseconds ×1.2mA×2.5V). the

The period from time point c to time point s is 710 nanoseconds. If the lighting duty (the ratio of the lighting period t4 to the lighting control period T(#A)) is set to 50%, the lighting control period T(#A) is set to 1420 nanoseconds. the

Therefore, the energy consumed by the memory thyristor M and the resistance Rn during the above period from the time point c to the time point y is an average power consumption of 0.93 mW. the

Returning to the light emitting portion 63, its operation is considered further. As described above, the light emitting chips C2 to C60 of the light emitting part 63 operate in parallel with the light emitting chip C1 as described above. In the lighting control period T(#A) in which lighting control is performed on the light-emitting thyristors L1 to L8 of the light-emitting chip C1 , light-emitting control is performed on the light-emitting thyristors L1 to L8 of each of the other light-emitting chips C2 to C60 in parallel. the

Similarly, in the lighting control period T(#B) in which lighting control is performed on the light-emitting thyristors L9 to L16 of the light-emitting chip C1, the light-emitting thyristors L9 to L16 of each of the other light-emitting chips C2 to C60 of the light-emitting portion 63 Light emission control is performed in parallel. In the other lighting control period T(#C), the same lighting control is performed. the

The period during which the potential of the lighting signal φI is set at “Le” (from the time point t to the time point x in FIG. 7 ) determines the light emission period t4 of the light-emitting thyristor L. In the first exemplary embodiment, each of the lighting signals φI (φI1 to φI30 ) is supplied to corresponding two of the light-emitting chips C. Therefore, in the light-emitting chip C supplied with one lighting signal φI (for example, the light-emitting chips C1 and C2 supplied with the lighting signal φI1 in FIG. 4 ), the light-emitting periods t4 thereof are equal to each other. However, since a different light-emitting period t4 can be set for each group (for example, for groups #A and #B), variations in light intensity can be corrected for each group of light-emitting chips C. the

Alternatively, variations in light intensity between light-emitting chips C may be corrected by setting the light-emitting period t4 for each lighting signal φI. the

Note that it has been described that the light-emitting thyristors L1 , L2 , L3 , L5 , and L8 are turned on (lighted) and the light-emitting thyristors L4 , L6 , and L7 are not turned on (turned off) in the lighting control period T(#A). As described above, when causing the light-emitting thyristor L to light, it is only necessary to set the potential of the memory signal φm at "L". Meanwhile, when the light-emitting thyristor L is not caused to light, it is only necessary to set the potential of the memory signal φm at "S". Since the memory signal φm is supplied to each light-emitting chip C shown in FIG. 4, it is possible to control whether to cause the light-emitting thyristor L to light up (emit light) according to the image data set. the

FIG. 8 is a timing chart illustrating the operation of the light emitting chip C1 (C) in the case where the first exemplary embodiment is not applied. Except for the following description, the operation is the same as the case shown in FIG. 7 to which the first exemplary embodiment is applied. In other words, the structure of the signal generating circuit 100 in the light emitting device 65 and the wiring structure between the signal generating circuit 100 and each light emitting chip C ( C1 to C60 ) are the same as those shown in FIG. 4 . In addition, the circuit structure of the light-emitting chip C is the same as that shown in FIG. 5 . In the lighting control period T(#A), it is assumed that the image data set "11101001" is printed. the

The difference between FIG. 8 and the case of the first exemplary embodiment ( FIG. 7 ) is the waveform of the memory signal φm1 (φm) in the period from time point c to time point r. The driving method here is not dynamic driving but static driving. the

In the case where the first exemplary embodiment is applied (FIG. 7), by setting the potential of the memory signal φm at "L" or "S" before the potential of the gate terminal Gm of the memory thyristor M becomes smaller than a predetermined value, The memory thyristor M that was turned off after being turned on is turned on, so as to prevent the loss of the stored information that the memory thyristor M has been turned on. the

On the other hand, in the case where the first exemplary embodiment is not applied, the memory thyristor M that has been turned on is not turned off, and remains in the on state. the

The waveform of the memory signal φm1 will be described. the

The potential of the memory signal φm1 (φm) changes from “H” to “L” at the start time point c of the writing period T( M1 ), and changes from “L” to “S” at the time point d. Subsequently, its potential is maintained at "S" until a time point g which is an end time point of the writing period T( M1 ). Its potential changes from "S" to "L" at a time point g also as a start time point of the writing period T( M2 ), and then changes from "L" to "S" at a time point h. Its potential is kept at "S" until time point k which is the end time point of the writing period T( M2 ). That is, the waveform in the writing period T(M2) repeats the waveform in the writing period T(M1). Then, also in the subsequent writing period T(M3), the same waveform is repeated. the

However, the potential of the memory signal φm1 (φm) is kept at “S” until the time point m which is the start time point of the write period T(M4), and at the time point which is the start time point of the write period T(M5) o from "S" to "L". The waveform of the memory signal φm1 in the writing period T( M5 ) repeats the waveform in the writing period T( M1 ). The waveform of the memory signal φm1 (φm) in the writing periods T(M6) and T(M7) repeats the waveform in the writing period T(M4). In addition, in the present exemplary embodiment, the waveform of the memory signal φm1 (φm) in the writing period T( M8 ) is the same as that in the writing period T( M8 ) in the first exemplary embodiment. the

Next, the operation of the memory thyristor M will be described. the

Immediately after time point b in FIG. 8 , the transfer thyristor T1 is in a conducting state, and the threshold voltage of the memory thyristor M1 is -2.6V. When the potential of the memory signal φm1 (φm) changes from “H” (0V) to “L” (−3.3V) at time point c, the memory thyristor M1 with a threshold voltage of −2.6V is turned on. the

Subsequently, at a time point d, the potential of the memory signal φm1 (φm) changes from “L” to “S”. The potential of the cathode terminal of the memory thyristor M1 in the on state is -1.3V, which is obtained by subtracting the diffusion potential Vd (1.3V) from the potential of the anode terminal ("H" (0V)). Therefore, "S" of -2.5V is used to maintain the on state of the memory thyristor M1. In other words, at time point d, the memory thyristor M1 is not turned off, but remains in the on state. the

Therefore, as shown in the current J(M1), the ON current Jo flows into the memory thyristor M1 from the time point c to the time point d, and the holding current Js flows into the memory thyristor M1 from the time point d to the time point f. the

Similarly, when the potential of the memory signal φm1 (φm) changes from “S” (−2.5V) to “L” (−3.3V) at the time point g, the memory thyristor M2 is turned on. At the same time, since the memory thyristor M1 is kept in the on state, the current flowing into the memory thyristor M1 changes from the holding current Js to the turning-on current Jo. From the time point g to the time point h, the conduction current Jo flows into the memory thyristor M1, and from the time point h to the time point k, the sustain current Js flows into the memory thyristor M1. Meanwhile, as shown in the current J(M2), the ON current Jo flows into the memory thyristor M2 from the time point g to the time point h, and the sustain current Js flows into the memory thyristor M2 from the time point h to the time point k. the

The writing period T(M3) repeats the writing period T(M1), and the memory thyristor M3 is turned on again. At the end time point m of the writing period T( M3 ), the memory thyristors M1 , M2 and M3 are kept in the on state. the

At the start time point m of the writing period T( M4 ), the potential of the memory signal φm1 (φm) is kept at “S”. Therefore, in the writing period T(M3), the memory thyristor M4 whose threshold voltage is -2.6V is not turned on. Therefore, at the time point m, the memory thyristors M1, M2, and M3 are kept in the on state. the

In the writing period T( M5 ), since the potential of the memory signal φm1 (φm) changes from “S” to “L”, the memory thyristor M5 is turned on. However, in the writing periods T( M6 ) and T( M7 ), since the potential of the memory signal φm1 (φm) remains at “S”, the memory thyristors M6 and M7 are not turned on. Thereafter, at the start time point r of the writing period T( M8 ), since the potential of the memory signal φm1 (φm) changes from “S” to “L”, the memory thyristor M8 is turned on. the

Although a detailed description thereof is omitted, current flows into the memory thyristors M1 to M8 as shown by currents J(M1) to J(M8) in the writing periods T(M3) to T(M7). the

The operations from time point r to time point y are the same as those already described in the case ( FIG. 7 ) to which the first exemplary embodiment is applied. In other words, when the potential of the lighting signal φI1 (φI) changes from “H” to “Le” at the time point t, each light-emitting thyristor L (here, light emitting thyristor L) having the same number as each memory thyristor M in the on state Thyristors L1 , L2 , L3 , L5 and L8 ) are turned on and lighted (emit light). the

As described above, in the case where the first exemplary embodiment is not applied, the memory thyristor M that has been turned on remains in the on state, and the potential of the gate terminal Gm thereof is kept at "H" (0 V). Therefore, unlike the first exemplary embodiment, it is not necessary to change the potential of the memory signal φm1 (φm) from “L” to “S” before the potential of the gate terminal Gm becomes a predetermined potential. In other words, in FIG. 8, the length of the period t3 from the time point d to the time point g is not limited. the

However, in the case where the first exemplary embodiment is not applied ( FIG. 8 ), the power consumption of the memory thyristor M increases. For example, the sustain current Js flows into the memory thyristor M in the period from the time point d to the time point g in the writing period T( M1 ). There are 21 periods during which the sustain current Js flows into the memory thyristor M. Therefore, the energy consumed by the memory thyristor M and the resistance Rn in the period from the time point c to the time point s has a value (6.99 nanojoules) which is obtained by multiplying 5.67 nanojoules (=21 times×90 nanojoules seconds x 1.2 mA x 2.5 V) to the value of 1.32 nJ as described in Figure 7. Therefore, dividing this value by 1420 nanoseconds for the period from time point c to time point y yields an average power consumption of 4.92 mW. the

Therefore, the average power consumption (0.93mW) in the first exemplary embodiment shown in FIG. 7 is one-fifth of the average power consumption (4.92mW) shown in FIG. 8 without applying the first exemplary embodiment . the

Assume that the current in the case where the light-emitting thyristor L is turned on (emits light) is 10 mA. In this state, the current in the case where five light-emitting thyristors L1, L2, L3, L5, and L8 are lit as shown in FIGS. 7 and 8 becomes 50 mA. Also assuming that the light emission duty ratio of the light emission period t4 from the time point t to the time point x in FIGS. 7 and 8 is 50%, the potential applied to the light emitting thyristor L is -2V. In this state, the power consumption of the five light-emitting thyristors L in the on state becomes 50 mW (=0.5×5 light-emitting thyristors×10 mA×2 V). the

The power consumption in the memory thyristor M without applying the first exemplary embodiment is 10% of the power consumption in the light emitting thyristor L. the

Therefore, in the first exemplary embodiment, since the power consumption of the memory thyristor M can be reduced, the power consumption of the light emitting chip C can be suppressed. the

Note that the above-mentioned power consumption is only an example, and the power consumption varies depending on the number of light-emitting thyristors L lit and the light-emitting duty ratio. the

Next, the potential change of the gate terminal Gm of the memory thyristor M after the memory thyristor M is turned off in the first exemplary embodiment will be described. the

FIG. 9 is a graph showing one example of a change in the threshold voltage of the memory thyristor M and the potential of the gate terminal Gm after the memory thyristor M is turned off. The horizontal axis represents the time (nanoseconds) after the memory thyristor M is turned off, and the vertical axis represents the potential (V) of the gate terminal Gm and the threshold voltage (V) of the memory thyristor M. Although, in the above description, the potential of the gate terminal Gm of the memory thyristor M in the on-state is assumed to be 0V, however, here it is set to a real value -0.2V (the potential at 0 nanoseconds after the memory thyristor M is turned off). potential at the gate terminal). the

Here, it is assumed that the parasitic capacitance of the gate terminal Gm is 25 pF, and the power supply line resistance Rm is 20 kΩ. Therefore, the potential of the gate terminal Gm of the memory thyristor M decreases with a time constant of 500 nanoseconds (=25 pF×20 kΩ). the

In response to the time elapsed after the memory thyristor M is turned off, the potential of the gate terminal Gm of the memory thyristor M decreases from -0.2V to the power supply potential Vga (-3.3V). The value of the threshold voltage of the memory thyristor M is obtained by subtracting the diffusion potential Vd (1.3V) from the potential of the gate terminal Gm, and thereby decreases from -1.5V to -4.6V. the

At 200 nm after the memory thyristor M is turned off, the potential of the gate terminal Gm decreases to -1.2V, that is, referring to FIG. 9 , the threshold voltage of the memory thyristor M decreases to -2.5V. the

Therefore, in the first exemplary embodiment shown in FIG. 7, only the period t3 (for example, the period from time point d to time point g in FIG. 7, the period from time point l to time point m, etc. etc.) are set within 200 nm such that a memory thyristor that was turned off after being turned on is turned on again. If the period t3 exceeds 200 nanoseconds, since the threshold voltage is less than -2.5V, the potential "S" (-2.5V) of the memory signal φm1 (φm) no longer causes the memory thyristor M to be turned on, and the memory thyristor M is already turned on. The stored information is lost from the memory thyristor M. the

Note that the values shown in FIG. 9 are an example, and the allowable length of the period t3 varies according to the parasitic capacitance of the gate terminal Gm of the memory thyristor M and the value of the power supply line resistance Rm. For example, if the power supply line resistance Rm is made larger, the time constant becomes larger, whereby the time for the potential of the gate terminal Gm to decrease to -1.2V becomes longer than 200 nanoseconds. On the contrary, if the power supply line resistance Rm is made small, the time constant becomes small, whereby the time for the potential of the gate terminal Gm to decrease to -1.2V becomes less than 200 nanoseconds. Similarly, the parasitic capacitance of the gate terminal Gm causes the length to vary. the

Therefore, the time constant can be adjusted using the parasitic capacitance of the gate terminal Gm of the memory thyristor M and the value of the power supply line resistance Rm. the

<Second Exemplary Embodiment>

FIG. 10 is a timing chart illustrating the operation of the light-emitting chip C1 (C) in the second exemplary embodiment. the

In the second exemplary embodiment, the structure of the signal generating circuit 100 in the light emitting device 65 and the wiring structure between the signal generating circuit 100 and each light emitting chip C (C1 to C60) are the same as those of the first example shown in FIG. The structure in the embodiment is the same. The circuit structure of the light emitting chip 100 is the same as that in the first exemplary embodiment shown in FIG. 5 . the

In the first exemplary embodiment, the signal “L” or “ S" (memory signal φm). the

However, as described above, as an example, the period t3 until the memory thyristor M is turned on again after the memory thyristor M that has been turned on is turned off is 200 nanoseconds. The period t3 is determined by the parasitic capacitance of the gate terminal Gm and the power supply line resistance Rm, and thus the variable range of the period t3 is limited. the

At the start time point (time point y in FIGS. 7 and 10 ) of the lighting control period T(#B), the memory thyristor M should be set in each memory thyristor M for the lighting control period T(#A). The stored information that has been turned on is reset. In order to reset the stored information, the potential of the gate terminal Gm is required to be less than -2V at the reset period t5 from the time point u to the time point y, at which the potential of the memory signal φm1 (φm) is in the lighting control Changing from "S" to "H" last in the period T(#A), at time point y, the potential of the memory signal φm1(φm) changes from "H" to "H" for the first time in the lighting control period T(#B) "L" or "S". In the example shown in FIG. 9 , in order to make the potential of the gate terminal Gm smaller than −2 V, it takes not less than 400 nanoseconds after the memory thyristor M is turned off. Therefore, the reset period t5 may be too long in some cases. the

Meanwhile, the period t4 may be shorter if the time constant is set shorter by adjusting at least any one of the parasitic capacitance of the gate terminal Gm of the memory thyristor M and the power supply line resistance Rm. However, period t3 is also shorter. the

In order to avoid this, in the second exemplary embodiment, the potential of the newly added memory signal φm becomes “ S" period, thereby updating the stored information that the memory thyristor M has been turned on. Therefore, the period t3 can be set larger than the period determined by the time constant defined by the parasitic capacitance of the gate terminal Gm of the memory thyristor M and the power supply line resistance Rm. the

In FIG. 10 , a period for resetting the potential of the memory signal φm1 (φm) to “S” is added to the writing period T(M) in FIG. 7 in the first exemplary embodiment. In other words, the potential of the memory signal φm1 (φm) changes from “H” to “S” at a time point α after the time point d and before the time point e in the writing period T(M1), and at the time point α After that and at a time point β before the time point e, it changes from "S" to "H". the

The operation of the light emitting chip C1(C) at the time point α is the same as the operation at the time point m in FIG. 7 in the already described first exemplary embodiment. Specifically, if the potential of the gate terminal Gm1 of the memory thyristor M1 turned on at the time point c and turned off at the time point d is not less than −1.2 V at the time point α, the threshold voltage of the memory thyristor M1 does not less than -2.5V. Therefore, by changing the potential of the memory signal φm1 (φm) from “H” (0 V) to “S” (−2.5 V) at the time point α, the memory thyristor M1 is turned on again. Similarly, if the potential of the gate terminal Gm1 is not less than -1.2V, the threshold voltage of the memory thyristor M1 which has been turned off at the time point β at the time point g is not less than -2.5V. Therefore, by changing the potential of the memory signal φm1 (φm) from “H” (0 V) to “L” (−3.3 V) at the time point g, the memory thyristor M1 is turned on again. the

The same is true for the other writing periods T(M2) to T(M7). For these periods T(M2) to T(M7), detailed description will be omitted. Note that in the writing period T( M8 ), the operation is the same as that in the first exemplary embodiment. the

As described above, in the second exemplary embodiment, in the middle of the writing period T(M) (for example, the period from the time point α to the time point β in the writing period T(M1)), the memory signal is set The potential of φm1 (φm) is set for a period of “S”. This is because the stored information that the memory thyristor M has been turned on is updated as described above. Note that the potential of the memory signal φm1 (φm) is set at “S” instead of “L”, thereby preventing new memory thyristors M from being turned on. the

In addition, in the second exemplary embodiment, although a period in which the potential is set at "S" to update the memory is provided in the middle of the writing period T(M), it is possible to Set multiple time periods. It is only necessary to set a period of time for setting the potential at "S" for refresh so that the memory thyristor M which was turned off after being turned on is turned on again. Therefore, the length of the period t3 and the reset period t5 can be set individually. the

<Third Exemplary Embodiment>

11 is a schematic diagram showing the structure of the signal generating circuit 100 in the light emitting device 65 in the third exemplary embodiment and the wiring structure between the signal generating circuit 100 and each light emitting chip C ( C1 to C60 ). the

The difference between the third exemplary embodiment and the first exemplary embodiment shown in FIG. 4 lies in the cancellation signal generation unit 140 newly provided in the third exemplary embodiment. The erasing signal generation generating unit 140 is used for the signal generating unit 100 to transmit an erasing signal φe for erasing charges accumulated in the parasitic capacitance of each gate terminal Gm to the light emitting chips C (C1 to C60). the

On the circuit board 62 , in addition to the structure of the first exemplary embodiment shown in FIG. 4 , a cancel signal line 102 is newly provided. The erasing signal line 102 sends the erasing signal φe from the erasing signal generating unit 140 of the signal generating circuit 100 to the light emitting section 63 . The cancellation signal line 102 is connected in parallel to φe terminals of the light emitting chips C ( C1 to C60 ) (see FIG. 12 described later). the

Other structures are the same as those in the first exemplary embodiment shown in FIG. 4 . Therefore, in the third exemplary embodiment, the same reference numerals are given to the same components as those in the first exemplary embodiment, and a detailed description thereof is omitted. the

In the first exemplary embodiment, the potential of the gate terminal Gm of the memory thyristor M which is turned off after being turned on is changed from 0 V to −3.3 V after the memory thyristor M is turned off. This rate of change is determined by a time constant defined by the parasitic capacitance of the gate terminal Gm of the memory thyristor M and the power supply line resistance Rm. Therefore, it is not allowed to set the reset period t5 for resetting the storage information of the memory thyristor M of which the memory thyristor M has been turned on independently of the period t3. In the third exemplary embodiment, the reset period t5 is set shorter by forcibly setting the potential of the gate terminal Gm with the erase signal φe. the

In the third exemplary embodiment, the reference potential Vsub, the power supply potential Vga, the first transfer signal φ1, the second transfer signal φ2, and the erasing signal φe are commonly sent to all the light emitting chips C (C1 to C60). According to the image data set, the memory signals φm (φm1 to φm60) are individually sent to the light-emitting chips C (C1 to C60). Each lighting signal φI (φI1 to φI30) is sent to corresponding two light emitting chips C (C1 to C60). the

12 is a schematic diagram illustrating a circuit configuration of light-emitting chips C ( C1 to C60 ) as self-scanning light-emitting element array (SLED) chips in the third exemplary embodiment. Here, the light-emitting chip C1 is described as an example. However, the other light emitting chips C2 to C60 have the same structure as the light emitting chip C1. Note that in FIG. 12 , a portion including transfer thyristors T1 to T4 , memory thyristors M1 to M4 , and light-emitting thyristors L1 to L4 is mainly shown. the

The difference between the third exemplary embodiment and the first exemplary embodiment shown in FIG. 5 lies in newly provided canceling diodes Sd1, Sd2, Sd3, . . . as examples of canceling elements. the

The light emitting chip C1 (C) includes cancellation diodes Sd1 , Sd2 , Sd3 . . . arranged in a line on the substrate 80 . The cancellation diodes Sd1 , Sd2 , Sd3 . . . may be Schottky diodes. If the elimination diodes Sd1 , Sd2 , Sd3 . . . are not distinguished, they are called eliminator diodes Sd. the

Next, the electrical connection of the cancellation diode Sd in the light emitting chip C1(C) will be described. the

Each anode terminal of the cancellation diode Sd1, Sd2, Sd3... is connected to a corresponding one of the gate terminals Gm1, Gm2, Gm3... of the memory thyristor M1, M2, M3.... the

The cathode terminals of the cancellation diodes 1 , Sd2 , Sd3 . . . are connected to the cancellation signal line 76 . Also, the cancel signal line 76 is connected to the φe terminal which is an input terminal of the cancel signal φe. The cancel signal line 102 (see FIG. 11 ) is connected to the φe terminal, and the cancel signal φe is supplied to the φe terminal. the

Next, the operation of the light emitting section 63 in the third exemplary embodiment will be described. As shown in FIG. 11 , a signal pair of the first transfer signal φ1 and the second transfer signal φ2 and the erasure signal φe are commonly supplied to the light-emitting chips C ( C1 to C60 ) constituting the light-emitting portion 63 . Meanwhile, memory signals φm (φm1 to φm60 ) based on image data sets are individually supplied to the light emitting chips C ( C1 to C60 ). The lighting signals φI (φI1 to φ130) are respectively supplied to corresponding light-emitting chip pairs each composed of two light-emitting chips C, so that each lighting signal φI is shared by the two light-emitting chips C constituting each pair, And the lighting signal φI is individually supplied to the light-emitting chips C constituting different pairs. the

The third exemplary embodiment differs from the first exemplary embodiment only in the additionally provided cancel diode Sd. Similar to the description in the first exemplary embodiment, if the operation of the light-emitting chip C1 is described, the operation of the light-emitting portion 63 is understood. Therefore, the operation of the light emitting chip C will be described taking the light emitting chip C1 as an example. the

FIG. 13 is a timing chart illustrating the operation of the light-emitting chip C1 (C) in the third exemplary embodiment. the

Also in FIG. 13 , it is assumed that time is from time point a to time point y in alphabetical order. In FIG. 13, the first transfer signal φ1, the second transfer signal φ2, the memory signal φm1, the erasing signal φe, the lighting signal φI1, and the currents J(M1) to J( M8). the

FIG. 13 shows a lighting control period T(#A) in the case where lighting control is performed using groups each composed of 8 light-emitting thyristors L shown in FIG. 6 . Here, in the lighting control period T(#A), brightness control is performed on the light-emitting thyristors L1 to L8 in the group #A. Note that the lighting control period T(#A) is followed by a lighting control period T(#B) for brightness control of the light-emitting thyristors L9 to L16 in group #B, and brightness control for the light-emitting thyristors L17 to L24 in group #C. Lighting control period T(#C) of luminance control, . . . but description of the lighting control period T(#C) is omitted. the

Note that in the lighting control period T(#A) shown in FIG. 13 , similarly to the first exemplary embodiment, the light-emitting thyristors L1 , L2 , L3 among the eight light-emitting thyristors L1 to L8 in the group #A are , L5 and L8 light up (light), while keeping the light-emitting thyristors L4, L6 and L7 not light up (extinguish). In other words, assume that the image data set "11101001" is printed. the

In FIG. 13 , the waveforms of signals other than the cancellation signal φe are the same as those shown in FIG. 7 . Therefore, only the cancellation signal φe will be described. the

Here, the waveform of the erasure signal φe in the lighting control period T(#A) will be described. the

The potential of the erasing signal φe is "H" at the start time point c of the lighting control period T(#A), and changes from "H" to "L" at the time point v. Subsequently, at a time point w, its potential changes from "L" to "H". At the end time point y of the lighting control period T(#A), its potential is kept at "H". the

In other words, the erasing signal φe has an "L" potential once in the lighting control period T(#A). the

The operation of canceling the signal φe will be described. the

As described above, the potential of the gate terminal Gm of the memory thyristor M which is turned off after being turned on changes from 0V to -3.3V. This rate of change is determined by a time constant defined by the parasitic capacitance of the gate terminal Gm and the power supply line capacitance Rm. As described above, if the potential change of the gate terminal Gm is slow, it may be advantageous because the period t3 is set long, but it may be disadvantageous because the reset period t5 becomes longer. the

In the third exemplary embodiment, in order to control the reset period t5, an erasing signal φe that forcibly eliminates the charge accumulated in the parasitic capacitance of the gate terminal Gm and clears the memory thyristor M from the memory thyristor M is set. Connected storage information. the

Referring to FIG. 12 , operations of the light emitting portion 63 and the light emitting chip C1 (C) will be described based on the timing chart shown in FIG. 13 . the

Note that in FIG. 12 , only the part including the transfer thyristor T, the memory thyristor M, the light emitting thyristor L and the like whose numbers are all 1-4 is shown. The above part is repeated for other parts (not shown in the figure) including thyristors and the like whose numbers are not less than 5. In the following description, not only elements respectively numbered 1-4 but also elements respectively having other numbers are described. the

(initial state)

At time point a in the timing chart shown in FIG. 13 , the Vsub terminal provided on each light-emitting chip C ( C1 to C60 ) of the light-emitting portion 63 is set at the reference potential Vsub (0 V). At the same time, each Vga terminal is set at the power supply potential Vga (-3.3 V) (see FIG. 11 ). the

In addition, the transfer signal generating unit 120 of the signal generating circuit 100 sets the potentials of the first transfer signal φ1 and the second transfer signal φ2 at “H”, and the memory signal generating unit 130 sets the potentials of the memory signals φm (φm1 to φm60) to “H”. set at "H", the erasing signal generating unit 140 sets the potential of the erasing signal φe at "H", and the lighting signal generating unit 110 sets the potential of the lighting signal φI (φI1 to φI30) at "H" (see Figure 11). the

The states of the signal-causing light-emitting portion 63 and the light-emitting signal C ( C1 to C60 ) other than the cancel signal φe are the same as those described in the first exemplary embodiment. Hereinafter, the part related to the erasure signal φe will be mainly described. the

When the potential of the erasing signal φe becomes “H”, the potential of the erasing signal line 102 becomes “H”, and thus the erasing signal line 76 of each light-emitting chip C becomes "H". Since the erasure signal φe is commonly sent to the light-emitting chip C, the operation of the light-emitting chip C is understood if the operation of the light-emitting chip C1 is described. the

Hereinafter, the operation related to the erasure signal φe of the light-emitting chip C will be mainly described taking the light-emitting chip C1 as an example. The other light emitting chips C2 to C60 perform operations similar to the light emitting chip C1 in parallel with the light emitting chip C1 . the

When the potential of the erasing signal φe becomes "H", the potentials of the cathode terminals of the erasing diodes Sd1 , Sd2 , Sd3 . . . become "H" (0 V). the

On the other hand, as described in the first exemplary embodiment, the potential of the gate terminal Gm1 of the memory thyristor M1 becomes -2.6V by the forward-biased start diode Ds and connection diode Dm1. The gate terminals Gm of the memory thyristors M whose respective numbers are not less than 2 are connected to the anode terminals of the start diode Ds set at "H" (0 V) potential (for example, the gate terminal Gm2) through three or more stages of forward diodes. The anode terminal of the start diode Ds is connected via three stages of the start diode Ds, the coupling diode Dc1 and the connection diode Dm2). Therefore, the potential of these gate terminals Gm becomes the power supply potential Vga (-3.3 V). The anode terminals of the cancellation diodes Sd are connected to the gate terminals Gm, respectively. the

Therefore, all cancellation diodes Sd are reverse biased. In this way, the potential of the gate terminal Gm is not affected by the cancel signal φe. the

(operational start and operating conditions) 

The period from the time point b to the time point s in the lighting control period T(#A) is a period in which the image data set is written in the memory thyristors M1 to M8. During this period, the potential of the erasing signal φe is kept at "H". Therefore, the potential of the cathode terminal of the cancel diode Sd is set at 0 V ("H"). Meanwhile, each potential value of the gate terminal Gm connected to the anode terminal of the cancellation diode Sd is between 0V and −3.3V. When the memory thyristor M is turned on, the potential of the gate terminal Gm becomes 0V. Meanwhile, while the memory thyristor M remains in the off state without being turned on, its potential becomes -3.3V. Subsequently, the potential of the gate terminal Gm of the memory thyristor M turned off after being turned on is changed from 0V to −3.3V, and thus the value of the potential of the gate terminal Gm thereof is between 0V and −3.3V. the

Therefore, during the period from the time point b to the time point s, the cancellation diode Sd is at least not forward biased. Thus, the potential of the gate terminal Gm is not affected by the erasing signal φe. the

Therefore, the operation of the lighting chip C1 (C) in the period from the time point b to the time point s is the same as that in the first exemplary embodiment. the

At a time point t, similarly to the first exemplary embodiment, by changing the potential of the lighting signal φI1 (φI) from “H” to “Le”, the light-emitting thyristors L1, L2, L3, L5, and L8 are turned on. And light up (glow). Also in this state, the cancellation diode Sd is at least not forward biased. Thus, the potential of the gate terminal Gm is not affected by the cancel signal φe. the

Subsequently, at a time point u, the potential of the memory signal φm1 (φm) changes from “S” to “H”. Accordingly, the memory thyristors M1 , M2 , M3 , M5 , and M8 in the on state are turned off, and the potentials of the gate terminals Gm1 , Gm2 , Gm3 , Gm5 , and Gm8 start to change from 0V to −3.3V. At the same time, the potentials of the gate terminals Gm4 , Gm6 , and Gm7 of the memory thyristors M4 , M6 , and M7 kept in the off state are kept at 3.3 V by the power supply potential Vga. the

As described above, in the third exemplary embodiment in which "S" is set at -2.5V and "L" is set at -3.3V, in order for the stored information of the memory thyristor M which the memory thyristor M has turned on Resetting requires making the potential of the gate terminal Gm smaller than -2V. the

At the time point v, the potential of the erasing signal φe changes from "H" (0 V) to "L" (-3.3 V). Therefore, the potential of the cathode terminal of the cancellation diode Sd becomes -3.3V. Meanwhile, the anode terminals of the cancel diodes Sd are connected to the gate terminals Gm of the above-mentioned memory thyristors M, respectively. The potential of the gate terminal Gm of the memory thyristors M1 , M2 , M3 , M5 , and M8 , which have been turned off after being turned on, starts to change from 0 V to −3.3 V at the time point u. Thus, the cancellation diodes Sd1, Sd2, Sd3, Sd5 and Sd8 are forward biased. Therefore, the potentials of the gate terminals Gm1, Gm2, Gm3, Gm5, and Gm8 become values (-2.5V) obtained by subtracting the forward potential of the cancellation diode Sd from -3.3V ("L") Vs (0.8V) and get. In other words, by changing the potential of the cancel signal φe from "H" to "L", the potential of the gate terminal Gm of the memory thyristor M that has been turned on is forcibly set at -2.5V, and the gate terminal Gm1, Potential changes of Gm2, Gm3, Gm5 and Gm8. the

Since the forward potential Vs (0.8V) of the Schottky diode using the Al electrode is smaller than the diffusion potential Vd (1.3V) of the p-n junction, the potential of the gate terminal Gm of the memory thyristor M that has been turned on can be set at a lower low potential. Note that, in addition to Al, Au, Pt, Ti, Mo, W, WSi, TaSi, or the like can also be used as the electrode of the Schottky diode. the

Note that the potentials of the gate terminals Gm4, Gm6, and Gm7 of the memory thyristors M4, M6, and M7 do not change from -3.3V. the

At the time point v, the potential of the second transfer signal φ2 is changed from “L” to “H”, and the transfer thyristor T8 is turned off. If the transfer thyristor T8 is in the on state, the potential of the gate terminal Gt8 is 0V. In addition, the gate terminal Gm8 connected to the gate terminal Gt8 through the connection diode Dm8 is -1.3V. However, when the transfer thyristor T8 is turned off, the potential of the gate terminal Gt8 changes from 0V to -3.3V. the

At the time point v, the potential change of the cancel signal φe from “H” to “L” and the potential change of the second transfer signal φ2 from “L” to “H” are performed simultaneously. If the potential change of the cancel signal φe from “H” to “L” is performed before the potential change of the second transfer signal φ2 from “L” to “H”, the gate terminal is connected by the forward biased connection diode Dm8 The potential of Gm was fixed at -1.3V. Thus, the effect of the cancellation diode Sd8 to set the potential of the gate terminal Gm8 at a lower value (-2.5V) is lost. Therefore, the potential change of the second transfer signal φ2 from “L” to “H” can be performed before the potential change of the cancel signal φe from “H” to “L”. the

At the time point w, the potential of the erasing signal φe changes from "L" to "H". Therefore, the potential of the cathode terminal becomes 0 V, and the potential of the anode terminal (gate terminal Gm) becomes −2.5 V, and thereby the cancellation diode Sd is reverse biased. Therefore, the potential of the gate terminal Gm is not affected by the cancel signal φe, and becomes the power supply potential Vga (−3.3 V), and the gate terminal Gm is connected to the power supply potential Vga through each power supply line resistance Rm. the

As described above, by eliminating the signal φe (by changing its potential from “H” to “L”), the potential of the gate terminal Gm of the memory thyristor M which has been turned off after being turned on is forcibly set at such a value : This value is obtained by subtracting the forward potential Vs of the cancellation diode Sd from "L" (-3.3V), and thus the memory of the memory thyristor M whose memory thyristor M has been turned on is forced to be reset, and reset The period t5 becomes shorter. Therefore, the reset period t5 can be set independently of the time constant defined by the parasitic capacitance of the gate terminal Gm and the power supply line resistance Rm. Therefore, the period t3 and the reset period t5 can be set independently. the

Note that in the third exemplary embodiment, a Schottky diode is used as the snubber Sd. the

The thyristors (light-emitting thyristor L, transfer thyristor T, memory thyristor M) used in the third exemplary embodiment may each be constituted by a pnpn structure in which a first p-type semiconductor layer, a second n-type semiconductor layer, third p-type semiconductor layer, and fourth n-type semiconductor layer, but detailed description thereof is omitted here. In this case, the p-n junction between the fourth n-type semiconductor layer as the topmost layer and the next third p-type semiconductor layer can function as a diode. However, below the diode there is a second n-type semiconductor layer and a first p-type semiconductor layer. With this structure, if it is desired to use the p-n junction between the fourth n-type semiconductor layer and the third p-type semiconductor layer as a diode, it is possible to make a junction consisting of the first p-type semiconductor layer, the second n-type semiconductor layer, The thyristor (parasitic thyristor) of the pnpn structure constituted by the third p-type semiconductor layer and the fourth n-type semiconductor layer is turned on (locked). the

Alternatively, if a Schottky diode is configured by removing the fourth n-type semiconductor layer that is the topmost layer and providing a material that makes a Schottky contact with the surface-exposed third p-type semiconductor layer, the pnpn is no longer formed. structure. Thus, it is possible to suppress the turn-on (lock-up) of the parasitic thyristor. the

<Fourth Exemplary Embodiment>

14 is a schematic diagram showing the structure of the signal generating circuit 100 in the light emitting device 65 in the fourth exemplary embodiment and the wiring structure between the signal generating circuit 100 and each light emitting chip C ( C1 to C60 ). the

The difference between the fourth exemplary embodiment and the first exemplary embodiment shown in FIG. 4 lies in a hold signal generating unit 150 newly provided in the fourth exemplary embodiment. The hold signal generation unit 150 is used in the signal generation circuit 100 to send a hold signal φb for temporarily holding the position (number) of the light emitting thyristor L for lighting to the light emitting chips C ( C1 to C60 ). the

Thus, the hold signal line 103 is newly provided on the circuit board 62 in addition to the structure in the first exemplary embodiment shown in FIG. 4 . Here, the hold signal line 103 transmits the hold signal φb from the hold signal generating unit 150 of the signal generating circuit 100 to the light emitting portion 63 . The holding signal line 103 is connected in parallel to φb terminals of the light emitting chips C ( C1 to C60 ) (see FIG. 15 described later). the

Other structures are the same as those of the first exemplary embodiment shown in FIG. 4 . Thus, in the fourth exemplary embodiment, the same reference numerals are given to the same components as those in the first exemplary embodiment, and detailed description thereof is omitted. the

In the first exemplary embodiment, by turning on the plurality of memory thyristors M corresponding to the plurality of light-emitting thyristors L to be sequentially lit according to the image data set, the position (No. ) for storage. Subsequently, after all the memory thyristors M corresponding to the light-emitting thyristor L to cause lighting are set in the on state, the lighting signal φI is supplied to the light-emitting thyristor L, and the light-emitting thyristor L is turned on to light (emit light ). For example, as shown in FIG. 7, in the period from time point c to time point s in the lighting control period T(#A), the image data set is written into the memory thyristor M, and in the period from time point t to time point During the light-emitting period t4 of x, the light-emitting thyristor L is set in a lighted (conducting) state. the

However, in the first exemplary embodiment, the image data set corresponding to the lighting control period T(#B) cannot be written in the memory thyristor M until the light emitting period t4 of the light emitting thyristor L ends. the

In the fourth exemplary embodiment, in the light emitting period t4 of the light-emitting thyristors L in one group, writing to the next group can also be performed. Therefore, it is possible to increase the light emission duty ratio, which is the ratio of the light emission period per unit time. the

FIG. 15 is a schematic diagram illustrating a circuit configuration of a light-emitting chip C as a self-scanning light-emitting element array (SLED) chip in the fourth exemplary embodiment. Note that description is made here by taking the light-emitting chip C1 as an example. However, the other light emitting chips C2 to C60 have the same structure as the light emitting chip C1. the

In addition to the structure of the light emitting chip C1 in the first exemplary embodiment shown in FIG. 5 , the light emitting chip C1 in the fourth exemplary embodiment includes holding thyristors as an example of holding elements arranged in a line on the substrate 80 . A holding thyristor array (holding element array) composed of B1, B2, B3.... In addition to the structure of the light-emitting chip C1 in the first exemplary embodiment, the light-emitting chip C1 includes connection diodes Db1, Db2, Db3, . . . Also, the light emitting chip C1 includes power supply line resistors Rb1 , Rb2 , Rb3 . . . and resistors Rc1 , Rc2 , Rc3 . . . in addition to the structure of the light emitting chip C1 in the first exemplary embodiment. the

Here, similar to the first exemplary embodiment, if the holding thyristors B1 , B2 , B3 . . . are not distinguished, they are referred to as holding thyristors B. Likewise, connection diodes Db1, Db2, Db3..., power line resistances Rb1, Rb2, Rb3..., and resistances Rc1, Rc2, Rc3... are called connection diodes Db, power line resistance Rb, and resistance Rc, respectively, if they are not distinguished separately . the

Note that holding thyristor B is a semiconductor element as follows: each semiconductor element has three terminals, namely an anode terminal (anode), a cathode terminal (cathode) and a gate terminal (gate), similar to transfer thyristor T, memory thyristor M and the three terminals in the light-emitting thyristor L. the

If it is assumed that the number of transfer thyristors T is set to 128, similar to the number of light-emitting chips C1 in the first exemplary embodiment, each of the number of thyristors B, the number of power supply line resistors Rb, and the number of resistors Rc is maintained Both are set to 128. the

Similar to the transfer thyristors T1 , T2 , T3 . . . in the first exemplary embodiment, the holding thyristors B1 , B2 , B3 . Similarly, connecting diodes Db1, Db2, Db3..., power supply line resistors Rb1, Rb2, Rb3... and resistors Rc1, Rc2, Rc3... are arranged in numerical order from the left in FIG. 15, respectively. the

Other structures are the same as those in the first exemplary embodiment shown in FIG. 5 . Thus, in the fourth exemplary embodiment, the same reference numerals are given to the same components as those in the first exemplary embodiment, and detailed descriptions thereof are omitted. the

Next, electrical connections between elements of the light-emitting chip C1 will be described. the

As described above, the light-emitting chip C1 in the fourth exemplary embodiment has a structure in which the holding thyristor B, the connection diode Db, the power supply line resistance Rb, and the resistance Rc are additionally provided. Thus, electrical connections of newly added elements are mainly described. the

Similar to the anode terminals of the transfer thyristors T1 , T2 , T3 . . . , the anode terminals of the holding thyristors B1 , B2 , B3 are connected to the substrate 80 of the light emitting chip C1 . These anode terminals are connected to the power supply line 104 (see FIG. 14 ) through the Vsub terminal provided on the substrate 80 . A reference potential Vsub is supplied to this power supply line 104 . Gate terminals Gb1 , Gb2 , Gb3 . . . of holding thyristors B1 , B2 , B3 . the

Here, if the gate terminals Gb1 , Gb2 , Gb3 . . . are not distinguished, they are referred to as gate terminal Gb. the

The cathode terminals of the holding thyristors B1 , B2 , B3 . . . are connected to the holding signal line 77 through resistors Rc1 , Rc2 , Rc3 . The hold signal line 77 is connected to a φb terminal which is an input terminal of a hold signal φb. A hold signal line 103 (see FIG. 14 ) is connected to the φb terminal, and a hold signal φb is supplied to the φb terminal. the

In the light emitting chip C1 in the first exemplary embodiment shown in FIG. 5 , the gate terminal Gm of the memory thyristor M and the gate terminal G1 of the light emitting thyristor L are directly connected to each other. In the fourth exemplary embodiment, unlike the above structure, the gate terminals Gb1, Gb2, Gb3... of the thyristors B1, B2, B3... are kept connected one by one through the respective connection diodes Db1, Db2, Db3. Respective gate terminals Gm1 , Gm2 , Gm3 . . . of the memory thyristors M1 , M2 , M3 . . . keep the thyristor B the same. In other words, the cathode terminals of the connection diodes Db1, Db2, Db3... are connected to the respective gate terminals Gb1, Gb2, Gb3... of the holding thyristors B1, B2, B3..., while the anode terminals of the connection diodes Db1, Db2, Db3... are connected to the memory The respective gate terminals Gm1, Gm2, Gm3... of the thyristors M1, M2, M3... are. In addition, the connection diodes Db are connected along the direction of current flow from the respective gate terminals Gm of the memory thyristors M to the respective gate terminals Gb of the holding thyristors B. As shown in FIG. the

The connection diode Db is connected to each gate terminal Gb of the holding thyristor B and each gate terminal G1 of the light emitting thyristor L. the

Next, the operation of the light emitting section 63 in the fourth exemplary embodiment will be described. As shown in FIG. 14 , a signal pair of the first transfer signal φ1 and the second transfer signal φ2 and the hold signal φb are commonly supplied to the light-emitting chips C ( C1 to C60 ) constituting the light-emitting portion 63 . Meanwhile, memory signals φm (φm1 to φm60 ) based on image data sets are individually supplied to the light emitting chips C ( C1 to C60 ). The lighting signals φI (φI1 to φI30) are respectively supplied to corresponding light-emitting chip pairs each composed of two light-emitting chips C, so that each lighting signal φI is shared by the two light-emitting chips C constituting each pair, And are individually supplied to the light-emitting chips C constituting different pairs. the

The fourth exemplary embodiment differs from the first exemplary embodiment only in that a holding thyristor B is additionally provided. Similar to the description in the first exemplary embodiment, if the operation of the light-emitting chip C1 is described, the operation of the light-emitting portion 63 is understood. Therefore, the operation of the light-emitting chip C is described by taking the light-emitting chip C1 as an example. the

FIG. 16 is a timing chart illustrating the operation of the light-emitting chip C1 (C) in the fourth exemplary embodiment. In FIG. 16 , it is assumed that the time is from time point a to time point ac (time point a to time point z in alphabetical order, followed by time points aa, ab, and ac). In FIG. 16, the first transfer signal φ1, the second transfer signal φ2, the memory signal φm1, the hold signal φb, the lighting signal φI1, and the currents J(M1) to J(M8) flowing into the respective memory thyristors M1 to M8 are shown. ) waveform. the

FIG. 16 shows a lighting control period T(#A) (from time point c to time point y) in the case where lighting control is performed using groups each composed of 8 light-emitting thyristors L shown in FIG. 6 And a part of the lighting control period T(#B) (from the time point y and subsequent periods). Here, in the lighting control period T(#A), brightness control is performed on the light-emitting thyristors L1 to L8 in the group #A, and in the lighting control period T(#B), the light-emitting thyristor L9 in the group #B is controlled. Go to L16 for brightness control. Note that the lighting control period T(#B) is followed by a lighting control period T(#C) of performing brightness control on the light-emitting thyristors L17 to L24 in the group #C, etc., but description thereof is omitted. the

In the case of comparing FIG. 16 and FIG. 7 with each other, it can be recognized that the lighting control period T(#A) (from time point c to time point y) in the fourth exemplary embodiment is shorter than that in the first exemplary embodiment. The lighting control period T(#A) should be short. In other words, the lighting control period T(#B) starts at the time point y before the time point aa when the light emitting period t4 of the light emitting thyristors L1 to L8 in the group #A ends. the

Note that in the lighting control period T(#A) shown in FIG. 16 , it is assumed that the light-emitting thyristor L1 of the eight light-emitting thyristors L1 to L8 in the group #A is caused to light up similarly to the case in the first exemplary embodiment. , L2, L3, L5, and L8 light up (light up), while the light-emitting thyristors L4, L6, and L7 remain unlighted (off). Also, as an example, assume that the light-emitting thyristors L9 , L11 , and L12 are caused to light up (emit light) in the lighting control period T(#B) while the light-emitting thyristor L10 remains off. In other words, assume that the image data set "11101001" is printed in the lighting control period T(#A) and the image data set "1011..." is printed in the lighting control period T(#B). the

Portions in waveforms of respective signals that are different from those in the first exemplary embodiment will be described. the

The waveforms in the period from the time point a to the time point s are the same as those shown in FIG. 7 in the first exemplary embodiment, except for the hold signal φb. the

The potential of the hold signal φb added in the fourth exemplary embodiment is “H” at the start time point c of the lighting control period T(#A), and changes from “H” to “L” at the time point t. ". Subsequently, its potential changes from "L" to "H" at a time point v. Its potential is kept at "H" at the end time point y of the lighting control period T(#A). the

The potential of the lighting signal φI1 is "H" at the start time point c of the lighting control period T(#A), and changes from "H" to "H" at the time point u of the lighting control period T(#A). Le", and further changes from "Le" to "H" at the time point aa of the lighting control period T(#B). the

In the first exemplary embodiment, the light-emitting period t4 of the light-emitting thyristors L in each group is included in the lighting control period (for example, the lighting control period T(#A)). However, in the fourth exemplary embodiment, the light-emitting period t4 (from time point u to time point aa) of the light-emitting thyristor L is included in the lighting control periods for two groups (for example, T(#A) and T( #B)). the

In addition to the above points, the waveforms of the first transfer signal φ1, the second transfer signal φ2, the memory signal φm1(φm), and the currents J(M1) to J(M8) flowing in the memory thyristor M are the same as those of the first exemplary embodiment. The waveforms in are the same, and thus their detailed descriptions are omitted. the

Referring to FIG. 15 , operations of the light emitting portion 63 and the light emitting chip C will be described based on the timing chart shown in FIG. 16 . The operation of the light-emitting chip C is similar to that of the light-emitting chip C in the first exemplary embodiment except for the part related to the holding thyristor B newly provided in the fourth exemplary embodiment. Thus, the operation of the light-emitting chip C related to the newly provided holding thyristor B will be mainly described, and the description of the operation similar to that in the first exemplary embodiment will be omitted. (initial state)

At time point a in the timing chart shown in FIG. 16 , the Vsub terminal provided on each light-emitting chip C ( C1 to C60 ) of the light-emitting portion 63 is set at the reference potential Vsub (0 V). At the same time, each Vga terminal is set at the power supply potential Vga (-3.3 V) (see FIG. 14 ). the

In addition, the first transfer signal φ1, the second transfer signal φ2, the memory signal φm (φm1 to φm60), and the hold signal φb are set at “H”, and the potential of the lighting signal φI (φI1 to φI30) is set at "H". Therefore, the potential of the hold signal line 103 added in the fourth exemplary embodiment becomes "H", and the potential of the hold signal line 77 of each light-emitting chip C becomes "H" through the φb terminal of each light-emitting chip C ". the

Similar to other thyristors (transfer thyristor T, memory thyristor M, and light emitting thyristor L), the anode terminal of holding thyristor B is connected to the Vusb terminal and supplied with "H" (0V). Meanwhile, the cathode terminal of the holding thyristor B is connected to the holding signal line 77 having the potential set at "H". Therefore, both the potentials of the anode terminal and the cathode terminal of the thyristor B are kept becoming "H", and thus the thyristor B is kept in an off state. the

Since other thyristors (transfer thyristor T, memory thyristor M, and light-emitting thyristor L) are the same as those in the first exemplary embodiment, all thyristors (transfer thyristor T, memory thyristor M, holding thyristor B, and light-emitting thyristor L) are at off state. the

Since the start diode Ds is the same as that in the first exemplary embodiment, the potential of the gate terminal Gt1 becomes −1.3 V by the start diode Ds. Therefore, the threshold voltage of the transfer thyristor T1 is -2.6V. the

The potential of the gate terminal Gt2 of the transfer thyristor T2 and the potential of the gate terminal Gm1 of the memory thyristor M1 are -2.6V. However, since the gate terminal Gb1 of the thyristor B1 is kept connected to the gate terminal Gt1 at a potential of -1.3 V through two stages of forward-biased diodes (connection diode Dm1 and connection diode Db1 ), the gate terminal Gb1 is not subjected to the potential Influence of -1.3V on the gate terminal Gt1. Thus, the potential of the gate terminal Gb1 becomes the power supply potential Vga (−3.3 V). The potential of the other gate terminal Gb of the holding thyristor B also becomes the power supply potential Vga (-3.3V). Therefore, the threshold voltage of thyristor B is maintained at -4.6V. (operating status)

Similar to the case in the first exemplary embodiment, when the potential of the first transfer thyristor φ1 changes from “H” (0 V) to “L” (−3.3 V) at time point b, the transfer thyristor T1 comes into conduction state. the

Operations related to the memory thyristor M from time point c to time point s are the same as those in the first exemplary embodiment. Note that it is assumed that the period from time point c to time point s in FIG. 16 is equal to the period from time point c to time point s in FIG. 7 . the

The operation of holding thyristor B from time point c to time point s will be described. the

When the memory thyristor M1 is turned on at the start time point c of the writing period T(M1), the potential of the gate terminal Gm1 becomes "H" (0 V), and thus the conduction current Jo flows into the memory thyristor M1, This is shown in current J(M1). The gate terminal Gb1 of the holding thyristor B1 is connected to the gate terminal Gm1 through a forward biased connection diode Db1 . Thus, the potential of the gate terminal Gb1 of the holding thyristor B1 becomes -1.3V, and the threshold voltage of the holding thyristor B1 becomes -2.6V. In addition, since the gate terminal Gb1 is also connected to the gate terminal Gl1 of the light-emitting thyristor L1, the threshold voltage of the light-emitting thyristor L1 also becomes -2.6V. the

However, since the potential of the hold signal φb is “H” (0 V) at the time point c, the hold thyristor B1 is not turned on. In addition, since the potential of the lighting signal φI1 (φI) is also “H” (0 V), the light-emitting thyristor L1 is also not turned on, and thus does not light up (emit light). the

Note that since the gate terminal Gb2 of the holding thyristor B2 is connected to the gate terminal Gt1 of potential "H" (0 V) through three stages of forward-biased diodes (coupling diode Dc1, connection diode Dm2, and connection diode Db2), The gate terminal Gt1 at potential "H" (0 V) does not affect the gate terminal Gb2, and thus the gate terminal Gb2 is kept at the power supply potential Vga (−3.3 V). Therefore, the threshold voltage of thyristor B2 is maintained at -4.6V. The holding thyristors B each numbered not less than 3 are the same as above. In addition, the light-emitting thyristors L whose respective numbers are not less than 2 are the same as above. the

When the potential of the memory signal φm1 (φm) changes from “L” to “H” at time point d, the memory thyristor M1 is turned off. The potential of the gate terminal Gm1 starts to change from 0V to -3.3V. With this change, the potential of the gate terminal Gb1 of the holding thyristor B1 starts to change from -1.3V to -3.3V. The gate terminal Gl1 of the light emitting thyristor L1 is the same as above because the gate terminal Gl1 of the light emitting thyristor L1 is connected to the gate terminal Gb1. Since the hold signal φb is held at the potential "H" (0 V), the hold thyristor B1 is not turned on. Also, since the lighting signal φI1 (φI) is kept at the potential “H” (0 V), the light-emitting thyristor L1 is not turned on and thus does not light up (emit light). the

In the subsequent writing periods T(M2) to T(M7), the memory thyristors M1, M2, M3, and M5 are alternately turned on and off as described in the first exemplary embodiment. In response thereto, the potentials of the gate terminals Gb of the thyristors B1 to B7 (the gate terminals G1 of the light-emitting thyristors L1 to L7 ) are kept varied between -1.3V and -3.3V. Thus, the threshold voltages of the thyristors B1 to B7 (light-emitting thyristors L1 to L7 ) are kept varied between -2.6V and -4.6V. In the writing period T( M1 ) to T( M7 ), since the potential of the hold signal φb is “H” (0 V), the thyristors B1 to B7 are not turned on. In addition, since the potential of the lighting signal φI1 (φI) is also “H” (0 V), the light-emitting thyristors L1 to L7 are not turned on, and thus do not light up (emit light). the

Similar to the case in the first exemplary embodiment, when the potential of the memory signal φm1 (φm) changes from “H” to “L” at the time point r, the memory thyristors M1, M2, M3, M5, and M8 are turned on . the

Even if the memory signal φm1 (φm) changes from “L” to “S” at the time point s, the memory thyristors M1 , M2 , M3 , M5 , and M8 maintain the on state. the

Since the potential of the gate terminal Gm of the memory thyristor M that has been turned on becomes 0 V, the gate terminal Gb of the thyristor B that is connected to this gate terminal Gm through one stage of forward biased diode (connection diode Db) holds The potential becomes -1.3V. Therefore, the threshold voltage of the holding thyristor B becomes -2.6V. In other words, immediately after the time point s, the threshold voltages of the thyristors B1 , B2 , B3 , B5 and B8 are kept at -2.6V. At the same time, keep the threshold voltage of thyristors B4, B6 and B7 at -4.6V. In addition, the threshold voltage of each holding thyristor B whose number is not less than 9 is -4.6V. the

At a time point t, the potential of the hold signal φb changes from "H" (0 V) to "L" (−3.3 V). Thus, the holding thyristors B1 , B2 , B3 , B5 and B8 with a threshold voltage of -2.6V are turned on. The other keeps thyristor B off. the

In other words, by turning on the holding thyristor B having the same number as the memory thyristor M in the on-state, the information on the number (position) of the light-emitting thyristor L that caused the lighting is copied to the holding thyristor B, which is determined by The memory thyristor M performs storage. the

Note that the holding thyristors B are connected to the holding signal line 77 through the respective resistors Rc. Even if a holding thyristor B comes into conduction state and the potential of the cathode terminal of the holding thyristor B becomes value, the signal line 77 is kept at the potential "L". Thus, a plurality of holding thyristors B (here, holding thyristors B1 , B2 , B3 , B5 and B8 ) are ready to be turned on simultaneously. the

When the thyristors B1 , B2 , B3 , B5 , and B8 are kept turned on, the potentials of the gate terminals Gb1 , Gb2 , Gb3 , Gb5 , and Gb8 become 0 V as the anode terminal potential. The threshold voltage of the light-emitting thyristors L1, L2, L3, L5, and L8 having the respective gate terminals Gl1, Gl2, Gl3, Gl5, and G18 connected to the respective gate terminals Gb1, Gb2, Gb3, Gb5, and Gb8 becomes -1.3V . At the same time, the potentials of the gate terminals Gb4, Gb6 and Gb7 of the holding thyristors B4, B6 and B7 which are not turned on are kept at -3.3V. Therefore, the threshold voltage of thyristors B4, B6 and B7 is maintained at -4.6V. The threshold voltage of each holding thyristor B whose number is not less than 9 is -4.6V. the

Therefore, the transfer thyristor T8, the memory thyristors M1, M2, M3, M5, and M8, and the holding thyristors B1, B2, B3, B5, and B8 are kept in the on state. the

When the potential of the lighting signal φI1 (φI) changes from “H” to “Le” (-2.6V<“Le”≤-1.3V) at the time point u, the light-emitting thyristors L1, L2, L3, L5, and L8 Switch on and light up (glow). the

Note that the light-emitting thyristor L is not connected to the lighting signal line 75 through a resistor. However, since the lighting signal φI1 (φI) is driven by current, the plurality of light-emitting thyristors L1, L2, L3, L5, and L8 are ready to be turned on without resistance. the

Also, at a time point u, the potential of the memory signal φm1 (φm) changes from “S” to “H”. Therefore, the memory thyristors M1, M2, M3, M5 and M8 are turned off. Subsequently, the potential of the gate terminals Gm1, Gm2, Gm3, Gm5, and Gm8 gradually changes from 0V to -3.3V. Note that the potentials of the gate terminals Gm4, Gm6, and Gm7 are kept at -3.3V. the

When the potentials of the gate terminals Gm1, Gm2, Gm3, Gm5, and Gm8 become smaller than 2 V (<−2 V), as described above, even if the potential of the memory signal φm1 (φm) is set at “L”, the memory thyristor M1 , M2, M3, M5 and M8 are not connected either. In other words, the stored information of the memory thyristors M1 , M2 , M3 , M5 and M8 that have been turned on, that is, the stored information of the position (number) of the light-emitting thyristor L is lost. the

In the fourth exemplary embodiment, at a time point t before a time point u, the positions (numbers) of the light-emitting thyristors L that keep the thyristors B1, B2, B3, B5, and B8 turned on and thus cause lighting are Sent (copied) to holding thyristor B. Therefore, there is no problem if the information on the position (number) of the light-emitting thyristor L that caused lighting is lost from the memory thyristor M at the point of time u and subsequent periods. the

Also, at the time point u, the potential of the first transfer signal φ1 is changed from "H" to "L". Therefore, the transfer thyristor T9 whose threshold voltage is -2.6V is turned on. Subsequently, the gate terminal Gt9 of the transfer thyristor T9 becomes 0V. In addition, the potential of the gate terminal Gt10 of the transfer thyristor T10 becomes -1.3V, and the threshold voltage of the transfer thyristor T10 becomes -2.6V. Similarly, the threshold voltage of the memory thyristor M9 becomes -2.6V. the

Note that in the fourth exemplary embodiment, at the time point u, the potential change of the lighting signal φI1 (φI) from “H” to “Le”, the memory signal φm1 (φm) from “S” to “H” The potential change of , and the potential change of the first transfer signal φ1 from “H” to “L” are performed simultaneously. These changes can be performed in any order. the

Specifically, if the potential change of the first transfer signal φ1 from “H” to “L” is performed first, the transfer thyristor T9 is turned on and the threshold voltage of the memory thyristor M9 becomes -2.6V. Even in this case, since the memory signal φm1 (φm) is “S” (−2.5V), the memory thyristor M9 is not turned on. In addition, although the threshold voltage of the holding thyristor B9 is -3.9V, since the potential of the holding signal φb is "L" (-3.3V), the holding thyristor B9 is not turned on. the

Alternatively, if the potential change of the first transfer signal φ1 from “H” to “L” is performed after the potential change of the memory signal φm1 (φm) from “S” to “H” is first performed, the transfer thyristor T9 is turned on , and the threshold voltage of the memory thyristor M9 becomes -2.6V. However, since the potential of the memory signal φm1 (φm) becomes “H” (0 V), the memory thyristor M9 is not turned on. Although the threshold voltage of the holding thyristor B9 is -3.9V, since the potential of the holding signal φb is -3.3V, the holding thyristor B9 is not turned on. the

Alternatively, if the potential change of the first transfer signal φ1 from “H” to “L” is performed first, the transfer thyristor T9 is turned on. As a result, the threshold voltage of the memory thyristor M9 becomes -2.6V, and the threshold voltage of the light-emitting thyristor L9 becomes -3.9V. Thereafter, even if the potential of the lighting signal φI1 (φI) changes from “H” to “Le”, the light-emitting thyristor L9 is not turned on. In addition, since the potential of the memory signal φm1 (φm) is “S” (−2.5 V), the memory thyristor M9 is not turned on. the

As mentioned above, the sequence of the above three changes is not limited. the

Immediately after the time point u, the transfer thyristors T8 and T9 and the holding thyristors B1, B2, B3, B5, and B8 are kept in the on state, and the light-emitting thyristors L1, L2, L3, L5, and L8 are kept in the lighted (conducting) state. state. the

Next, when the potential of the second transfer signal φ2 is changed from “L” to “H” at the time point v, the transfer thyristor T8 is turned off. the

Immediately after the time point v, the transfer thyristor T9 and the holding thyristors B1, B2, B3, B5, and B8 are kept in the on state, and the light-emitting thyristors L1, L2, L3, L5, and L8 are kept in the lighting (on) state. the

At the time point v, the potential of the hold signal φb is changed from "L" to "H". Therefore, the potentials of the respective cathode terminals and anode terminals of the thyristors B1, B2, B3, B5 and B8 are kept at "H", thereby keeping the thyristors B1, B2, B3, B5 and B8 no longer in the conducting state, and turning off broken. the

Therefore, the stored information of the position (number) that caused the light-emitting thyristor L to light is lost from the holding thyristor B. However, at the time point u before the time point v, the light-emitting thyristor L to be caused to be turned on has already been caused to be turned on, and if the stored information of the position (number) at which the light-emitting thyristor L was caused to be turned on is lost from the holding thyristor B no problem. the

Immediately after the time point v, the transfer thyristor T9 is kept in the on state, and the light-emitting thyristors L1, L2, L3, L5, and L8 are kept in the lighted (on) state. the

Subsequently, the lighting control period T(#B) for the light-emitting thyristors L9 to L16 in the group #B starts from the time point y. the

At the start time point y of the writing period T( M9 ), the potential of the memory signal φm1 (φm) is changed from “H” to “L” to write stored information causing the light-emitting thyristor L9 to light. Therefore, the memory thyristor M9 whose threshold voltage is -2.6V is turned on. the

At this time, the memory thyristors M1 , M2 , M3 , M5 , and M8 that have been turned on in the lighting control period T(#A) are no longer allowed to be turned on. Therefore, at time point y, it is necessary to make the threshold voltages of these memory thyristors M1, M2, M3, M5 and M8 smaller than "L" "-3.3V" (<-3.3V), that is, the gate terminals Gm1, Gm2, The potentials of Gm3, Gm5 and Gm8 are less than -2V (<-2V). The potential changes of the gate terminals Gm1, Gm2, Gm3, Gm5, and Gm8 are determined by a time constant defined by the parasitic capacitance of the gate terminal Gm and the power supply line resistance Rm. Thus, the reset period t5 from the time point u to the time point y is set long enough so as to satisfy the above requirement. the

Therefore, immediately after the time point y, the transfer thyristor T9 and the memory thyristor M9 are kept in the ON state, the light-emitting thyristors L1, L2, L3 that have been lit at the time point u in the lighting control period T(#A) , L5 and L8 remain on (conducting) state. the

At time point z, in order to prevent the light-emitting thyristor L10 from lighting up, the potential of the memory signal φm1 (φm) changes from “H” to “S”. the

Immediately after the time point z, the transfer thyristor T10 and the memory thyristor M9 are kept in the on state, and the light-emitting thyristors L1, L2, L3, L5, and L8 are kept in the lighted (on) state. the

At time point aa, the potential of the lighting signal φI1 (φI) changes from “Le” to “H”. Therefore, the potentials of the respective cathode terminals and anode terminals of the light-emitting thyristors L1, L2, L3, L5, and L8 that have been in the lighting (conducting) state are "H", whereby they are not kept in the conducting state, and are turned off. thereby extinguished. the

Immediately after the time point aa, the transfer thyristor T10 and the memory thyristor M9 are kept in the on state. the

In other words, the light-emitting thyristors L1, L2, L3, L5, and L8 stored to cause lighting in the lighting control period T(#A) are lighted (lighted) in the light-emitting period t4 from included in Time point u in the lighting control period T(#A) to time point aa included in the lighting control period T(#B). the

Note that the end time point of the light emitting period t4 for the light emitting thyristors L1 , L2 , L3 , L5 , and L8 does not have to be the time point aa included in the writing period T( M10 ). In other words, it is only necessary that the end time point of the light emission period t4 be a time point before the time point when the light-emitting thyristors L9 , L11 . . . to cause lighting in the lighting control period T(#B) start lighting. the

At time point ab, the potential of the memory signal φm1 (φm) changes from “H” to “L” to store information that causes the light-emitting thyristor L11 to light. the

Immediately after the time point ab, the transfer thyristor T11 and the memory thyristors M9 and M11 are kept in a conductive state. the

At time point ab and subsequent periods, the waveform of the image data set-based memory signal φm1 (φm) is different from that in the preceding period. However, since it is similar to the time point k in the lighting control period T(#A) and subsequent periods, a detailed description thereof is omitted. the

As described above, in the fourth exemplary embodiment, lighting (emission of light) of the light-emitting thyristor L and writing to the memory thyristor M storing the position (number) of the light-emitting thyristor L causing lighting are performed simultaneously. Therefore, lighting (emission of light) of the light-emitting thyristor L can be performed at a high light-emitting duty ratio compared to the case of the first exemplary embodiment. the

Thus, the writing time to the photosensitive drum 12 by the print head 14 becomes shorter. the

This is due to the fact that by setting the holding thyristor B, the position (number) of the light-emitting thyristor L that caused the light-up stored in the memory thyristor M is sent to the holding thyristor B, deleted (cleared) from the memory thyristor M The storage information of the position (number) of the light-emitting thyristor L that caused lighting, and the position (number) of the light-emitting thyristor L that caused lighting next time is stored in the memory thyristor M. the

In other words, this is due to the fact that by disposing the holding thyristor B between the light-emitting thyristor L and the memory thyristor M, the state change of the memory thyristor M is prevented from affecting the light-emitting thyristor L, and the connection between the memory thyristor M and the light-emitting thyristor L is cut off. electrical relationship. the

Note that in FIG. 16, the image data set in the lighting control period T(#A) is set to "11101001", and the image data set in the lighting control period T(#B) is set to "11101001" 101...". Similar to the case in the first exemplary embodiment, only the potential of the memory signal φm is set at "L" when causing the light-emitting thyristor L to light up, and only the memory is required when the light-emitting thyristor L is not caused to light up. The potential of the signal φm is set at "S". the

Therefore, a plurality of light-emitting points (light-emitting thyristors L) are ready to light up simultaneously in one light-emitting period t4. Therefore, the light-emitting period t4 of each light-emitting chip C is allowed to be shortened compared with the case where the luminance is controlled one by one for the light-emitting points (light-emitting thyristors L). From the viewpoint of the print head 14, the writing time to the photosensitive drum 12 can be shortened. the

<Fifth Exemplary Embodiment>

17 is a schematic diagram showing the structure of the signal generating circuit 100 in the light emitting device 65 in the fifth exemplary embodiment and the wiring structure between the signal generating circuit 100 and each light emitting chip C ( C1 to C60 ). the

The fifth exemplary embodiment differs from the fourth exemplary embodiment shown in FIG. 14 in that the cancellation signal generating unit 140 described in the third exemplary embodiment is newly provided in the fifth exemplary embodiment. The erasing signal generating unit 140 is used in the signal generating circuit 100 to transmit an erasing signal φe for erasing charges accumulated in the parasitic capacitance of each gate terminal Gm to the light emitting chips C ( C1 to C60 ). the

Accordingly, the cancel signal line 102 is newly provided on the circuit board 62 . The erasing signal line 102 sends the erasing signal φe from the erasing signal generating unit 140 of the signal generating circuit 100 to the light emitting section 63 . The cancellation signal line 102 is connected in parallel to the φe terminals of the light emitting chips C (C1 to C60) (see FIG. 18 described later). Other structures are the same as those in the fourth exemplary embodiment shown in FIG. 14 . the

In the fourth exemplary embodiment, the position (number) of the light-emitting thyristor L that caused the lighting stored in the memory thyristor M is sent to the holding thyristor B, and then the location (number) of the light-emitting thyristor L that caused the lighting is deleted (cleared) from the memory thyristor M. The storage information of the position (number) of the light-emitting thyristor L, and thus the position (number) of the light-emitting thyristor L that causes lighting next time within the light-emitting period of the light-emitting thyristor L is stored in the memory thyristor M. However, in order to delete (reset) the stored information of the position (number) of the light-emitting thyristor L that caused lighting from the memory thyristor M, it is necessary to wait until the potential of the gate terminal Gm is less than -2V (<-2V). the

In the fifth exemplary embodiment, the fourth exemplary embodiment is combined with the canceling signal φe described in the third exemplary embodiment, thereby shortening until the potential of the gate terminal Gm is less than -2V (<-2V). The reset period t5. the

Note that in the fifth exemplary embodiment, the same reference numerals are given to the same components as those in the fourth exemplary embodiment, and a detailed description thereof is omitted. the

18 is a schematic diagram illustrating a circuit configuration of light-emitting chips C ( C1 to C60 ) which are self-scanning light-emitting element array (SLED) chips in the fifth exemplary embodiment. Here, the light-emitting chip C1 will be described as an example. However, the other light emitting chips C2 to C60 have the same structure as the light emitting chip C1. Note that in Figure 18. A portion including transfer thyristors T1 to T4 , memory thyristors M1 to M4 , and light-emitting thyristors L1 to L4 is mainly shown. the

The difference from the fourth exemplary embodiment shown in FIG. 14 lies in the elimination diodes Sd1 , Sd2 , Sd3 . . . newly provided in the fifth exemplary embodiment. the

The light-emitting chip C1 (C) includes cancellation diodes Sd1 , Sd2 , Sd3 . . . arranged in a line on the substrate 80 . The cancellation diodes Sd1 , Sd2 , Sd3 . . . may be Schottky diodes similarly to those in the third exemplary embodiment. the

Next, the electrical connection of the cancellation diode Sd in the light-emitting chip C1 (C) will be described. The electrical connections of the cancellation diode Sd are the same as those in the third exemplary embodiment shown in FIG. 12 . the

In other words, each anode terminal of the cancellation diode Sd1, Sd2, Sd3... is connected to a corresponding one of the gate terminals Gm1, Gm2, Gm3... of the memory thyristor M1, M2, M3.... the

The cathode terminals of the cancel diodes Sd1 , Sd2 , Sd3 . . . are connected to the cancel signal line 76 . In addition, the cancel signal line 76 is connected to a φe terminal which is an input terminal of the cancel signal φe. The cancel signal line 102 (see FIG. 17 ) is connected to the φe terminal, and the cancel signal φe is supplied to the φe terminal. the

Next, the operation of the light emitting section 63 in the fifth exemplary embodiment will be described. A signal pair of the first transfer signal φ1 and the second transfer signal φ2, the hold signal φb and the erase signal φe are commonly supplied to the light-emitting chips C (C1 to C60) constituting the light-emitting portion 63, as shown in FIG. Meanwhile, memory signals φm (φm1 to φm60 ) based on image data sets are individually supplied to the light emitting chips C ( C1 to C60 ). The lighting signals φI (φI1 to φI30) are respectively supplied to corresponding light-emitting chip pairs each composed of two light-emitting chips C, so that each lighting signal φI is shared by the two light-emitting chips constituting each pair, and is Individually supplied to the light-emitting chips C constituting different pairs. the

The fifth exemplary embodiment differs from the fourth exemplary embodiment in that the cancellation diode Sd is additionally provided. Similar to the description in the fourth exemplary embodiment, if the operation of the light-emitting chip C1 is described, the operation of the light-emitting portion 63 is understood. Therefore, the operation of the light-emitting chip C is described taking the light-emitting chip C1 as an example. the

FIG. 19 is a timing chart illustrating the operation of the light-emitting chip C1 (C) in the fifth exemplary embodiment. Also in FIG. 19 , it is assumed that the time is from time point a to time point ac (time point a to time point z, and subsequent time points aa, ab, and ac in alphabetical order). In FIG. 19, the first transfer signal φ1, the second transfer signal φ2, the memory signal φm1, the hold signal φb, the erase signal φe, the lighting signal φI1, and the current J(M1) flowing into the respective memory elements M1 to M8 are shown. to the waveform of J(M8). the

FIG. 19 shows a lighting control period T(#A) (from time point c to time point y) in the case where lighting control is performed using groups each composed of 8 light-emitting thyristors L shown in FIG. 6 and a part of the lighting control period T(#B) (from time point y and subsequent periods). Here, in the lighting control period T(#A), brightness control is performed on the light-emitting thyristors L1 to L8 in the group #A, and in the lighting control period T(#B), the light-emitting thyristor L9 in the group #B is controlled. Go to L16 for brightness control. Note that the lighting control period T(B) is followed by a lighting control period T(#C) for performing luminance control on the light-emitting thyristors L17 to L24 in the group #C, but description thereof is omitted. the

Note that in the lighting control period T(#A) in FIG. 19 , similarly to the case in the fourth exemplary embodiment, it is assumed that the light-emitting thyristor L1 , of the eight light-emitting thyristors L1 to L8 in the group #A are caused to L2, L3, L5, and L8 light up (emit light), and light-emitting thyristors L4, L6, and L7 remain unlighted (extinguished). Also, as an example, assume that the light-emitting thyristors L9 , L11 , and L12 are caused to light up (emit light) in the lighting control period T(#B) while the light-emitting thyristor L10 remains off. Assume that the image data set "11101001" is printed in the lighting control period T(#A) and the image data set "1011..." is printed in the lighting control period T(#B). the

In FIG. 19 , the waveforms of signals other than the erasing signal φe are the same as those shown in FIG. 16 . the

Here, the cancellation signal φe is mainly described. the

The potential of the erasing signal φe in the lighting control period T(#A) is "H" at the time point c, and changes from "H" to "L" at the time point v. Subsequently, its potential changes from "L" to "H" at a time point w. At the end time point y of the lighting control period T(#A), its potential is kept at "H". the

In other words, the potential of the erasing signal φe becomes "L" once in the lighting control period T(#A). the

As described above, the potential of the gate terminal Gm of the memory thyristor M which is turned off after being turned on changes from 0V to -3.3V. This rate of change is determined by a time constant defined by the parasitic capacitance of the gate terminal Gm and the power supply line resistance Rm. As described above, if the potential change of the gate terminal Gm is slow, it may be advantageous because the period t3 is set long, but it may be disadvantageous because the reset period t5 becomes longer. the

In the fifth exemplary embodiment, in order to control the reset period t5, the erasure signal φe is provided. The erase signal φe erases the charge accumulated in the parasitic capacitance of the gate terminal Gm, and erases the stored information of the memory thyristor M whose memory thyristor M has been turned on. the

Referring to FIG. 18 , operations of the light emitting portion 63 and the light emitting chip C1 (C) will be described based on the timing chart shown in FIG. 19 . the

Note that in FIG. 18 , only the part including the transfer thyristor T, the memory thyristor M, the light emitting thyristor L and the like whose numbers are all 1-4 is shown. Other parts (not shown) including thyristors whose numbers are not less than 5 are repetitions of the above-mentioned parts. in the description below. Not only elements numbered 1-4 are described, but also elements with other numbers may be described. the

The operations of the light emitting portion 63 and the light emitting chip C1 (C) from the initial state (time point a) to the time point s have been described in the third and fourth exemplary embodiments, at which time the light emitting thyristor L8 is caused to Lighted information is stored in the memory thyristor M8, and thus a detailed description thereof is omitted. the

When the potential of the holding signal φb changes from "H" to "L" at the time point t, the holding thyristors B1, B2, B3, B5, and B8 whose threshold voltage is -2.6V are turned on, while the other holding thyristors B are not turned on . Accordingly, the gate terminals Gb1 , Gb2 , Gb3 , Gb5 , and Gb8 of the holding thyristors B1 , B2 , B3 , B5 , and B8 that have been turned on become “H” (0 V) as the anode terminal potential. the

The anode terminal of each connection diode Db is connected to the gate terminal Gm, and the cathode terminal is connected to the gate terminal Gb. As described above, the gate terminals Gm1 , Gm2 , Gm3 , Gm5 , and Gm8 change from 0 V to −3.3 V from the time point u. On the other hand, the gate terminals Gm4, Gm6, and Gm7 and the gate terminal Gm of the holding thyristor B each numbered not less than 9 are held at -3.3V. Thus, thyristor B is kept in a reverse biased state, or a state in which the anode and cathode terminals have the same potential. the

Immediately after the time point t, the transfer thyristor T8 and the memory thyristors M1 , M2 , M3 , M5 , and M8 are kept in the on state, and the light-emitting thyristors L1 , L2 , L3 , L5 , and L8 are in the lighted (on) state. the

Subsequently, when the potential of the lighting signal φI1 (φI) changes from “H” to “Le” (-2.6V<“Le”≤-1.3V) at the time point u, the light-emitting thyristors L1, L2, L3, L5 and L8 are switched on and lit (glows). the

In addition, at the time point u, the potential of the memory signal φm1 (φm) changes from “S” to “H”. Accordingly, the memory thyristors M1, M2, M3, M5, and M8 that have been turned on are turned off, and the potentials of the gate terminals Gm1, Gm2, Gm3, Gm5, and Gm8 start to change from 0V to -3.3V. This rate of change is determined by a time constant defined by the parasitic capacitance of the gate terminal Gm and the power supply line resistance Rm. the

Further, when the potential of the first transfer signal φ1 changes from “H” to “L” at the time point u, the transfer thyristor T9 is turned on. the

At the time point u, the potential change of the lighting signal φI1 (φI) from “H” to “Le”, the potential change of the memory signal φm1 (φm) from “S” to “H”, and the first transition signal φ1 from The relationship between potential changes from "H" to "L" is the same as that described in the fourth exemplary embodiment. the

At the time point v, the potential of the erasing signal φe changes from "H" (0 V) to "L" (-3.3 V). Thus, the cancellation diodes Sd1, Sd2, Sd3, Sd5, and Sd8 are forward biased, and thus the potentials of the gate terminals Gm1, Gm2, Gm3, Gm5, and Gm8 become values (-2.5 V) that are obtained by This is obtained by subtracting the forward potential Vs (0.8 V) of the cancellation diode Sd from -3.3 V ("L"), as described in the third exemplary embodiment. the

In other words, by changing the cancel signal φe from "H" to "L", the potential of the gate terminal Gm of the memory thyristor M that has been turned on is forcibly set at -2.5V, and the gate terminals Gm1, Gm2, Potential changes of Gm3, Gm5 and Gm8. the

At the time point v, the potential of the hold signal φb is changed from "L" to "H". By this change, the keeping thyristors B1, B2, B3, B5 and B8 are turned off. Therefore, the stored information of the position (number) of the light-emitting thyristor L that caused the lighting is lost from the holding thyristor B. However, at the time point u, the light-emitting thyristors L1, L2, L3, L5, and L8 are already lit, so there is no problem. the

In addition, at the time point v, the potential of the second transfer signal φ2 is changed from "L" to "H". By this change, the transfer thyristor T8 is turned off. the

Note that at a time point v, the potential change of the cancel signal φe from “H” to “L”, the potential change of the hold signal φb from “L” to “H”, and the second transfer signal φ2 from “L” to “ The potential change of H" is performed simultaneously. the

These changes can be performed in any order. the

Specifically, if canceling the potential change of the signal φe from “H” to “L” is performed first, only the potential change of the gate terminal Gm is accelerated without affecting the operations of the transfer thyristor T and the holding thyristor B. the

Alternatively, if the potential change of the hold signal φb from “L” to “H” is first performed to turn off the hold thyristor B, the potential of the cathode terminal (gate terminal Gb) of the connection diode Db is changed from 0 V to −3.3 V . At the same time, the potentials of the gate terminals Gm1, Gm2, Gm3, Gm5, and Gm8, which are the anode terminals of the connection diode Db, start to change from 0V to -3.3V. Therefore, if the connection diode Db is forward biased during these potential changes, the potential change of the gate terminal Gm (from 0 V to -3.3 V) is accelerated more. Here, turning on the holding thyristor M does not affect the operation of the transfer thyristor T. the

Also alternatively, if the potential change of the second transfer signal φ2 from “L” to “H” is first performed to turn off the transfer thyristor T8, the potential of the gate terminal Gt8 is changed from 0 V to the power supply potential Vga (−3.3 V ). However, similar to the case where the potential changes of the hold signal φb from “L” to “H” are performed first, if the connection diode Dm is forward biased during these potential changes, the potential changes of the gate terminal Gt are more accelerated ( from 0V to -3.3V). the

As described above, even if these changes are performed in an arbitrary order, the operation of the light-emitting chip C is not affected. the

At the time point w, the potential of the erasing signal φe changes from "H" (0 V) to "L" (-3.3 V). Therefore, the cancellation diode Sd is forward biased, or the anode terminal and the cathode terminal have the same potential. According to the time constant defined by the parasitic capacitance of the gate terminal Gm and the power supply line resistance Rm, the potentials of the gate terminals Gm1, Gm2, Gm3, Gm5, and Gm8 further become -3.3V. the

Note that the extraction effect of charge extraction by the cancellation diode Sd is obtained in the case where the cancellation diode Sd is forward biased. Therefore, if the potential of the gate terminal Gm becomes a value obtained by subtracting the forward potential Vs from -3.3V ("L"), the extraction effect of extracting charges by the cancellation diode Sd can no longer be obtained. the

Thus, in order to effectively accelerate the potential change of the gate terminal Gm, the potential of the cancel signal φe may be changed from “L” to “ H". the

At the time point y and subsequent periods, its operation is the same as that in the fourth exemplary embodiment, and thus its detailed description is omitted. the

In the fifth exemplary embodiment, since the cancellation diode Sd accelerates the potential change of the gate terminal Gm, compared with the case in the fourth exemplary embodiment, the reset period t5 from the time point u to the time point y can be is set to be very short. Therefore, a higher light-emitting duty ratio of the light-emitting thyristor L can be set. the

Note that, in the first to fifth exemplary embodiments, although the number of light-emitting thyristors L included in each group shown in FIG. 6 is set to 8, the number may be set arbitrarily. At this time, only the timing of the signals (first transfer signal φ1, second transfer signal φ2, memory signal φm, hold signal φb, erase signal φe, and lighting signal φI) needs to be changed without changing the structure of the light-emitting chip C. the

In addition, in the first to fifth exemplary embodiments, description has been made on the assumption that the number of light-emitting thyristors L included in each light-emitting chip C is set to 128. However, this number can also be set arbitrarily. In addition, it is assumed that a self-scanning light emitting element array (SLED) is mounted on one light emitting chip C. As shown in FIG. However, a plurality of SLEDs may be mounted on each light emitting chip C. Referring to FIG. the

In addition, the description has been made on the assumption that the number of light-emitting thyristors L is the same as the respective numbers of transfer thyristors T, memory thyristors M, and holding thyristors B. FIG. However, it is also acceptable that the number of transfer thyristors T is greater than the number of light emitting thyristors L. This is achieved by driving the device with portions of the first transfer signal φ1 and the second transfer signal φ when the image data set is not being written. the

In the first to fifth exemplary embodiments, it is assumed that the memory signal φm is individually supplied to the light-emitting chips C, and each lighting signal φI is supplied to the corresponding two light-emitting chips C in common. However, the lighting signal φI may be supplied to the light-emitting chips C individually, or each lighting signal φI may be supplied to three or more light-emitting chips C in common. the

Alternatively, by connecting a plurality of light-emitting chips C in series to form a plurality of light-emitting chips C like a self-scanning light-emitting element array (SLED) chip, the memory signal φm and the lighting signal φI can be commonly supplied to the multiple light-emitting chips C connected in series to each other. A light-emitting chip C. the

In the first to fifth exemplary embodiments, the case of a common anode in which the substrate is provided as the anode terminal of the thyristor was described. By changing the polarity of the circuit, common cathode thyristors can be used where the substrate is provided as the cathode terminal. the

In addition, in the first to fifth exemplary embodiments, the light emitting chip C is formed of a GaAs-based semiconductor such as GaAs, GaAlAs, or the like, but the material of the light emitting chip C is not limited thereto. For example, the light emitting chip C may be formed of other compound semiconductors that are difficult to become p-type semiconductors or n-type semiconductors by ion implantation, such as GaP. the

Note that the use of the light emitting device in the present invention is not limited to the exposure device used in the electrophotographic image forming unit. In addition to electrophotographic recording, display, illumination, optical communication, etc., the light emitting device in the present invention can also be used for optical writing. the

The foregoing description of the exemplary embodiments of the present invention has been presented for purposes of illustration and description. It is not intended to be exhaustive or to limit the invention to the precise forms disclosed. Obviously, many modifications and variations will occur to those skilled in the art. The exemplary embodiment was chosen and described in order to best explain the principles of the invention and its practical application, thereby enabling others skilled in the art to understand various embodiments of the invention to which it is applicable and to foresee suitable applications for particular applications. various modifications. It is intended that the scope of the invention be defined by the appended claims and their equivalents. the

Claims (12)

1. A lighting device, comprising: Array of self-scanning light-emitting elements, including: A plurality of light-emitting elements arranged in a straight line; A plurality of memory elements, which are arranged to correspond to and electrically connect to the respective light emitting elements, each of the memory elements is set in any one of an on state and an off state, and is set in an off state. The plurality of memory elements makes it easy for each light emitting element to be set in the on state when being set in the on state compared to the case of being in the off state; and a plurality of switching elements provided corresponding to and electrically connected to the respective memory elements, each of which is set in any one of an on state and an off state, the plurality of switching elements Being set to allow the conduction state to sequentially move from one end side to the other end side, in the case of being set in the conduction state, the plurality of switching elements makes it easy for each memory element to is set in a conducting state; and Light up controllers, including: a transfer signal generating unit that supplies a transfer signal to the plurality of switching elements, the transfer signal setting the plurality of switching elements so as to allow the conduction state to sequentially shift from one end side to the other end side; a memory signal generation unit that supplies a memory signal to a plurality of memory elements corresponding to a plurality of light emitting elements of one of a plurality of groups into which the plurality of light emitting elements are divided, in relation to the light emitting elements forming the group When the corresponding switch element is set in the conduction state, if it is desired to turn on the light emitting element corresponding to the switch element, the memory signal is made to correspond to the switch element set in the conduction state The memory element of the switch temporarily changes from the off state to the on state, and if the light emitting element corresponding to the switching element is not to be lit, the memory signal causes the memory corresponding to the switching element set in the on state to keeping the element in the off state, and then temporarily setting the memory element which has been temporarily turned on in the on state again; and a lighting signal generating unit that supplies a lighting signal to the plurality of light emitting elements for each group, after setting a memory element corresponding to a light emitting element to be turned on in an on state, the point The ON signal causes the light-emitting element to be turned on to be set in a conductive state. 2. The light emitting device according to claim 1, wherein, The self-scanning light-emitting element array further includes a plurality of canceling elements disposed corresponding to and electrically connected to the respective memory elements, and The lighting controller further includes a canceling signal generating unit that supplies a canceling signal to the plurality of canceling elements, and a light emitting element to be lit in the group is set in a conductive state. Thereafter, the cancel signal prevents the memory element corresponding to the light-emitting element to be turned on from being set in a conductive state. 3. The light emitting device according to claim 1 or 2, wherein, The self-scanning light-emitting element array further includes a plurality of holding elements disposed between the respective light-emitting elements and the respective memory elements so as to correspond to the respective light-emitting elements and the respective memory elements, and electrically connected to the respective light-emitting elements With each memory element, in a case where each memory element is set in an on state, the plurality of holding elements makes it easy to light up each light emitting element as compared with a case of an off state, and The lighting controller further includes a hold signal generation unit that supplies a hold signal to the plurality of hold elements so that a memory element corresponding to a light emitting element in the group that is to be turned on After being set in the conducting state, the hold signal causes the holding element corresponding to the memory element in the conducting state to be set in the conducting state. 4. A lighting device, comprising: Array of self-scanning light-emitting elements, including: Substrate; a plurality of light-emitting thyristors formed on the substrate and arranged in a line; a plurality of memory thyristors formed on the substrate and arranged to correspond to the respective light emitting thyristors and electrically connected to the respective light emitting thyristors, each of the memory thyristors being set in either of an on state and an off state state, the plurality of memory thyristors changes the respective threshold voltages of the plurality of light-emitting thyristors to values that, when set in the on state, compared with the case of being set in the off state, said value makes it easy for each light-emitting thyristor to be set in a conducting state; and a plurality of transfer thyristors formed on the substrate and arranged to correspond to the respective memory thyristors and electrically connected to the respective memory thyristors, each of which is set in either an on state or an off state state, the plurality of transfer thyristors are set to allow the on-state to move sequentially from one end side to the other end side, and to change the respective threshold voltages of the plurality of memory thyristors to values that are the same as in the case of the off-state Said value makes it easy for each memory thyristor to be set in a conductive state, compared to being set in a conductive state; and Light up controllers, including: a transfer signal generation unit that supplies a transfer signal to the plurality of transfer thyristors, the transfer signal setting the plurality of transfer thyristors so as to allow the conduction state to sequentially shift from one end side to the other end side; a memory signal generating unit that supplies a memory signal to a plurality of memory thyristors corresponding to a plurality of light emitting thyristors of one of a plurality of groups into which the plurality of light emitting thyristors are divided, in conjunction with the light emitting thyristors forming the group In the case where the corresponding transfer thyristor is set in the conduction state, if it is desired to turn on the light-emitting thyristor corresponding to the transfer thyristor, the memory signal is made to correspond to the transfer thyristor set in the conduction state The memory thyristor of the switch temporarily changes from the off state to the on state, and if the light-emitting thyristor corresponding to the transfer thyristor is not wanted to be lit, the memory signal makes the memory corresponding to the transfer thyristor set in the on state maintaining the thyristor in an off state, and then temporarily setting the memory thyristor, which has been temporarily turned on, in an on state again; and a lighting signal generation unit that supplies a lighting signal to the plurality of light-emitting thyristors for each group, after setting a memory thyristor corresponding to a light-emitting thyristor to be turned on in an on state, the point The light-on signal causes the light-emitting thyristor to be turned on to be set in a conducting state. 5. The light emitting device according to claim 4, wherein, The self-scanning light-emitting element array further includes a plurality of cancellation diodes disposed corresponding to and electrically connected to the respective memory thyristors, and The lighting controller further includes a canceling signal generation unit that supplies a canceling signal to the plurality of canceling diodes, and a light emitting thyristor to be lit in the group is set in an on state. Thereafter, the cancel signal prevents the memory thyristor corresponding to the light-emitting thyristor to be turned on from being set in a conducting state. 6. The light emitting device according to claim 5, wherein, The elimination diodes of the self-scanning light-emitting element array are Schottky diodes. 7. The light emitting device according to any one of claims 4 to 6, wherein, The self-scanning light-emitting element array further includes a plurality of holding thyristors formed on the substrate and disposed between the respective light-emitting thyristors and the respective memory thyristors so as to correspond to the respective light-emitting thyristors and the respective memory thyristors. , and are electrically connected to the respective light-emitting thyristors and the respective memory thyristors, the plurality of holding thyristors change the respective threshold voltages of the plurality of light-emitting thyristors to values that, in the plurality of In the case where the memory thyristors are set in a conductive state, the value is such that the respective light emitting thyristors are easily set in a conductive state, and The lighting controller further includes a holding signal generating unit that supplies a holding signal to the plurality of holding thyristors such that a memory thyristor corresponding to a light-emitting thyristor to be turned on in the group After being set in the on state, the hold signal causes the hold thyristors corresponding to the memory thyristors in the on state to be set in the on state. 8. A driving method for a self-scanning light-emitting element array, the self-scanning light-emitting element array comprising: a plurality of light-emitting elements arranged in a straight line; a plurality of memory elements, which are arranged to correspond to each light-emitting element and are electrically connected to each light-emitting element elements, each of the memory elements is set in any one of the on state and the off state, compared with the case of setting in the off state, in the case of setting in the on state, the a plurality of memory elements so that the respective light emitting elements are easily set in the conduction state; and a plurality of switching elements, which are arranged to correspond to the respective memory elements and electrically connected to the respective memory elements, each of which is set in the conduction state And any one of the off-states, the plurality of switching elements are set to allow the on-state to move sequentially from one end side to the other end side, compared with the case of the off-state, when set in the on-state In the case of a state, the plurality of switching elements make it easy for each memory element to be set in a conduction state, and the driving method includes: supplying a transfer signal to the plurality of switching elements so that conduction states of the plurality of switching elements are sequentially shifted from one end side to the other end side; A memory signal is supplied to a plurality of memory elements corresponding to a plurality of light emitting elements of one of a plurality of groups into which the plurality of light emitting elements are divided, after switching elements corresponding to the light emitting elements forming the group are turned on. In the case of being set in the on state, if it is desired to turn on the light emitting element corresponding to the switching element, the memory signal causes the memory element corresponding to the switching element set in the on state to be temporarily turned off. The off state is changed to the on state, and if the light emitting element corresponding to the switching element is not intended to be lit, the memory signal causes the memory element corresponding to the switching element set in the on state to be kept in the off state , and subsequently causing the memory element that has been temporarily turned into the conductive state to be temporarily set in the conductive state again; and A lighting signal is supplied to the plurality of light emitting elements for each group, the lighting signal causing the desired light emitting element to be turned on after setting the memory element corresponding to the light emitting element to be turned on. Lighted light-emitting elements are set in a conductive state. 9. The driving method of the self-scanning light-emitting element array according to claim 8, wherein, The self-scanning light-emitting element array further includes a plurality of canceling elements disposed corresponding to and electrically connected to the respective memory elements, and The driving method further includes: supplying a canceling signal to the plurality of canceling elements, the canceling signal preventing the desired The memory element corresponding to the lit light-emitting element is set in a conductive state. 10. The driving method of the self-scanning light-emitting element array according to claim 8 or 9, wherein, The self-scanning light-emitting element array further includes a plurality of holding elements disposed between the respective light-emitting elements and the respective memory elements so as to correspond to the respective light-emitting elements and the respective memory elements, and electrically connected to the respective light-emitting elements With each memory element, in a case where each memory element is set in an on state, the plurality of holding elements makes it easy to light up each light emitting element as compared with a case of an off state, and The driving method further includes: supplying a hold signal to the plurality of hold elements, the hold signal is activated after setting a memory element corresponding to a light emitting element in the group to be turned on. The holding element corresponding to the memory element in the on state is caused to be set in the on state. 11. A print head comprising: an exposure unit that exposes the image carrier and includes: Array of self-scanning light-emitting elements, including: A plurality of light-emitting elements arranged in a straight line; A plurality of memory elements, which are arranged to correspond to and electrically connect to the respective light emitting elements, each of the memory elements is set in any one of the on state and the off state, and is set in the off state. The plurality of memory elements makes it easy for each light emitting element to be set in the on state when being set in the on state compared to the case of being in the off state; and a plurality of switching elements provided corresponding to and electrically connected to the respective memory elements, each of which is set in any one of an on state and an off state, the plurality of switching elements Being set to allow the conduction state to sequentially move from one end side to the other end side, in the case of being set in the conduction state, the plurality of switching elements makes it easy for each memory element to is set in a conducting state; and Light up controllers, including: a transfer signal generating unit that supplies a transfer signal to the plurality of switching elements, the transfer signal setting the plurality of switching elements so as to allow the conduction state to sequentially shift from one end side to the other end side; a memory signal generation unit that supplies a memory signal to a plurality of memory elements corresponding to a plurality of light emitting elements of one of a plurality of groups into which the plurality of light emitting elements are divided, in relation to the light emitting elements forming the group When the corresponding switch element is set in the conduction state, if it is desired to turn on the light emitting element corresponding to the switch element, the memory signal is made to correspond to the switch element set in the conduction state The memory element of the switch temporarily changes from the off state to the on state, and if the light emitting element corresponding to the switching element is not to be lit, the memory signal causes the memory corresponding to the switching element set in the on state to keeping the element in the off state, and then temporarily setting the memory element which has been temporarily turned on in the on state again; and a lighting signal generating unit that supplies a lighting signal to the plurality of light emitting elements for each group, after setting a memory element corresponding to a light emitting element to be turned on in an on state, the point A bright signal causes the light-emitting element to be turned on to be set in a conductive state; and an optical unit that condenses light emitted from the exposure unit onto the image carrier. 12. An image forming apparatus comprising: a charging unit that charges the image carrier; an exposure unit that exposes the image carrier and includes: Array of self-scanning light-emitting elements, including: A plurality of light-emitting elements arranged in a straight line; A plurality of memory elements, which are arranged to correspond to and electrically connect to the respective light emitting elements, each of the memory elements is set in any one of the on state and the off state, and is set in the off state. The plurality of memory elements makes it easy for each light emitting element to be set in the on state when being set in the on state compared to the case of being in the off state; and a plurality of switching elements provided corresponding to and electrically connected to the respective memory elements, each of which is set in any one of an on state and an off state, the plurality of switching elements Being set to allow the conduction state to sequentially move from one end side to the other end side, in the case of being set in the conduction state, the plurality of switching elements makes it easy for each memory element to is set in a conducting state; and Light up controllers, including: a transfer signal generating unit that supplies a transfer signal to the plurality of switching elements, the transfer signal setting the plurality of switching elements so as to allow the conduction state to sequentially shift from one end side to the other end side; a memory signal generation unit that supplies a memory signal to a plurality of memory elements corresponding to a plurality of light emitting elements of one of a plurality of groups into which the plurality of light emitting elements are divided, in relation to the light emitting elements forming the group When the corresponding switch element is set in the conduction state, if it is desired to turn on the light emitting element corresponding to the switch element, the memory signal is made to correspond to the switch element set in the conduction state The memory element of the switch temporarily changes from the off state to the on state, and if the light emitting element corresponding to the switching element is not to be lit, the memory signal causes the memory corresponding to the switching element set in the on state to keeping the element in the off state, and then temporarily setting the memory element which has been temporarily turned on in the on state again; and a lighting signal generating unit that supplies a lighting signal to the plurality of light emitting elements for each group, after setting a memory element corresponding to a light emitting element to be turned on in an on state, the point The bright signal causes the light-emitting element to be turned on to be set in a conduction state; an optical unit that condenses light emitted from the exposure unit onto the image carrier; a developing unit that develops an electrostatic latent image formed on the image carrier; and A transfer unit that transfers the image developed on the image carrier to the object to be transferred.

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