CN102013887B - Driver for reducing voltage swing for digital-to-analog converter - Google Patents
Driver for reducing voltage swing for digital-to-analog converter Download PDFInfo
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- CN102013887B CN102013887B CN2009101952097A CN200910195209A CN102013887B CN 102013887 B CN102013887 B CN 102013887B CN 2009101952097 A CN2009101952097 A CN 2009101952097A CN 200910195209 A CN200910195209 A CN 200910195209A CN 102013887 B CN102013887 B CN 102013887B
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Abstract
本发明属数模转换器集成电路技术领域，涉及一种降低电压摆幅驱动器。本发明利用电容分压原理，降低输出电压的摆幅，通过调节电容比值来改变摆幅的大小。本发明应用在数模转换器中，位置在锁存器和电流开关之间，能降低摆幅，减小信号串通对差分电流开关的共源点和差分输出的影响，同时能够调节差分信号的交叉点的位置，避免差分电流开关同时处在关断的状态，明显提高了数模转换器的动态性能。本发明结构简单，易于实现，而且低功耗，适合于高速数模转换器。
The invention belongs to the technical field of digital-to-analog converter integrated circuits, and relates to a driver for reducing voltage swing. The invention utilizes the principle of capacitor voltage division to reduce the swing amplitude of the output voltage, and changes the swing amplitude by adjusting the capacitance ratio. The present invention is applied in the digital-to-analog converter, and the position is between the latch and the current switch, which can reduce the swing amplitude, reduce the influence of signal collusion on the common source point and differential output of the differential current switch, and can adjust the differential signal at the same time The location of the cross point prevents the differential current switches from being in an off state at the same time, which significantly improves the dynamic performance of the digital-to-analog converter. The invention has a simple structure, is easy to implement, and has low power consumption, and is suitable for high-speed digital-to-analog converters.
Description
Technical field
The invention belongs to technical field of integrated circuits, be specifically related to a kind of reduction voltage swing driver that is applied to digital to analog converter.
Background technology
Along with communication and development of semiconductor, communication system and wireless data transmission technology develop rapidly, and particularly continuing to bring out of technology such as 3G/4G, Home eNodeB and phase battle array control radar proposed very high requirement to high performance analogue device.Analog part more and more comes into one's own as the conversion portion of analog signal and digital signal, and communication system increases the market demand of high-speed A/D converter (DAC) gradually.
For DAC, the index of weighing its performance has static and dynamic two indexs, and dynamic indicator promptly is SFDR (SFDR).The dynamic indicator of high-speed DAC is very important.Research shows that the factor that influences the DAC dynamic indicator mainly contains following several kinds: the differential input signal of (1) current switch array is asynchronous; Burr when (2) worst case is overturn; (3) variation of current source array output impedance; (4) because the difference current switch goes out at off state simultaneously, cause current source drain terminal voltage dithering, to such an extent as to the output current shake.Above-mentioned first three influencing factor can some technology improve; For (4) kind influencing factor, existing many pieces of documents have given multiple relevant solution.But the essence of said method all is the position through the crosspoint that changes rising edge and trailing edge, so that the difference current switch can not get into closed condition simultaneously.Method in the document [1] is to make rising edge time and trailing edge time asymmetric, thereby changes the position in crosspoint, but asymmetric rising edge and trailing edge cause asynchronous that difference exports in this method, have reduced SFDR; Method in the document [2] adopts has the latch than the positive feedback structure of logic; And through separately for latch provides a supply voltage, except can further regulating the crosspoint, can also reduce ganging up of signal; But because the power supply that provides separately makes complex designization; Adopt delay cell to change duty ratio in the document [3], thereby change the crosspoint.
The list of references relevant with the present invention has:
[1]T.W.Wu，C.T.Jih，J.C.Chen，etc.A?low?glitch?10-bit?75-MHz?CMOSvideo?D/A?converter[J].IEEE?Journal?of?Solid-State?Circuits，1995，30：68-72.
[2]J.Bastos，A.M.Marques，M.S.J.Steyaert，etc.A?12-bit?intrinsicaccuracy?high-speed?CMOS?DAC[J].IEEE?Journal?of?Solid-State?Circuits，1998，33：1959-1969.
[3]K.Hiroyuki，N.Yasuyuki，etc.A?350MS?3.3V?8bit?CMOS?D/A?converterusing?a?delayed?driving?scheme[J].IEEE?Custom?Integrated?CircuitsConference，1995，10：211-214.
Summary of the invention
The present invention is intended to improve the defective that exists in the prior art, and a kind of reduction voltage swing driver that is used for digital to analog converter is provided.
Particularly, the invention provides a kind of reduction voltage swing driver, it utilizes the capacitance partial pressure principle, reduces the amplitude of oscillation of output voltage, changes the size of the amplitude of oscillation through control capacittance ratio.The present invention reduces the voltage swing driver applications in digital to analog converter; Be positioned between latch (Latch) and the current switch (Switch); Can improve described in the prior art (4) and plant influencing factor, avoid separately, reduce through reducing the influence that voltage swing makes signal gang up to latch provides power supply; Can reduce the influence of ganging up of signal to the common source point of difference current switch; Can further improve simultaneously the position in crosspoint, avoid the difference current switch to be in the state of shutoff simultaneously, improve the dynamic characteristic of DAC.The present invention can be used for technological high speed digital to analog converter chips such as radio communication base station, military radar and wireless data transmission.
Reduction voltage swing driver of the present invention adopts the principle of capacitance partial pressure, and the voltage swing value of output can be adjusted to ground (GND) to the arbitrary value between the supply voltage (VDD), and is simple in structure and power consumption is little, can adopt to be easy to integrated CMOS technology and to realize.
Among the present invention, described reduction voltage swing driver is connected between the latch and difference current switch in the DAC structure, and is as shown in Figure 1.Input signal carries out synchronously through latch, and preliminary treatment is carried out in the crosspoint, the signal swing of latch output be GND to VDD, after reducing the voltage swing driver, voltage swing is reduced to suitable value, and has regulated the position in crosspoint once more.Signal after the adjusting is used for the Control current switch, has improved the high-speed DAC dynamic property greatly.
Among the present invention, utilize the capacitance partial pressure principle, reduce the amplitude of oscillation of output voltage, change the size of the amplitude of oscillation through control capacittance ratio; Wherein, by shown in Figure 3, NMOS pipe M1, M2, M4, M5 and PMOS manage M3, M6 as switch, wherein, the source end ground connection of M1 pipe, the positive terminal of grid termination differential input signal, drain terminal connects node 1; The source terminated nodes 1 of M2 pipe, grid terminated nodes 5, drain terminal connects node 2; The source termination power of M3 pipe, grid terminated nodes 5, drain terminal connects node 2; The source end ground connection of M4 pipe, the end of oppisite phase of grid termination differential input signal, drain terminal connects node 4; The source terminated nodes 4 of M5 pipe, grid terminated nodes 6, drain terminal connects node 3; The source termination power of M6 pipe, grid terminated nodes 6, drain terminal connects node 3; NMOS pipe M9 and M10, with PMOS pipe M7 and M8 as metal-oxide-semiconductor electric capacity, wherein, the source end of M9, drain terminal and substrate ground connection, grid terminated nodes 1; The source end of M10, drain terminal and substrate ground connection, grid terminated nodes 4; Source end, drain terminal and the substrate of M7 connect power supply, grid terminated nodes 2; Source end, drain terminal and the substrate of M8 connect power supply, grid terminated nodes 3; The N termination power of diode D1, P terminated nodes 1, the N termination power of diode D2, P terminated nodes 4; PMOS pipe M11 and NMOS pipe M12 form inverter, and PMOS pipe M13 and NMOS pipe M14 form inverter, wherein; The source termination power of M11 pipe, the positive terminal of grid termination input signal, drain terminal connects node 5; The source end ground connection of M12 pipe, the positive terminal of grid termination input signal, drain terminal connects node 5; The source termination power of M13 pipe, the end of oppisite phase of grid termination input signal, drain terminal connects node 6, the source end ground connection of M12 pipe, the end of oppisite phase of grid termination input signal, drain terminal connects node 6.
Among the present invention, described reduction voltage swing driver, it is arranged in the difference output end that the differential input end that reduces the voltage swing driver connects the DAC latch, and the difference output end that reduces the voltage swing driver connects the input of difference current switch.
Among the present invention; Between described node 1 and the power supply; And inserting diode D1 and D2 between node 4 and the power supply respectively, diode D1 and D2 are realized by the PMOS pipe, make grid end, source end and the substrate of PMOS pipe be connected together as the N end of diode; Connect on the power supply, drain terminal terminates on node 1 or the node 4 as the P of diode.
Among the present invention, node 1 connects the difference current switch that the PMOS pipe is formed with node 4 as difference output end, and node 2 connects the difference current switch that the NMOS pipe is formed with node 3 as difference output end.
Among the present invention, among the metal-oxide-semiconductor M7～M10 as electric capacity, M7 and M8 are made up of the PMOS pipe, and M9 and M10 are made up of the NMOS pipe.
The present invention combines Fig. 2 that its principle further clearly is described.Among Fig. 2, Latch_op, Latch_on are the difference output of latch, control switch S respectively
1～S
3And S
4～S
6, S wherein
2And S
5Be that Latch_op and Latch_on control through inverter INV1 and INV2, switch is conducting at high level.Four capacitor C
1～C
4Be to be used for carrying out dividing potential drop, general C
1=C
3, C
2=C
4Can know that according to the capacitance partial pressure principle output voltage V op and Von are respectively:
In actual design, the ratio of electric capacity is can not make the difference current switch get into cut-off state simultaneously according to output voltage V op and Von to choose suitable value.
Reduction voltage swing driver provided by the invention can improve the position in differential output voltage crosspoint through the size of regulating pipe.
The distinguishing feature of reduction voltage swing driver of the present invention is embodied in: adopt the capacitance partial pressure principle to reduce output voltage swing; Reduce to optimize when train of signal is corresponded topic the position in crosspoint, its circuit structure is simple, is easy to realize; And low-power consumption, be suitable for high-speed A/D converter.
Description of drawings
The position of Fig. 1 reduction voltage swing of the present invention driver in the DAC structure;
The schematic diagram of Fig. 2 reduction voltage swing of the present invention driver;
The implementation structure of Fig. 3 reduction voltage swing of the present invention driver;
The implementation structure of diode in Fig. 4 reduction voltage swing of the present invention driver;
The structure chart of Fig. 5 reduction voltage swing of the present invention driver drives PMOS current switch;
The structure chart of Fig. 6 reduction voltage swing of the present invention driver drives NMOS current switch;
The output of Fig. 7 reduction voltage swing of the present invention driver when driving the PMOS current switch;
The output of Fig. 8 reduction voltage swing of the present invention driver when driving N MOS current switch.
Indicate explanation among the figure:
NMOS pipe M1, M2, M4, M5 and PMOS pipe M3, M6 are switch, wherein, the source end ground connection of M1 pipe, the positive terminal of grid termination differential input signal, drain terminal connects node 1; The source terminated nodes 1 of M2 pipe, grid terminated nodes 5, drain terminal connects node 2; The source termination power of M3 pipe, grid terminated nodes 5, drain terminal connects node 2; The source end ground connection of M4 pipe, the end of oppisite phase of grid termination differential input signal, drain terminal connects node 4; The source terminated nodes 4 of M5 pipe, grid terminated nodes 6, drain terminal connects node 3; The source termination power of M6 pipe, grid terminated nodes 6, drain terminal connects node 3;
NMOS pipe M9 and M10, with PMOS pipe M7 and M8 as metal-oxide-semiconductor electric capacity, wherein, the source end of M9, drain terminal and substrate ground connection, grid terminated nodes 1; The source end of M10, drain terminal and substrate ground connection, grid terminated nodes 4; Source end, drain terminal and the substrate of M7 connect power supply, grid terminated nodes 2; Source end, drain terminal and the substrate of M8 connect power supply, grid terminated nodes 3;
The N termination power of diode D1, P terminated nodes 1, the N termination power of diode D2, P terminated nodes 4;
PMOS pipe M11 and NMOS pipe M12 form inverter, and PMOS pipe M13 and NMOS pipe M14 form inverter, wherein; The source termination power of M11 pipe, the positive terminal of grid termination input signal, drain terminal connects node 5; The source end ground connection of M12 pipe, the positive terminal of grid termination input signal, drain terminal connects node 5;
The source termination power of M13 pipe, the end of oppisite phase of grid termination input signal, drain terminal connects node 6, the source end ground connection of M12 pipe, the end of oppisite phase of grid termination input signal, drain terminal connects node 6.
For the ease of understanding, below will describe in detail of the present invention through concrete accompanying drawing and embodiment.What need particularly point out is; Instantiation and accompanying drawing only are in order to explain; Obviously those of ordinary skill in the art can explain according to this paper, within the scope of the invention the present invention is made various corrections and change, and these corrections and change are also included in the scope of the present invention.In addition, the present invention has quoted open source literature, and these documents are in order more clearly to describe the present invention, and their full text content is all included this paper in and carried out reference, just looks like that repeated description is the same excessively in this article for their full text.
Below the embodiment conjunction with figs. is specified implementation structure of the present invention, technology contents and effect.
Embodiment
Fig. 3 is the structure chart of reduction voltage swing driver of the present invention.Metal-oxide-semiconductor M1～M6 has replaced the switch among Fig. 2, and metal-oxide-semiconductor M7～M10 replaces the electric capacity among Fig. 2.M1, M2, M4, M5, M9, M10 realize that by the NMOS pipe M3, M6, M7, M8 are realized that by PMOS M11 and M12, M13 and M14 form inverter respectively.D1 and D2 are diode, can be realized by NMOS or PMOS pipe.
For M7～M10 pipe, source end, drain terminal and the substrate with each pipe is connected together respectively, as an end of electric capacity.The measure-alike of M7 and M8 is set, and M9 and M10's is measure-alike.If the capacitance size that M7 and M8 form is C
1, the capacitance size that M9 and M10 form is C
2
Suppose that working as Latch_op is 1, Latch_on is 0.Switching tube M1 conducting, M2 closes, the M3 conducting, M4 closes, the M5 conducting, M6 closes.Like this, node 1 is moved to ground (GND) and power supply (VDD) respectively with node 2, and the voltage of node 3 and node 4 is in the same place through the M5 short circuit, and its voltage is:
V
On=0.
Suppose that working as Latch_op is 0, Latch_on is 1.Switching tube M1 closes, the M2 conducting, and M3 closes, the M4 conducting, M5 closes, the M6 conducting.Like this, node 4 is moved to ground (GND) and power supply (VDD) respectively with node 3, and the voltage of node 1 and node 2 is in the same place through the M2 short circuit, and its voltage is: V
Op=0,
It is thus clear that the output voltage that reduces the voltage swing driver is through capacity ratio C
1/ (C
1+ C
2) be limited in the supply voltage, realize reducing the function of voltage swing.
Regulate rising edge and trailing edge time through the size of by-pass cock pipe M1～M6 and the size of electric capacity M7～M10, and then regulate the position in crosspoint.
Diode D1 and D2 can be realized by PMOS, like Fig. 4.For D1, source electrode, grid and the substrate of PMOS is connected on VDD, drain electrode is connected on node 1, for D2, source electrode, grid and the substrate of PMOS is connected on VDD, and drain electrode is connected on node 2.
The effect of diode D1 and D2 is the speed that discharges and recharges of accelerating electric capacity.Area through regulating diode D1 and D2 changes the speed of discharging and recharging, and then regulates the position in crosspoint.
In DAC, current switch can be realized by PMOS according to the different different implementations that is designed with, can be realized by NMOS again.Like Fig. 5, current switch is made up of the PMOS differential pair tube, reduces the voltage swing output end of driver and is picked out by node 1 and node 4.Like Fig. 6, current switch is made up of pipe nmos differential, reduces the voltage swing output end of driver and is picked out by node 2 and node 3.Under above two kinds of situation, the output that reduces the voltage swing driver is provided by Fig. 7 and Fig. 8 respectively.In Fig. 7, the voltage swing scope is 0～Vx, and in Fig. 8, voltage swing is VDD～Vx.In order to make current switch when the operate as normal; A conducting; One is ended; Need satisfy min{Vx; (VDD-Vx) } greater than
of the overdrive voltage of switching tube doubly, i.e.
Claims (4)
1. be used for the reduction voltage swing driver of digital to analog converter, it is characterized in that, utilize the capacitance partial pressure principle, reduce the amplitude of oscillation of output voltage, change the size of voltage swing through control capacittance ratio; In said reduction voltage swing driver:
Manage M3, M6 as switch with NMOS pipe M1, M2, M4, M5 and PMOS, wherein, the source end ground connection of M1 pipe, the positive terminal of grid termination differential input signal, drain terminal connects node 1; The source terminated nodes 1 of M2 pipe, grid terminated nodes 5, drain terminal connects node 2; The source termination power of M3 pipe, grid terminated nodes 5, drain terminal connects node 2; The source end ground connection of M4 pipe, the end of oppisite phase of grid termination differential input signal, drain terminal connects node 4; The source terminated nodes 4 of M5 pipe, grid terminated nodes 6, drain terminal connects node 3; The source termination power of M6 pipe, grid terminated nodes 6, drain terminal connects node 3; NMOS pipe M9 and M10, with PMOS pipe M7 and M8 as metal-oxide-semiconductor electric capacity, wherein, the source end of M9, drain terminal and substrate ground connection, grid terminated nodes 1; The source end of M10, drain terminal and substrate ground connection, grid terminated nodes 4; Source end, drain terminal and the substrate of M7 connect power supply, grid terminated nodes 2; Source end, drain terminal and the substrate of M8 connect power supply, grid terminated nodes 3; The N termination power of diode D1, P terminated nodes 1, the N termination power of diode D2, P terminated nodes 4; PMOS pipe M11 and NMOS pipe M12 form inverter, and PMOS pipe M13 and NMOS pipe M14 form inverter, wherein; The source termination power of M11 pipe; The positive terminal of grid termination differential input signal, drain terminal connects node 5, the source end ground connection of M12 pipe; The positive terminal of grid termination differential input signal, drain terminal connects node 5; The source termination power of M13 pipe, the end of oppisite phase of grid termination differential input signal, drain terminal connects node 6, the source end ground connection of M14 pipe, the end of oppisite phase of grid termination differential input signal, drain terminal connects node 6.
2. the reduction voltage swing driver that is used for digital to analog converter according to claim 1; It is characterized in that; The differential input end that reduces the voltage swing driver connects the difference output end of latch in the digital to analog converter, and the difference output end that reduces the voltage swing driver connects the input of the difference current switch in the digital to analog converter.
3. the reduction voltage swing driver that is used for digital to analog converter according to claim 1; It is characterized in that; Described diode D1 and D2 are realized by the PMOS pipe; Make grid end, source end and the substrate of PMOS pipe be connected together as the N end of diode, connect on the power supply, drain terminal terminates on node 1 or the node 4 as the P of diode.
4. the reduction voltage swing driver that is used for digital to analog converter according to claim 1; It is characterized in that; Node 1 connects the difference current switch that the PMOS pipe is formed with node 4 as difference output end, and perhaps node 2 connects the difference current switch that the NMOS pipe is formed with node 3 as difference output end.
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| Application Number | Priority Date | Filing Date | Title |
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| CN2009101952097A CN102013887B (en) | 2009-09-04 | 2009-09-04 | Driver for reducing voltage swing for digital-to-analog converter |
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|---|---|---|---|
| CN2009101952097A CN102013887B (en) | 2009-09-04 | 2009-09-04 | Driver for reducing voltage swing for digital-to-analog converter |
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| CN102013887A CN102013887A (en) | 2011-04-13 |
| CN102013887B true CN102013887B (en) | 2012-05-23 |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| US9225565B2 (en) * | 2012-03-20 | 2015-12-29 | Intel Deutschland Gmbh | Device for generating a vector-modulated output signal and method for generating a vector-modulated output signal |
| CN110138388A (en) * | 2018-02-09 | 2019-08-16 | 长沙泰科阳微电子有限公司 | A kind of anti-interference high-performance current steering DAC circuit |
| CN111966158B (en) * | 2020-08-24 | 2021-10-01 | 中国电子科技集团公司第二十四研究所 | Complementary low-drift constant current source and control method thereof |
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|---|---|---|---|---|
| CN1306347A (en) * | 2000-01-17 | 2001-08-01 | 华为技术有限公司 | D/A converter with current helm structure for 12c logic |
| CN1527485A (en) * | 2003-01-23 | 2004-09-08 | ���ǵ�����ʽ���� | Digital to analog converter with low time-lag and low interference |
| US7064695B2 (en) * | 2003-12-10 | 2006-06-20 | Samsung Electronics, Co., Ltd. | Differential switching circuit and digital-to-analog converter |
| CN1829063A (en) * | 2006-01-23 | 2006-09-06 | 北京万工科技有限公司 | Voltage amplitude limiter for current supply switch in high-speed A/D converter |
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2009
- 2009-09-04 CN CN2009101952097A patent/CN102013887B/en not_active Expired - Fee Related
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1306347A (en) * | 2000-01-17 | 2001-08-01 | 华为技术有限公司 | D/A converter with current helm structure for 12c logic |
| CN1527485A (en) * | 2003-01-23 | 2004-09-08 | ���ǵ�����ʽ���� | Digital to analog converter with low time-lag and low interference |
| US7064695B2 (en) * | 2003-12-10 | 2006-06-20 | Samsung Electronics, Co., Ltd. | Differential switching circuit and digital-to-analog converter |
| CN1829063A (en) * | 2006-01-23 | 2006-09-06 | 北京万工科技有限公司 | Voltage amplitude limiter for current supply switch in high-speed A/D converter |
Non-Patent Citations (1)
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| 崔福良 等.一种用于数模转换器的电流-电压转换电路.《固体电子学研究与进展》.2004,第24卷(第4期),第493-497页. * |
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