CN102013431A - Umbrella memory cell with self-aligning bottom electrode and diode access device - Google Patents

Abstract

The invention discloses an umbrella-shaped memory cell with a self-aligned bottom electrode and a diode access device. The memory device disclosed in the present invention includes a plurality of word lines extending in a first direction and a plurality of bit lines on the word lines extending in a second direction. The apparatus includes a plurality of memory cells at the intersection location. Each memory cell includes a diode having first and second sides and aligned with a side of a corresponding wordline of the plurality of wordlines. Each memory cell also includes a bottom electrode self-centering in the diode, the bottom electrode having a top surface with a surface area that is less than the surface area of the top surface of the diode. Each memory cell includes a strip of memory material on the top surface of the bottom electrode, the strip of memory material being under and electrically connected to a corresponding bit line of the plurality of bit lines.

Description

Umbrella memory cell with self-aligning bottom electrode and diode access device

technical field

The present invention relates to high density memory devices using phase change memory materials, such as chalcogenides and other materials, and methods of making such devices.

Background technique

Such phase-change memory materials, such as chalcogenides and similar materials, can be caused to change their crystalline phase between an amorphous state and a crystalline state by applying a current of a magnitude suitable for use in an integrated circuit. Generally speaking, the characteristic of the amorphous state is that its resistance is higher than that of the crystalline state, and this resistance value can be easily measured and used as an indicator. This property has sparked interest in using programmable resistive materials to form nonvolatile memory circuits that can be used for random access reading and writing.

The transition from the amorphous state to the crystalline state is generally a low current step. The transition from a crystalline state to an amorphous state (hereinafter referred to as reset) is generally a high current step, which includes a short pulse of high current density to melt or break the crystalline structure, after which the phase change material is rapidly cooled, The process of inhibiting the phase change so that at least part of the phase change structure is maintained in an amorphous state. Ideally, the magnitude of the reset current that causes the phase change material to transition from a crystalline state to an amorphous state should be as low as possible.

In order to reduce the current amplitude required for reset, it can also be achieved by reducing the size of the phase change memory element in the memory cell, and/or the contact area between the electrode and the phase change material, so that it can be achieved at a relatively small absolute current value Higher current densities are achieved by means of the phase change material elements.

One way to control the size of the active region in a phase change cell is to design very small electrodes to deliver current into a body of phase change material. The tiny electrode structure induces a phase change in the umbrella-like small area in the phase change material, that is, the contact point. Please refer to US Patent No. 6,429,064 "Reduced Contact Areas of Sidewall Conductor" issued to Wicker on August 22, 2002, and US Patent No. 6,462,353 "Method for Fabricating a Small Area of Contact Between Electrodes" issued to Gilgen on October 8, 2002. US Patent No. 6,501,111 "Three-Dimensional (3D) Programmable Device" issued to Lowrey on /12/31, and US Patent No. 6,563,156 "MemoryElements and Methods for Making same" issued to Harshfield on July 1, 2003.

Various problems arise from the need to meet stricter specifications and process variations in the manufacture of devices with very small dimensions, mass production of large-scale high-density storage devices.

Therefore, there is a need to provide a memory cell structure with a small size and low reset current, and a method of manufacturing the structure to meet the stricter specifications required for mass production of large-scale high-density memory devices.

Contents of the invention

In view of this, the main purpose of the present invention is to provide a storage device and a manufacturing method thereof.

The invention discloses a storage device, which includes a plurality of word lines extending to a first direction, and a plurality of bit lines on the word lines and extending to a second direction. The bit line intersects the word line at an intersection point. The device includes a plurality of memory cells at the intersection location. Each memory cell includes a diode having first and second sides aligned to sides of a corresponding one of the plurality of word lines, the diode having a top surface. Each memory cell also includes a bottom electrode self-centering on the diode, the bottom electrode having a top surface, and the top surface having a surface area that is less than the surface area of the top surface of the diode. Each memory cell further includes a strip of memory material on the top surface of the bottom electrode, the strip of memory material is under and electrically connected to a corresponding bit line of the plurality of bit lines.

The present invention discloses a method for fabricating a memory device, the method comprising forming a structure comprising a word line material, a diode material on the word line material, a first material on the diode material, and a second material on the second material. on a material layer. A plurality of dielectric-filled first trenches are formed in the structure and extend in a first direction to define a plurality of strips of memory material, each comprising a wordline comprising wordline material. A plurality of dielectric filled second trenches are formed under the word line and extending in a second direction to define a plurality of stacks. Each stack comprises a diode comprising the diode material over a corresponding word line and having a top surface, a first element comprising a first material over the diode, a second element comprising a second material over the first over a component. Bottom electrodes are formed on a corresponding diode of the first element and the second element using the stack. A strip of memory material is formed on the top surface of the top electrode, and a bit line is formed on the strip of memory material.

The memory cell of the present invention allows the active area within the memory element to be made extremely small, thereby reducing the amount of current required to induce a phase change. The strips of memory material can be achieved using thin film deposition techniques. Furthermore, the bottom electrode has a top surface and has a surface area smaller than the top surface of the diode. In addition, the width of the bottom electrode is smaller than the width of the diode, and preferably smaller than the minimum feature size of the photolithography process generally used to form word lines and bit lines of memory devices. The small bottom electrode concentrates the current density in that portion of the memory element, thereby reducing the amount of current required to induce a phase change in the active region. Additionally, the dielectric material surrounding the bottom electrode in embodiments may provide some thermal insulation, which also helps reduce the amount of current required to induce a phase change.

The memory cells described in the present invention can produce high density memory. In an embodiment, the cross-sectional area of the memory cells of the array is entirely determined by the size of the wordlines and bitlines, which allows the array to have a high memory density. The word line has a word line width and adjacent word lines are separated by a word line separation distance, and the bit line has a bit line width and adjacent bit lines are separated by a bit line separation distance. In a preferred embodiment, the sum of the word line width and the word line separation distance is equal to twice the feature size F used to form the array, and the sum of the bit line width and the bit line separation distance is equal to the feature size F used to form the array twice as much. In addition, F is preferably the minimum feature size of a process (usually a photolithography process) used to form the bit line and the word line, so that the memory array has a memory cell area of 4F ² .

The purpose and advantages of the present invention can be fully understood through the following description of the attached drawings, implementation methods and scope of claims.

Description of drawings

FIG. 1 is a schematic diagram showing a portion of a cross-point array implementation described in the present invention using umbrella memory cells with self-aligned bottom electrodes and diode access devices.

2A to 2B are cross-sectional views showing a first embodiment of memory cells arranged in a cross-point array.

3A to 3B are cross-sectional views showing a second embodiment of memory cells arranged in a cross-point array.

4A to 4B are cross-sectional views showing a third embodiment of memory cells arranged in a cross-point array.

5 to 14 are steps showing the manufacturing sequence of the intersection array of memory cells shown in FIGS. 3A to 3B .

FIGS. 15-16 illustrate an alternative fabrication embodiment to the example shown in FIGS. 12-13 , resulting in memory cells as shown in FIGS. 3A-3B .

17-26 illustrate an alternative manufacturing embodiment to that depicted in FIGS. 10-14.

FIG. 27 illustrates an alternative embodiment of FIG. 20 for forming the bottom electrode, illustrating the formation of the bottom electrode having a ring-shaped top electrode.

28-29 illustrate an alternative manufacturing technique to that shown in FIGS. 21-24.

30 is a simplified block diagram of an integrated circuit comprising a cross-point array of umbrella memory cells with self-aligned bottom electrodes and diode access devices as described herein.

[Description of main component symbols]

10 integrated circuits

14 drives

16 word line

18-bit line decoder

20 bit line

22 bus

24 sense amplifiers

26 data bus

24 Data Entry Structure

28 data input lines

30 circuits

32 data output lines

34 controllers

36 bias adjustment supply voltage

100 array

111 first conductive element

113 second conductive element

115 storage units

116 top surface

120-bit line

120a bit line

120b bit line

120c bit line

121 diodes

122 first doped semiconductor region

123a side

123b side

124 second doped semiconductor region

124 width

125 separation distance

126pn junction

127 side

130 word line

130a word line

130b word line

130c word line

132 separation distance

133a side

133b side

134 width

140 dielectric spacers

141 side

150 storage material strips

150b storage material strip

155 active areas

160 memory elements

163 width

165 inner surface

167 outer surface

170 dielectric

172 filling material

180 Conductive Overlay

300 Dielectric

310 Dielectric

312 diode material

315 total thickness

320 first doped semiconductor material layer

330 second doped semiconductor material layer

340 layer of conductor mask material

345 thickness

350 Dielectric Spacer Material

355 thickness

360 Sacrificial Component Materials

365 thickness

400 layers of strips

410 bottom electrode

420 pitch

500 dielectric filler material

510 character line material

512 diode material

520 first doped semiconductor material layer

530 second doped semiconductor material layer

540 layer of conductive cover material

550 first material

560 second material

600 strips

610 first groove

700 dielectric filler material

800 second groove

810 laminated

820 first element

830 second element

1000 side wall surface

1100 tailoring elements

1200 openings

1700 vias

1800 sidewall spacers

1810 opening

1900 opening

2100 sacrificial material strips

2110 separation distance

2200 Dielectric Material Strips

2300 Groove

2500 oxide layer

2600 overall word line

2610 Conductive Via

2620 peripheral circuit

2900 first dielectric layer

2910 second dielectric layer

Detailed ways

The following description of the invention will generally refer to specific structural embodiments and methods. It will be understood that the invention is not limited to its detailed description, particularly with respect to the disclosed embodiments and methods, and the invention can also be practiced using other features, elements, methods, and embodiments. The preferred embodiments described in the present invention are not intended to limit its scope, but are defined in the scope of the claims. Those skilled in the art can also understand various equivalent changes in the embodiments of the present invention. Elements as used in the various embodiments are commonly referenced by like element numbers.

1 is a schematic diagram showing a portion of a cross-point memory array 100 implementation described in the present invention using fully self-aligned umbrella memory cells with bottom electrodes and diode access devices.

As shown in the schematic diagram of FIG. 1 , each memory cell of the array 100 includes a diode access device and a memory element (represented by a variable resistor in FIG. 1 ) that can be set to multiple resistance states. One, and thus can store one or more bits of data.

The array 100 includes a plurality of word lines 130 and bit lines 120, the plurality of word lines 130 includes word lines 130a, 130b and 130c extending parallel to the first direction, and the plurality of bit lines 120 includes word lines extending parallel to the second direction bit lines 120a, 120b and 120c. The array 100 is shown as a crosspoint array because the wordlines 130 and bitlines 120 are arranged in such a way that a given wordline 130 and a given bitline 120 straddle each other rather than actually intersecting, and the memory cells are located at the word At the intersection of the line 130 and the bit line 120 .

The memory cell 115 is representative of the memory cell of the array 100 and is disposed at the intersection of the bit line 120b and the word line 130b. The memory cell 115 includes a diode 121 and memory elements 160 arranged in series. The diode 121 is electrically coupled to The word line 130b and the memory element 160 are electrically coupled to the bit line 120b.

Reading and writing of the memory cells 115 of the array 100 can be achieved by applying appropriate voltages and/or currents to the corresponding word lines 130 b and bit lines 120 b to induce current flow through the selected memory cells 115 . The magnitude and duration of the applied voltage and current depend on the operation being performed, such as a read operation or a write operation.

In a reset (or erase) operation of a memory cell 115 having a memory element 160 comprising a phase change material, a reset pulse is applied to the corresponding word line 130b and bit line 120b to cause the active region of the phase change material to become amorphous state, thereby setting the resistance within the range of resistance values associated with the reset state. The reset pulse is a relatively high energy pulse sufficient to raise the temperature of at least the active region of memory element 160 above the transition (crystallization) temperature of the phase change material, and above the melting temperature such that at least the active region is in a liquid state. Then, the reset pulse is quickly terminated, resulting in a relatively fast cooling time, which rapidly cools the active region below the transition temperature, so that the active region can stabilize to an amorphous state.

In a set (or program) operation of a memory cell 115 having a memory element 160 comprising a phase change material, applying a program pulse of an appropriate size and duration to the corresponding word line 130b and bit line 120b is sufficient to cause at least a portion of Raising the temperature of a portion of the active region above the transition temperature and causing a transition of a portion of the active region from an amorphous state to a crystalline state reduces the resistance of memory element 160 and sets memory cell 115 to an state of desire.

In a read (or sense) operation of the data value stored in memory cell 115 having memory element 160 comprising phase change material, a read pulse of appropriate size and duration is applied to corresponding word line 130b and The bit line 120b induces a current to flow, which does not cause the memory element 160 to change the resistance state. The current flowing through memory cell 115 is dependent on the resistance of the memory element, and thus the data value is stored in memory cell 115 .

2A and FIG. 2B are cross-sectional views showing a part of memory cells (including representative memory cells 115) disposed in the intersection array 100. FIG. 2A is taken along the bit line 120 and FIG. 2B is taken along the word line. 130 sections.

Referring to FIG. 2A and FIG. 2B, the memory cell 115 includes a first doped semiconductor region 122 with a first conductivity type, and a second doped semiconductor region 124 on the first doped semiconductor region 122, the second doped semiconductor region 124 The hetero semiconductor region 124 has a second conductivity type opposite to the first conductivity type. The first doped semiconductor region 122 and the second doped semiconductor region 124 define a pn junction 126 therebetween.

The memory cell 115 includes a conductive capping layer 180 located on the second doped semiconductor region 124 . The first and second doped semiconductor regions 122 , 124 and the conductive capping layer 180 comprise a multilayer structure to define the diode 121 . In an exemplary embodiment, the conductive capping layer 180 includes a metal silicide including titanium, tungsten, cobalt, nickel or tantalum. The conductive capping layer 180 helps maintain contact across the first and second doped semiconductor regions 122, 124 during operation by providing a contact surface of higher conductivity than the first and second doped semiconductor regions 122, 124. The uniformity of the electric field of 122,124. In addition, the conductive capping layer 180 can be used as a protective etch stop layer for the second doped semiconductor region 124 during the fabrication of the memory cell 100 .

The first doped semiconductor region 122 is located on the word line 130b, and the word line 130b extends into and out of the cross section shown in FIG. 2A. In an exemplary embodiment, the word line 130b includes a doped N ⁺ (highly doped N-type) semiconductor material, the first doped semiconductor region 122 includes a doped N ⁻ (lightly doped N-type) semiconductor material, and The second doped semiconductor region 124 includes doped P ⁺ (highly doped P-type) semiconductor material. It can be seen that the breakdown voltage of diode 121 can be increased by increasing the distance between the P ⁺ doped region and the N ⁺ doped region, and/or reducing the doping concentration in the N ⁻ region.

In another embodiment, the word line 130 may include other conductive materials, such as tungsten, titanium nitride, tantalum nitride, aluminum. In yet another embodiment, the first doped semiconductor region 122 can be omitted, and the diode 121 can be formed by the second doped semiconductor region 124 , the conductive capping layer 180 and a part of the word line 130b.

A bottom electrode 110 is located on the diode 121 and electrically couples the diode 121 to a portion of a memory element comprising a strip of memory material 150b and below the bit line 120b. The memory material may comprise, for example, a compound selected from the group consisting of germanium, antimony, tellurium, selenium, indium, titanium, gallium, bismuth, tin, copper, palladium, lead, silver, sulfur, silicon, oxygen, phosphorus, arsenic, nitrogen and gold. A group of one or more materials.

The bottom electrode 110 may comprise, for example, titanium nitride or tantalum nitride. In embodiments of the memory element 160 in which GSTs (discussed below) are included, titanium nitride is preferred because it has good contact with the GSTs, it is a common material commonly used in semiconductor fabrication, and it provides a good diffusion barrier layer. Alternatively, the bottom electrode 110 may be aluminum titanium nitride or aluminum tantalum nitride, or further include, for example, one or more elements selected from the following group: titanium, tungsten, molybdenum, aluminum, tantalum, copper, platinum, iridium, lanthanum, Nickel, nitrogen, oxygen and ruthenium and combinations thereof.

A dielectric spacer 140 contacts an outer surface 167 of the bottom electrode 110 and surrounds the bottom electrode 110 . The dielectric spacer 140 preferably comprises a material that blocks the diffusion of the memory material of the memory element 160 . In some embodiments, the material of the dielectric spacer 140 may be selected to have low thermal conductivity for reasons discussed in detail below. Dielectric spacer 140 has sides 141 that are self-aligning with sides 125 of diode 121 .

Bit line 120 including bit line 120b as the top electrode of memory cell 115 extends into and out of the cross-section shown in FIG. 2B. The bit line 120 may comprise one or more conductive materials as described above with reference to the bottom electrode 110 .

A dielectric 170 comprising one or more layers of dielectric material surrounds the memory cell and separates adjacent word lines 130 and adjacent bit lines 120 .

In operation, voltages on wordline 130b and bitline 120b induce current through memory element 160 and diode 121 .

The active region 155 is the region of the memory element 160 where the memory material is induced to change between at least two solid state phases. It can be appreciated that in the illustrated structure, the active region 155 can be made extremely small, thereby reducing the amount of current required to induce a phase change. The thickness of the strips of memory material 150 can be achieved using thin film deposition techniques. In some embodiments, the thickness is less than 100 nm, such as between 10 nm and 100 nm. Furthermore, the bottom electrode 110 has a top surface 116 and has a surface area smaller than the top surface 181 of the diode 121 . In addition, the width 112 of the bottom electrode 110 is smaller than the width of the diode 121 , and preferably lower than the minimum feature size of the photolithography process generally used to form the word lines 130 and bit lines 120 of the memory array 100 . The small bottom electrode 110 can concentrate the current density in the portion of the memory element 160 adjacent to the top surface 116 of the bottom electrode 110 , thereby reducing the amount of current required to induce a phase change in the active region 155 . Additionally, dielectric spacer 140 preferably comprises a material that provides thermal isolation to active region 155, which also helps reduce the amount of current required to induce a phase change.

It can be seen from the cross-sections shown in FIG. 2A and FIG. 2B that the memory cells of the array 100 are arranged at the intersections of the word lines 130 and the bit lines 120 . The memory cell 115 is representative and is arranged at the intersection of the word line 130b and the bit line 120b. Diode 121, dielectric spacer 140, and memory element 160 form a structure of memory cell 115 having a first width that is substantially the same as width 134 of word line 130 (see FIG. 2A). Again, the structure has a second width that is substantially the same as the width of the bit line 120 (see FIG. 2B ). The term "substantially" as used herein is intended to accommodate manufacturing tolerances. Therefore, the cross-sectional area of the memory cells of the array 100 is completely determined by the sizes of the word lines 130 and the bit lines 120, allowing the array 100 to have a higher memory density.

The wordline 130 has a wordline width 134, and adjacent wordlines 130 are separated by a wordline separation distance 132 (see FIG. 2A ), and the bitline 120 has a bitline width 124, and adjacent bitlines 120 are separated by a The bitlines are separated by a separation distance 125 (see FIG. 2B ). In a preferred embodiment, the sum of the word line width 134 and the word line separation distance 132 is equal to twice the feature size F used to form the array 100, and the sum of the bit line width and the bit line separation distance 125 is equal to the sum of the bit line separation distance 125 used to form the array. Twice the characteristic dimension F of 100. In addition, F is preferably the minimum feature size of the process (usually a photolithography process) used to form the bit line 120 and the word line 130, so that the memory cell of the array 100 has a memory cell area 4F2.

In the memory array shown in FIGS. 2A-2B , the bottom electrode 110 is self-centered on the diode, and the diode has first and second sides 125a, 125b aligned with side 131a of the lower word line 130b , 131b. In a first manufacturing embodiment (see Figures 17 to 20 below for details), the side spacer 140 defines an opening forming the bottom electrode 110, and in a second embodiment (see Figures 5 to 20 below for details). FIG. 14 ) The bottom electrode 110 and the dielectric 170 define an opening forming the sidewall spacer 140 .

3A and FIG. 3B show a cross-sectional view of a part of a second embodiment of a memory cell (including representative memory cell 115) arranged in a cross-point array 100. FIG. 3A shows the bit line 120 and FIG. 3B is a drawing The word line 130 is shown.

In the embodiment of FIGS. 3A and 3B , the bottom electrode 210 includes a first conductive element 111 above the diode 121 and has a side 212 along the side 125 of the diode 121, and a second conductive element 111. The element 113 is automatically centered on the first conductive element 111 , and the second conductive element 113 has a width 117 smaller than that of the first conductive element 111 . In the exemplary embodiment the first conductive element comprises a conductive material such as titanium nitride, and the second conductive element 113 comprises amorphous silicon.

A dielectric layer 300 is located on an upper surface of the first conductive element 111 and the dielectric 170 , and the dielectric 300 surrounds the second conductive element 113 of the bottom electrode 210 . As shown in FIG. 3B , a dielectric 310 also separates adjacent bit lines and adjacent strips of memory material 150 .

As can be seen from the above, in the illustrated structure, the active region 155 can be made extremely small, thereby reducing the magnitude of the current required to induce the phase change. The thickness 152 of the strip of memory material 150 can be achieved using thin film deposition techniques. Furthermore, the bottom electrode 210 has a top surface 116 and has a surface area smaller than that of the top surface 181 of the diode 121 . In addition, the width 117 of the bottom electrode 210 is smaller than the width of the diode 121 , and preferably smaller than the minimum feature size of the photolithography process generally used to form the word line 130 and the bit line 120 of the memory device 100 . The small second conductive element 113 concentrates the current density in the portion of the memory element 160 adjacent to the top surface 116 of the bottom electrode 210 , thereby reducing the amount of current required to induce a phase change in the active region 155 . Additionally, the dielectric layer 300 preferably includes a material that provides thermal isolation to the active region 155, which also helps reduce the amount of current required to induce a phase change.

In the embodiment shown in FIGS. 3A to 3B , the first conductive element 111 has a side 212 aligned with the side 125 of the diode 121 , and the second conductive element 113 is automatically centered on the first conductive element 113 . conductive element 111 . For a more detailed description, please refer to Figures 10 to 11 and Figures 15 to 16 below. The materials of the first conductive element 111 and the second conductive element 113 are firstly patterned during the formation of the diode 121, and then the material of the second conductive element 113 is anisotropically etched to form the first conductive element with a width 117. The second conductive element 113 , and the width 117 is smaller than the width of the first conductive element 111 .

4A and 4B show a cross-sectional view of a part of a third embodiment of a memory cell (including a representative memory cell 115) arranged in a cross-point array 100. FIG. 4A shows the bit line 120 and FIG. 4B is a drawing The word line 130 is shown.

In the embodiment of FIGS. 4A and 4B , the bottom electrode 410 has an inner surface 165 defining an inner region containing the filling material 172 . In the exemplary embodiment, the filling material 172 is an electrically insulating material with a lower thermal conductivity than the bottom electrode 410 material. Fill material 172 comprises silicon nitride in the illustrated embodiment.

The inner surface 165 and the outer surface 167 of the bottom electrode 410 define an annular top surface 116 of the bottom electrode 410 and are in contact with the memory material strip 150b. In an embodiment the annular top surface is defined by the outer surface 165 and the inner surface 167, which can be circular, oval, rectangular or other irregularly shaped cross-sections depending on the intended use. A manufacturing technique for forming the bottom electrode 410 . The “ring shape” of the top surface 116 in the present invention does not have to be a circle, but should be determined by the shape of the bottom electrode 410 .

As can be seen from the above, in the illustrated structure, the active region 155 can be made extremely small, thereby reducing the magnitude of the current required to induce the phase change. The thickness 152 of the strip of memory material 150 can be achieved using thin film deposition techniques. Furthermore, the bottom electrode 410 can be formed by using conformal deposition techniques within an opening defined by the dielectric spacer 140, and is preferably smaller than the minimum photolithographic process typically used to form the memory device 100. feature size. The small thickness 119 makes the small annular top surface 116 of the bottom electrode 410 contact the memory element 160 of the memory material strip 150b. The small annular bottom electrode 410 concentrates the current density in the portion of the memory element 160 adjacent the annular top surface 116 , thereby reducing the amount of current required to induce a phase change in the active region 155 . Additionally, the fill material 172 and the sidewall spacers 140 preferably comprise materials that can provide thermal isolation of the active region 155, which also helps reduce the amount of current required to induce a phase change.

In the memory array 100 shown in FIGS. 4A-4B , the bottom electrode 410 is self-centered on the diode, and the diode 121 is aligned to the lower word line 130b. Please refer to FIG. 17 to FIG. 19 and FIG. 27 below for details. The material of the sidewall spacer 140 is first patterned during the formation of the diode 121, and then the material of the bottom electrode 410 is formed on the sidewall spacer. 140 inside the opening formed.

5 to 14 are steps showing the manufacturing sequence of the cross-point array 100 of memory cells as shown in FIGS. 3A to 3B .

5A-5B show a first step in forming a structure 500 in top and cross-sectional views. The structure 500 includes a wordline material 510 and a diode material 512 on the wordline material 510 .

The diode material 512 includes a first doped semiconductor material layer 520 , a second doped semiconductor material layer 530 , and a conductive capping material layer 540 on the second doped semiconductor material layer 530 .

In this exemplary embodiment, the word line material 610 includes doped N ⁺ (high concentration N-type doping) semiconductor material, and the first doped semiconductor material layer 520 includes doped N ⁻ (low concentration N-type doping) The semiconductor material, and the second doped semiconductor material layer 530 includes a doped P ⁺ (high concentration P-type doped) semiconductor material. Layers 510, 520, 530 may be formed by known techniques such as implantation and activation tempering processes.

In the exemplary embodiment, the conductive capping material layer 540 comprises a metal silicide comprising titanium, tungsten, cobalt, nickel or tantalum. In one embodiment, the conductive capping material layer 540 includes cobalt silicide (CoSi) and is formed by depositing a layer of cobalt and performing a rapid thermal process (RTP) to react the cobalt with the silicon of layer 530 to form layer 540 . It should be appreciated that other metal suicides may also be formed by depositing titanium, arsenic, doped nickel, or alloys thereof in this manner (similar to the example described here using cobalt).

A first material 550 is on the diode material 512 , and a second material 560 is on the first material 550 . Layers 550, 560 preferably comprise a material that can be selectively processed (eg, selectively etched) relative to the other. In the exemplary embodiment, layer 550 may comprise a conductive bottom electrode material (eg, titanium nitride) or may also comprise a dielectric spacer material (eg, silicon nitride), depending on the fabrication implementation used to form the memory cell. example. In an example embodiment, this layer 560 includes amorphous silicon.

In the illustrated embodiment, layers 510, 520, 530 have a total thickness 515 of about 300 nm, layer 540 has a thickness 545 of about 20 nm, layer 550 has a thickness 555 of about 100 nm, and layer 560 has a thickness 565 of about 100 nm.

Next, the structure 500 is patterned to form a plurality of first trenches 610 extending in a first direction to define a plurality of strips 600, each strip 600 includes a word line 130 including a word line material layer 510, respectively The structure shown in the top and cross-sectional views of Figures 4A and 4B is obtained. The word lines 130 have a width 134 and a separation distance 132, which are both preferably equal to the minimum feature size of the process (such as the photolithographic process) used to form the first trench 610 .

Next, the trenches 610 of the structure shown in FIGS. 6A-6B are filled with a dielectric filling material 700 to obtain the structures shown in the top view and cross-sectional view of FIGS. 7A and 7B , respectively. Dielectric fill material 700 may comprise, for example, silicon dioxide, and may be formed by depositing the material 700 within trench 610, and then performing a planarization process such as chemical mechanical polishing (CMP).

Next, the structures shown in FIGS. 7A to 7B are patterned to form a plurality of second trenches 800 extending parallel to the second direction to define a plurality of stacks 810, respectively to obtain the top view of FIG. 8A and the top view of FIGS. 8B to 8 . 8D cutaway view of the structure shown. Patterning the trench 800 and the stack 810 can be formed by patterning a photoresist layer over the structures shown in FIGS. 7A-7B , and etching down to the word lines using the patterned photoresist as an etch mask. 130.

As shown in the cross-sectional views of FIGS. 8B to 8C , each stack 810 includes a diode 121 including diode material on the corresponding word line 130 , a first element 820 including a first material layer 550 on the diode 121 , And a second element 830 including the second material layer 560 on the first element 730 .

The diode 121 includes a first doped semiconductor region 122 including a material layer 520 , and a second doped semiconductor region 124 including a material layer 530 . The first doped semiconductor region 122 and the second doped semiconductor region 124 define a pn junction 126 therebetween.

The stack 810 is self-aligned due to the formation of the first trench 610 of FIGS. 6A-6B and the subsequent formation of the second trench 800 of FIGS. to the corresponding lower word line 130 . In addition, the stack 810 has minimum feature widths 812, 814 and separation distances 816, 818 that are preferably equal to the process (typically a photolithographic process) used to form the trenches 610 and 810 .

Next, the trenches 800 of the structures shown in FIGS. 8A-8D are filled with additional dielectric filling material 700 to obtain the structures shown in the top view of FIG. 9A and the cross-sectional views of FIGS. 9B-9D , respectively. In the illustrated embodiment, trench 800 is filled with the same material as that used to fill dielectric 700 as trench 610 described above with reference to FIGS. 7A-7B . The dielectric fill material 700 may be formed by depositing material within the trench 800 , followed by a planarization process such as chemical mechanical polishing (CMP) to expose the top surface of the second element 830 . In an embodiment, the trench 800 is formed using a patterned photoresist mask, and the patterned photoresist mask may be removed using a planarization process such as CMP.

Next, the dielectric filling material 700 of the first trench 610 and the second trench 800 is removed to expose the sidewall surface 1000 of the second device 830, and the top view of FIG. 10A and the cross-sections of FIGS. 10B to 10C are obtained. The structure shown in the figure.

Next, the second element 830 of FIGS. 10A-10D is trimmed to a smaller width, thus forming a trimmed element 1100 having a structural width as depicted in the top view of FIG. 11A and the cross-sectional views of FIGS. 11B-11D . In the illustrated embodiment, an isotropic etching process is used to reduce the thickness and the width of the second element 830 to form the tailored element 1100 . In the exemplary embodiment, the second element 830 comprises amorphous silicon and can be removed by isotropic etching using, for example, KOH wet or tetramethylammonium hydroxide (THMA). Alternatively for various materials reactive ion etching can be used to shear the element 830 . As shown in the drawings, the shear element 1100 has a width 1100 smaller than the diode 121 of the stack 810 and covers only a portion of the first element 820 . Because the diode 121 preferably has a width equal to the minimum feature size of the process used to form the diode. In one embodiment, the tailoring element 1100 has a width of about 30 nm.

In the drawings, the tailoring element 1100 has a square-like cross-section. However, in embodiments, the tailoring element 1100 may be circular, oval, rectangular, or other irregular shape, depending on the manufacturing technique used to form the tailoring element 1100 .

Next, use the tailoring element 1100 as a mask to etch the first element 820 to form the bottom electrode 110 and the opening 1200 surrounding the bottom electrode 110, and obtain the top view of FIG. 12A and the cross-sectional views of FIGS. 12B to 12D. The structure shown.

As shown in the drawing, the opening 1200 extends to the conductive capping layer 180 , and the conductive capping layer 180 acts as an etch stop layer when the opening 1200 is formed.

In FIGS. 12A to 12D , the bottom electrode 110 has a square-like cross section. However, in embodiments, the bottom electrode 110 may be circular, elliptical, rectangular or other irregular shapes, depending on the fabrication technique used to form the tailoring element 1100 and the bottom electrode 110 .

Next, the sidewall spacers 140 are formed in the openings 1200 shown in FIGS. 12A to 12D to obtain the structures shown in the top view of FIG. 13A and the cross-sectional views of FIGS. 13B to 13D . In the illustrated embodiment, the dielectric spacers comprise SiON and are formed by depositing a dielectric spacer material on FIGS. 12A-12D , followed by planarization, such as by a CMP process.

Next, the storage material strips 150 and the bit lines 120 are formed on the corresponding storage material strips 150 above the structures shown in FIGS. Structure. The memory material strips 150 and bit lines 120 can be formed by forming memory material on the structure shown in FIGS. 13A-13D , forming bit line material on the memory material, patterning the bit line material. patterning a photoresist layer, and then using the patterned photoresist as an etch mask to etch the bit line material and storage material.

15-16 show an alternative fabrication embodiment to that shown in FIGS. 12-13 to obtain the memory cell shown in FIGS. 3A-3B .

A dielectric layer 300 is formed on the structure shown in FIGS. 11A-11D to surround the tailored second element 1100 , resulting in the structure shown in the top view of FIG. 15A and the cross-sectional views of FIGS. 15B-15D . The tailored second element 1100 of FIG. 11 is bounded by the second conductive element 113 of the bottom electrode 210 , and the first element 820 is bounded by the first conductive element 111 of the bottom electrode 210 .

Next, the storage material strips 150 and the bit lines 120 are formed on the corresponding storage material strips 150 above the structures shown in FIGS. 15A to 15D , so as to obtain the structures shown in FIGS. 16A to 16D . The memory material strips 150 and bit lines 120 can be formed by forming memory material on the structure shown in FIGS. 15A-15D , forming bit line material on the memory material, patterning the bit line material. patterning a photoresist layer, and then using the patterned photoresist as an etch mask to etch the bit line material and storage material.

17-24 show an alternative manufacturing embodiment to that shown in FIGS. 10-14.

The second element 830 of the stack 810 of FIGS. 9A-9D is removed to form a via 1700 and expose the first element 820, as shown in the top view of FIG. 17A and the cross-sectional views of FIGS. 17B-17D. Structure. In an exemplary embodiment, the second element 830 comprises amorphous silicon and can be etched away using, for example, KOH or THMA.

Next, a sidewall spacer 1800 is formed in the via hole 1700 in FIGS. 17A to 17D , so as to obtain the structure shown in the top view of FIG. 18A and the cross-sectional views of FIGS. 18B to 18D . The sidewall spacer 1800 defines an opening 1810 within the via 1700, and in the illustrated embodiment the sidewall spacer 1800 comprises silicon.

The sidewall spacer 1800 may be formed by forming a conformal dielectric material layer on FIGS. 17A-17D , and anisotropically etching the conformal dielectric material layer to expose a portion of the first element 820. .

In the exemplary embodiment, the sidewall spacer 1800 defines an opening 1810 having a square-like cross-section. However, in embodiments, the opening 1810 may be circular, oval, rectangular or other irregular shape, depending on the fabrication technique used to form the sidewall spacer 1800 .

Next, the first element 820 is etched using the sidewall spacer 1800 as a mask to form a dielectric spacer 140, and the structure shown in the top view of FIG. 19A and the cross-sectional views of FIGS. 19B-19D is obtained.

Referring to FIGS. 19A-19D , the dielectric spacer 140 has an opening 1900 extending to the conductive capping layer 180 , which acts as an etch stop layer when the dielectric spacer 140 is formed.

Next, bottom electrode material is formed within the opening 1900 defined by the dielectric spacer 140, and a planarization process (eg, CMP) is performed to remove the sidewall spacer 1800, thereby forming a self-centering diode 121. The bottom electrode 110 of FIG. 20A has a structure as shown in the top view of FIG. 20A and the cross-sectional views of FIGS. 20B to 20D . For example, the bottom electrode material may include titanium nitride or tantalum nitride.

In the illustrated embodiment, the bottom electrode 110 has a square-like cross-section. However, in embodiments, the bottom electrode 110 may have a circular, elliptical, rectangular or other irregular shape, depending on the fabrication technique used to form the sidewall spacer 1800 and the opening 1900 .

Then, a strip of sacrificial material 2100 is formed along the second direction on the structure shown in FIGS. 20A-20D , so as to obtain the structure shown in the top view of FIG. 21A and the cross-section of FIGS. 21A-21B . The sacrificial material strips 2100 extend parallel to the second direction and have a width 2110 and a separation distance 2110 , each of the sacrificial material strips 2100 is connected to the top surfaces of the plurality of bottom electrodes 110 . In the illustrated embodiment, the strips of sacrificial material 2100 comprise amorphous silicon. The strip of sacrificial material 2100 may be formed by forming a material layer on the structure shown in FIGS. 20A-20D and patterning the material layer using a photolithography process.

Next, strips of dielectric material 2200 are formed between the strips of sacrificial material 2100 to obtain the structure shown in the top view of FIG. 22A and the top and cross-sectional views of FIGS. 22B-22D . The strip of dielectric material 2200 may be formed by depositing a dielectric material on the structure shown in FIGS. 21A-21D , followed by a planarization process (eg, CMP) to expose the top surface of the strip of sacrificial material 2100 . In the illustrated embodiment, the dielectric material 2200 includes silicon nitride.

Next, the strips of sacrificial material 2100 are removed to expose the top surface of the bottom electrode 110, and trenches 2300 are defined between the strips of dielectric material 2200 to obtain the top view of FIG. 23A and the top view of FIGS. 23B-23D. The structure shown in the cross-sectional view. In the illustrated embodiment, the strips of sacrificial material 2100 comprise amorphous silicon and can be etched away using, for example, KOH or THMA.

Next, a storage material strip 150 is formed in the trench 2300 and a bit line 120 is formed on the corresponding storage material strip 150 to obtain the structure shown in the top view of FIG. 24A and the cross-sectional views of FIGS. 24B to 24D . The storage material strips 150 and bit lines 120 can be formed by depositing storage material using CVD or PVD on the structure shown in FIGS. Ion etching back and forth etches the memory material to form the memory material strip 150 and fills the trench 2300 with bit line material and forms the bit line 120 .

Next, an oxide layer 2500 is formed on the structures shown in FIGS. 24A to 24D to obtain the structures shown in the top view of FIG. 25A and the cross-sectional views of FIGS. 25B to 25D .

Next, an array of conductive vias 2610 extends through the oxide layer 2500 to connect a corresponding word line 130 and form an integral word line 2600 on the oxide layer, and is connected to a conductive via array 2610 within the array of conductive vias 2610. Corresponding conductive vias 2610 are connected to obtain the structures shown in FIGS. 26A-26D .

The overall word line 2600 extends to peripheral circuitry 2620 comprising a CMOS device as shown in the top view of FIG. 26A and the cross-sectional views of FIGS. 26B-26D .

FIG. 27 shows an alternative embodiment of FIG. 20 for forming the bottom electrode, which shows forming the bottom electrode 410 with a ring-shaped top surface.

In FIG. 27, a bottom electrode material is formed over the structure shown in FIGS. 19A-19D within the opening 1900 defined by the dielectric spacer 140, using a process that does not completely fill the opening 1900. . A fill material is then formed on the bottom electrode material to fill the opening, and the structure is planarized (eg, using CMP), thereby forming the bottom electrode 410, as shown in FIGS. 27A-27D. Each bottom electrode 410 has an inner surface 165 defining an inner region containing fill material 172 .

28-29 illustrate alternative fabrication techniques to that of FIGS. 21-24.

A plurality of strips of storage material 150 and bit lines on the corresponding storage materials are formed on the structure shown in FIGS. 20A to 20D to obtain the top view of FIG. structure. The storage material strip 150 and the bit line 120 can be formed by forming a storage material on the structure shown in FIG. 20A to FIG. A photoresist layer is patterned on the material layer, and then the bit line material layer and the storage material layer are etched by using the patterned photoresist as an etching mask. The formation of the bit lines 120 and the strips of memory material 150 exposes the top surfaces of the plurality of dielectric-filled trenches 800 .

Next, a first dielectric layer 2900 is formed on the bit line 120 , on the sidewall surfaces of the memory material strip 150 and on the exposed top surfaces of the plurality of dielectric-filled second trenches 800 . A second dielectric layer 2910 is formed on the first dielectric layer 2900, and a planarization process (such as CMP) is performed to expose the top surface of the bit line 120, thereby obtaining the top view of FIG. 29A and the top view of FIG. 29B to FIG. The structure shown in the cross-sectional view of 29D. In the illustrated embodiment, the first dielectric layer 2900 includes silicon nitride, and the second dielectric layer 2910 includes silicon dioxide.

Figure 30 is a simplified block diagram of integrated circuit 10 in one embodiment. The integrated circuit 10 includes a cross-point memory array memory array 100 of memory cells utilizing self-aligned bottom electrodes and diode access devices as described in the present invention. A word line decoder 14 is coupled and electrically connected to a plurality of word lines 16, and a bit line (row) decoder 18 is electrically connected to a plurality of bit lines 20 for changing the phase in the memory array 100. The storage unit (not shown) reads data and writes data. Addresses are supplied to word line decoder and driver 14 and bit line decoder 18 via bus 22 . The sense amplifier and data input structures in block 24 are coupled to bit line decoder 18 via data bus 26 . Data is transferred to the data-in structure of block 24 via data-in lines 28 from input/output terminals of integrated circuit 10 , or other data sources internal or external to integrated circuit 10 . Other circuits 30 are included on the integrated circuit 10, such as general purpose processors or special purpose application circuits, or a combination of modules that can provide SoC functionality (supported by a phase-change memory cell array). Data is output from the sense amplifiers in block 24 via data output lines 32 to input/output terminals of the integrated circuit 10 , or to other data destinations internal or external to the integrated circuit 10 .

The controller 34 used in this embodiment uses the bias adjustment state mechanism 36 and controls the application of the bias adjustment supply voltage and current source, such as read, program, erase, erase verify and program verify Voltage. The controller 34 may be implemented using special purpose logic circuitry, as is known to those skilled in the art. In an alternative embodiment, the controller 34 includes a general purpose processor, which can be used on the same integrated circuit to execute a computer program to control the operation of the device. In yet another embodiment, the controller 34 is a combination of special purpose logic and a general purpose processor.

Embodiments of memory cells described herein include phase change memory materials, including chalcogenide materials and others. Chalcogenides include any of the following four elements: oxygen (O), sulfur (S), selenium (Se), and tellurium (Te), forming part of Group VIA on the periodic table. Chalcogenides include the combination of a chalcogen element with a more electropositive element or free radical. Chalcogenide alloys include combining chalcogenides with other substances such as transition metals and the like. A chalcogenide alloy usually includes one or more elements selected from group IVA of the periodic table, such as germanium (Ge) and tin (Sn). Typically, chalcogenide alloys include complexes of one or more of the following elements: antimony (Sb), gallium (Ga), indium (In), and silver (Ag). A number of phase change based memory materials have been described in technical documents, including the following alloys: Ga/Sb, In/Sb, In/Se, Sb/Te, Ge/Te, Ge/Sb/Te, In/Sb /tellurium, gallium/selenium/tellurium, tin/antimony/tellurium, indium/antimony/germanium, silver/indium/antimony/tellurium, germanium/tin/antimony/tellurium, germanium/antimony/selenium/tellurium, and tellurium/germanium/ Antimony/Sulphur. Within the germanium/antimony/tellurium alloy family, a wide range of alloy compositions can be tried. This composition can be represented by the following characteristic formula: Te _a Ge _b Sb _100-(a+b) , where a and b represent the percentage of each atom when the total number of atoms of the constituent elements is 100%. One researcher described the most useful alloy systems as containing an average tellurium concentration in the deposited material well below 70%, typically below 60%, and in general type alloys ranging from the lowest 23% up to 58%, and optimally a tellurium content between 48% and 58%. The concentration of germanium is above about 5%, and its average range in the material is from a minimum of 8% to a maximum of 30%, generally below 50%. Optimally, the germanium concentration ranges from 8% to 40%. The remaining major component in this composition is antimony. (Ovshinky '112 patent, _{columns 10-11} ) Specific alloys evaluated by another investigator include _{Ge2Sb2Te5 , GeSb2Te4} , and _{GeSb4Te7 .} (Noboru Yamada, "Potential of Ge-Sb-Te Phase-change Optical Disks for High-Data-Rate Recording", SPIEv.3109, pp.28-37(1997)) More generally, transition metals such as chromium (Cr), Iron (Fe), nickel (Ni), niobium (Nb), palladium (Pd), platinum (Pt), and mixtures or alloys thereof, can be combined with germanium/antimony/tellurium to form a phase change alloy which includes programmed resistive nature. Specific examples of memory materials that may be used are described, for example, at columns 11-13 of the Ovshinsky '112 patent, examples of which are incorporated herein by reference.

In some embodiments, chalcogenides and other phase change materials are doped with impurities to modify conductivity, transition temperature, melting point, and other properties used in doped chalcogenide memory devices. Representative impurities used in doping chalcogenides include nitrogen, silicon, oxygen, silicon dioxide, silicon nitride, copper, silver, gold, aluminum, aluminum oxide, tantalum, tantalum oxide, tantalum nitride, titanium, titanium oxide . See US Patent No. 6,800,504 and US Patent Application No. 2005/0029502.

The phase change alloy can be switched between a first structural state in which the material is generally amorphous and a second structural state in which the material is generally crystalline solid, according to its position sequence in the active channel region of the unit. These materials are at least bistable. The term "amorphous" is used to refer to a relatively disordered structure, which is more disordered than a single crystal, with detectable characteristics such as higher electrical resistance than the crystalline state. The term "crystalline state" is used to refer to a relatively ordered structure that is more ordered than the amorphous state and thus includes detectable characteristics such as lower electrical resistance than the amorphous state. Typically, phase change materials are electrically switchable to all detectably different states between fully crystalline and fully amorphous. Other material properties affected by changes in amorphous and crystalline states include atomic order, free electron density, and activation energy. This material can be switched into different solid states, or can be switched into a mixture of two or more solid states, providing a gray scale part between the amorphous state and the crystalline state. Electrical properties in the material may also change accordingly.

Phase change alloys can be switched from one phase state to another by applying an electrical pulse. Previous observations indicate that a shorter, higher amplitude pulse tends to change the phase state of the phase-switching material to a substantially amorphous state. A longer, lower amplitude pulse tends to change the phase state of the phase transition material to a substantially crystalline state. The energy in the shorter, larger-amplitude pulse is large enough to break the bond energy of the crystalline structure, but short enough to prevent the atoms from rearranging into a crystalline state. Appropriate curves are based on experience or simulations, especially for a particular phase change alloy. The phase change material disclosed herein is generally referred to as GST, it is understood that other types of phase change materials may be used. The phase change read only memory (PCRAM) used in the present invention is Ge ₂ Sb ₂ Te ₅ .

Other programmable memory materials _that can be used in other _embodiments of the present invention include _{N2 -} doped GST, _GexSby , or other substances that determine resistance by switching between different crystalline states; _PrxCayMnO3 , Pr _{x Sry} MnO ₃ , ZrO _x or other materials that use electric pulses to change the state of resistance; or other substances that use an electric pulse to change the state of resistance; TCNQ (7,7,8,8-tetracyanoquinodimethylthane), PCBM (methanofullerene6, 6-phenyl C61-butyric acid methyl ester), TCNQ-PCBM, Cu-TCNQ, Ag-TCNQ, C60-TCNQ, TCNQ doped with other substances, or any other polymer material which includes control with an electric pulse bistable or multistable resistive states.

An exemplary method of forming chalcogenides may utilize PVD sputtering or magnetron (Magnetron) sputtering, the reaction gas is argon, nitrogen, and/or helium, and the pressure is 1 mTorr to 100 mTorr. This deposition step is generally performed at room temperature. A collimater with an aspect ratio of 1-5 can be used to improve the injection performance. In order to improve its injection performance, a DC bias voltage of tens to hundreds of volts can also be used. On the other hand, it is also possible to combine the use of DC bias and collimator at the same time.

Sometimes a post-deposition annealing treatment in vacuum or nitrogen atmosphere is required to improve the crystallinity of the chalcogenide material. The annealing temperature is typically between 100°C and 400°C, and the annealing time is less than 30 minutes.

The thickness of the chalcogenide material depends on the design of the cell structure. In general, chalcogenides with a thickness greater than 8 nm may have phase change properties such that the material exhibits at least a bistable resistance state. It is contemplated that certain materials are also suitable for thinner thicknesses.

While the present invention has been described with reference to preferred embodiments, it will be understood that the inventive concept is not limited to the detailed description. Alternatives and modifications have been suggested in the preceding description, and other alternatives and modifications will occur to those skilled in the art. Combinations of the components of the present invention to achieve substantially the same results as the present invention will not depart from the scope defined by the claims of the present invention.

Claims (22)

1. A storage device, characterized in that it comprises: A plurality of word lines extend to a first direction; a plurality of bit lines extending over the word line in a second direction, the bit line intersecting the word line at an intersection position; and A plurality of storage units are located at the intersection, where each storage unit includes: a diode having first and second sides aligned to a side of a corresponding one of the plurality of word lines, the diode having a top surface; a bottom electrode is self-centered in the diode, the bottom electrode has a top surface, and the top surface has a surface area that is less than the surface area of the top surface of the diode; and A strip of storage material is on the top surface of the bottom electrode, the strip of storage material is under and electrically connected to a corresponding bit line of the plurality of bit lines. 2. The device of claim 1, wherein the diode of each memory cell comprises a stack comprising: a first doped semiconductor region having a first conductivity type on the corresponding word line; a second doped semiconductor region having a second conductivity type opposite to the first conductivity type, the second doped semiconductor region overlying the first doped semiconductor region and defining therebetween a pn junction; and A conductive covering layer is on the second doped semiconductor region. 3. The device according to claim 2, characterized in that: The first doped semiconductor region of each memory cell includes n-type doped semiconductor material; the second doped semiconductor region of each memory cell comprises a p-type doped semiconductor material; and The conductive capping layer of each memory cell includes a silicide. 4. The device according to claim 3, wherein the plurality of word lines comprise n-type doped semiconductor material having a doping concentration higher than that of the first doped semiconductor region of each memory cell. 5. The device of claim 1, wherein the bottom electrode of each memory cell has an outer surface, and each memory cell further comprises a dielectric spacer on the outer surface of the bottom electrode , and have sides aligned with the sides of the diode. 6. The device according to claim 5, wherein the bottom electrode of each memory cell has an inner surface such that the top surface of the bottom electrode has a ring shape, and each memory cell further comprises a filling material In the inner region defined by the inner surface of the bottom electrode. 7. The device according to claim 1, wherein the bottom electrode of each memory cell comprises: a first conductive element having sides aligned with the side of the diode and having a width the same as the side of the diode; and A second conductive element is self-centered on the first conductive element and has a width smaller than the width of the first conductive element. 8. The device according to claim 1, characterized in that: The word line has a word line width and is separated from adjacent word lines by a word line separation distance; The bitline has a bitline width and is separated from adjacent bitlines by a bitline separation distance; and Each of the memory cells in the plurality of memory cells has a memory cell area having a first side along the first direction and a second side along the second direction, the first The side has a length equal to the sum of the bit line width and the bit line separation distance, and the second side has a length equal to the sum of the word line width and the word line separation distance. 9. A method of manufacturing a storage device, characterized in that the method comprises: forming a plurality of word lines extending in a first direction; forming a plurality of bit lines on the word line and extending in a second direction, the plurality of bit lines and the plurality of word lines intersect at a plurality of intersection positions; and forming a plurality of storage units at the plurality of intersection positions, wherein each storage unit includes: a diode having first and second sides aligned to a side of a corresponding one of the plurality of word lines, the diode having a top surface; a bottom electrode is self-centered in the diode, the bottom electrode has a top surface, and the top surface has a surface area that is less than the surface area of the top surface of the diode; and A strip of storage material is on the top surface of the bottom electrode, the strip of storage material is under and electrically connected to a corresponding bit line of the plurality of bit lines. 10. The method of claim 9, wherein the diode of each memory cell comprises a stack comprising: a first doped semiconductor region having a first conductivity type on the corresponding word line; a second doped semiconductor region having a second conductivity type opposite to the first conductivity type, the second doped semiconductor region overlying the first doped semiconductor region and defining a pn junction therebetween; as well as A conductive covering layer is on the second doped semiconductor region. 11. The method of claim 10, wherein: The first doped semiconductor region of each memory cell includes n-type doped semiconductor material; the second doped semiconductor region of each memory cell comprises a p-type doped semiconductor material; and The conductive capping layer of each memory cell includes a silicide. 12. The method of claim 11, wherein the plurality of word lines comprise an n-type doped semiconductor material that is more highly doped in the first doped semiconductor of each memory cell. 13. The method of claim 9, wherein the bottom electrode of each memory cell has an outer surface, and each memory cell further comprises a dielectric spacer on the outer surface of the bottom electrode , and have sides aligned with the sides of the diode. 14. The method according to claim 13, wherein the bottom electrode of each memory cell has an inner surface such that the top surface of the bottom electrode has a ring shape, and each memory cell further comprises a filling material In the inner region defined by the inner surface of the bottom electrode. 15. The method of claim 9, wherein the bottom electrode of each memory cell comprises: a first conductive element having sides aligned with the side of the diode and having a width the same as the side of the diode; and A second conductive element is self-centered on the first conductive element and has a width smaller than the width of the first conductive element. 16. The method of claim 9, wherein: The word line has a word line width and is separated from adjacent word lines by a word line separation distance; The bitline has a bitline width and is separated from adjacent bitlines by a bitline separation distance; and Each of the memory cells in the plurality of memory cells has a memory cell area having a first side along the first direction and a second side along the second direction, the first The side has a length equal to the sum of the bit line width and the bit line separation distance, and the second side has a length equal to the sum of the word line width and the word line separation distance. 17. A method for manufacturing a memory device, the method comprising: forming a structure comprising a wordline material, a diode material on the wordline material, a first material on the diode material, and a second material on the first material layer; forming a plurality of dielectric filled first trenches in the structure and extending in a first direction to define a plurality of strips of memory material, each comprising a word line comprising word line material; forming a plurality of dielectric filled second trenches under the word line and extending into a second direction to define a plurality of stacks, each stack comprising (a) a diode comprising the diode material in a corresponding word line and having a top surface, (b) a first element comprising a first material over the diode, (c) a second element comprising a second material over the first element; forming bottom electrodes on a corresponding diode of the first element and the second element using the stack; and A strip of memory material is formed on the top surface of the top electrode, and a bit line is formed on the strip of memory material. 18. The method of claim 17, further comprising: forming an oxide layer on the bit line; forming an array of conductive vias extending through the oxide layer to connect a corresponding word line; A plurality of integral word lines are formed on the oxide layer and connected with corresponding conductive vias in the conductive via array. 19. The method according to claim 17, wherein the step of forming a strip of storage material and forming a bit line on the strip of storage material comprises: forming a storage material over the top surface of the bottom electrode; forming bit line material over the memory material; patterning the storage material and the bitline material to expose top surfaces of the plurality of dielectric-filled second trenches; forming a first layer of dielectric material over the bit line, over sidewall surfaces of the memory material strips, and over the exposed top surfaces of the plurality of dielectric-filled second trenches; forming a second dielectric layer over the first dielectric layer; and A planarization step is performed to expose the top surface of the bitline. 20. The method according to claim 17, wherein the step of forming the storage material strip and the bit line on the storage material strip comprises: forming strips of sacrificial material extending to a second direction and contacting the top surfaces of the plurality of bottom electrodes; forming strips of dielectric material between the strips of sacrificial material; removing the strips of sacrificial material to expose the top surface of the bottom electrode and defining trenches between the strips of memory material; forming a strip of memory material in the trench to connect the top surface of the bottom electrode; and Bit lines are formed on the strip of memory material. 21. The method of claim 17, wherein forming a plurality of bottom electrodes comprises: removing material downward from the plurality of dielectric-filled first and second trenches to expose sidewall surfaces of the second element; reducing the width of the second element; etching the first element using the reduced width second element as an etch mask, thereby forming a bottom electrode comprising the first element material and defining an opening surrounding the bottom electrode; and A dielectric spacer is formed within the opening. 22. The method according to claim 17, wherein the step of forming a plurality of bottom electrodes comprises: removing the second element to form a dielectric via over the first element; forming sidewall spacers within the via; etching the first feature using the sidewall spacers as an etch mask, thereby forming dielectric spacers comprising the first material and defining openings; forming bottom electrode material within the opening defined by the dielectric spacer using a process that does not completely fill the opening; forming a dielectric fill material over the bottom electrode material to fill the opening defined by the dielectric spacers; and performing a planarization process to remove the sidewall surfaces, thereby forming the plurality of bottom electrodes, each bottom electrode having an inner surface such that the top surface of the bottom electrode has a ring shape, the dielectric filling material formed from the The inner region defined by the inner surface of the bottom electrode.

Images