CN102013271B - Fast reading device and method of phase change memory - Google Patents

Abstract

A fast reading device for phase-change memory, which includes a phase-change memory unit to be read, a charging circuit, an overshoot recovery rate detection circuit, a sensitive amplifier circuit, and a reference level or a reference memory unit. On the one hand, the phase-change memory unit (which can be abstracted as a resistor in the circuit) and the parasitic capacitance of the bit line form an RC loop; on the other hand, the gate MOS transistor enters the linear region from the saturation region at the moment of switching, which will cause an overshoot phenomenon . Phase-change resistors in different states have different recovery rates after overshoot. The method quickly reads the state of the phase-change memory unit by reading the recovery rate of the bit line level after the overshoot, thereby accelerating the overall read rate of the memory. In addition, fast reading is helpful to avoid damage to the phase change unit by the reading operation, so as to achieve the purpose of reducing read disturbance.

Description

A fast reading device and method for phase change memory

technical field

The invention relates to the technical field of micro-nano electronics, in particular to a novel fast reading method of a phase-change memory.

Background technique

Phase change memory technology is based on Ovshinsky's proposal in the late 1960s (Phys. Rev. Lett., 21, 1450-1453, 1968) and early 1970s (Appl. Phys. Lett., 18, 254-257, 1971) The idea that the phase change film can be applied to the phase change storage medium is established, and it is a storage device with low price and stable performance. Phase-change memory can be made on a silicon wafer substrate, and its key materials are recordable phase-change films, heating electrode materials, heat-insulating materials, and lead-out electrode materials. Including how to reduce device material and so on. The basic principle of phase change memory is to use electric pulse signal to act on the device unit, so that the phase change material undergoes reversible phase transition between amorphous state and polycrystalline state. By distinguishing the high resistance in the amorphous state and the polycrystalline state The low resistance can realize the writing, erasing and reading operations of information.

Due to the advantages of high-speed reading, high rewritable times, non-volatility, small component size, low power consumption, strong vibration resistance and radiation resistance, phase change memory is considered by the International Semiconductor Industry Association to be the most likely to replace the current flash memory Memory becomes the mainstream product of future memory and the first device to become a commercial product.

The read, write, and erase operations of phase change memory are to apply voltage or current pulse signals of different widths and heights on the device unit: erase operation (RESET), when a short and strong pulse signal is added to make the phase change material in the device unit After the temperature rises above the melting temperature, it undergoes rapid cooling to realize the transition from the polycrystalline state to the amorphous state of the phase change material, that is, the transition from the "1" state to the "0" state; when a write operation (SET) is applied, a A long and medium-intensity pulse signal raises the temperature of the phase change material below the melting temperature and above the crystallization temperature, and maintains it for a period of time to promote the growth of the crystal nucleus, thereby realizing the transformation from the amorphous state to the polycrystalline state, that is, "0" state to "1" state conversion; read operation, when a very weak pulse signal that does not affect the state of the phase change material is applied, its state is read by measuring the resistance value of the device unit.

Although phase-change memory has great application prospects and has attracted extensive attention from the industry, there are still several key technical points that have not been well resolved. One of them is the read problem. The reading process of phase-change memory can generally be divided into two parts: pre-charging and level-amplification. The pre-charging part sends current (voltage) pulses to the phase change memory unit, so that the bit line voltage (current) rises, and the rising speed is affected by the parasitic capacitance and the resistance value of the phase change unit itself. When it rises to a certain value, the amplified level part amplifies the bit line level to the full scale signal output through the sense amplifier. This process must be destructive to the phase change unit itself, and the state of the phase change unit will definitely be affected after multiple reads. To minimize disruption, current circuit designs have to rely on sacrificing read margin. Secondly, the larger parasitic capacitance of the bit line makes the reading speed slower, which hinders the application of the phase change memory.

In view of this, it is necessary to design a new device and method to quickly read phase change memory.

Contents of the invention

The technical problem to be solved by the present invention is to provide a fast reading device and method for a phase change memory. On the one hand, the impact of the read operation on the phase change unit is minimized without sacrificing the read margin; on the other hand, On the one hand, under the premise of considering the parasitic capacitance of the bit line, the reading speed is greatly improved.

In order to solve the above problems, the present invention adopts the following technical solutions:

A fast reading device for a phase-change memory unit, characterized in that the device includes a phase-change memory unit to be read, a

The charging circuit is used to send a fixed current pulse to the phase-change memory cell to be read or maintain the voltage of the bit line to a fixed level;

An overshoot recovery rate detection circuit connected to the phase-change memory unit to be read is used to read the recovery rate of the bit line level of the phase-change memory unit to be read and output it in the form of a level;

The pull-down bit line circuit connected to the phase-change memory unit to be read is used to quickly pull down the bit-line circuit after the read operation is completed, so that the phase-change memory unit to be read performs the next read and write operation;

A sensitive amplifier circuit connected to the output terminal of the overshoot recovery rate detection circuit, the sensitive amplifier circuit includes at least two input terminals, one input terminal is connected to the output terminal of the overshoot recovery rate detection circuit, and the other input terminal is connected to the reference level Or the reference storage unit is connected to compare the signal magnitudes of the two input terminals and amplify and output the comparison result;

A latch circuit connected to the output of the sensitive amplifier circuit is used to lock the correct reading result into the latch when the overshoot recovery process is not over, so as to be used by the lower circuit;

The latch control signal generating circuit connected with the latch circuit is used for generating a signal to control the latch circuit.

The present invention also relates to a reading method of a fast reading device for a phase-change memory unit, which is characterized in that the method includes the following steps:

1) Utilize the overshoot recovery rate detection circuit to read the recovery rate after the overshoot of the phase-change memory unit to be read;

2) comparing the recovery rate with the recovery rate or reference level of the set reference storage unit;

3) If the output level of the overshoot recovery rate detection circuit is greater than the reference level or the level of the reference storage unit, the sensitive amplifier circuit outputs a high-level signal, then the phase-change storage unit to be read is in a high-impedance state. If the output level of the impulse recovery rate detection circuit is lower than the reference level or the level of the reference storage unit, the sensitive amplifying circuit outputs a low-level signal, and the phase-change storage unit to be read is in a low-impedance state;

4) The latch circuit latches the high-level signal or the low-level signal output by the sensitive amplifier circuit before the overshoot recovery phenomenon ends.

The method quickly reads the state of the phase-change memory unit through the recovery rate of the bit line level after the read overshoot, thereby accelerating the overall read rate of the memory. In addition, fast reading is helpful to avoid damage to the phase change unit by the reading operation, so as to achieve the purpose of reducing read disturbance.

Description of drawings:

Fig. 1 is a schematic structural diagram of a phase-change memory cell to be read in the present invention;

Fig. 2 is a kind of structural schematic diagram of phase-change memory fast reading device of the present invention;

Fig. 3 is a kind of possible circuit diagram of charging circuit among the present invention;

Fig. 4 is a possible circuit schematic diagram of the overshoot recovery rate detection circuit in the present invention;

Fig. 5 is a possible circuit schematic diagram of the low bit line circuit in the present invention;

Fig. 6 is a possible circuit schematic diagram of the latch control signal generating circuit in the present invention;

Fig. 7 is the result figure that utilizes industry standard simulation software Specter simulation gained in the present invention;

FIG. 8 is a schematic diagram of a reference memory cell circuit in the present invention;

FIG. 9 is another structural schematic diagram of a fast reading device for a phase change memory according to the present invention;

Fig. 10 is a possible schematic circuit diagram of the latch circuit in the present invention;

Fig. 11 is a possible circuit schematic diagram of the sensitive amplifier circuit in the present invention.

Detailed ways

Example 1

Referring to Fig. 2, the present invention provides a fast reading device for phase-change memory, which includes a phase-change memory unit 104 to be read, and a charging circuit 101 connected to the phase-change memory unit 104 to be read, for sending fixed Current pulses to the phase-change memory cell to be read 104 or keep the bit line voltage to a fixed level; the overshoot recovery rate detection circuit 102 connected to the phase-change memory cell to be read is used to read the bit line of the phase-change memory cell to be read The recovery rate of the level is output in the form of a level; the pull-down bit line circuit 106 connected with the phase-change memory unit to be read is used to quickly pull down the bit-line circuit after the read operation is completed, so that the phase-change memory unit to be read is Next read and write operation; the sensitive amplifying circuit 103 that is connected with the output terminal of overshoot recovery rate detection circuit 102, described sensitive amplifying circuit 103 includes two input terminals at least, one input terminal and overshoot recovery rate detection circuit 102 output terminals The other input terminal is connected to the reference level, and is used to compare the signals of the two input terminals and amplifies and outputs the comparison result; the latch circuit 107 connected to the output terminal of the sensitive amplifier circuit 103 is used for the overshoot recovery process. At the end, the correct reading result is locked into the latch for use by the lower circuit; the latch control signal generating circuit 108 connected to the latch circuit 107 is used to generate a signal to control the latch circuit.

FIG. 1 shows a phase-change memory cell 104, including a gate MOS transistor 202 and a phase-change memory material 201. One end of 201 is connected to the drain end of 202, and the other end is a bit line. The gate terminal of 202 is a word line.

Figure 2 provides a new type of phase-change memory fast read circuit. It includes a charging circuit 101 , an overshoot recovery rate detection circuit 102 , a sense amplifier circuit 103 , a phase-change storage unit to be tested 104 , a pull-down bit line circuit 106 , a latch circuit 107 , and a latch control signal generation circuit 108 . One end of the sense amplifier circuit 103 is connected to the overshoot recovery rate detection circuit 102, and the other end is connected to a reference level. If the phase-change memory unit 104 to be tested is in a high-impedance state, the output level of the overshoot recovery rate detection circuit 102 is greater than the reference level, the sense amplifier circuit 103 outputs a high-level signal, and the latch circuit 107 is in the overshoot recovery phenomenon. Latch the high-level signal before the end; if the phase-change memory unit 104 to be tested is in a low-impedance state, the output level of the overshoot recovery rate detection circuit 102 is less than the reference level, and the sensitive amplifier circuit 103 outputs a low-level signal, The latch circuit 107 latches the low-level signal before the overshoot recovery phenomenon ends.

The charging circuit includes sending a fixed current pulse to the phase-change memory cell to be tested or maintaining the voltage of the bit line to a fixed level. FIG. 3 is a possible circuit form of the charging circuit 101 . A set of current mirrors is formed by the PMOS transistors 204 and 205 and the current source 206 . The NMOS transistor 203 is used as a gate transistor, its drain end is connected to the drain end of the PMOS transistor 205 , its source end is connected to the bit line of the phase change unit 104 to be tested, and its gate end is connected to the read enable signal.

When the read enable is at low level, the source level of the gate transistor 203 is floating or grounded, and the drain level is connected to VDD, which should be VDD. At the moment when the read enable signal changes from low level to high level, the level of its gate terminal rises beyond the threshold voltage. In this case, since the level of the drain terminal is at the highest level, the gate tube 203 is forced to enter the saturation region. In this way, a relatively large current in the saturation region will flow through the gate transistor 203, and this current will cause an upward overshoot phenomenon of the bit line level. When the path between the gate transistor 203 and the ground is opened, the level of the drain terminal will drop, and finally the gate transistor 203 enters the linear region, so that the current flowing through the gate transistor 203 becomes smaller, and the overshoot phenomenon recovers.

The overshoot recovery rate detection circuit may be a differential circuit composed of an operational amplifier, a resistor, and a capacitor. It can also be other circuit forms with detection level or current slope. As shown in Figure 4, due to the "virtual short, virtual break" characteristic of an ideal operational amplifier, V1=V2=0. Then the current flowing through the resistor 207 must be equal to the current flowing through the capacitor 210 . According to the capacitance charge and discharge formula.

$\frac{{\mathrm{<span\; class="notranslate">\; u</span>}}_{\mathrm{<span\; class="notranslate">\; o</span>}}}{\mathrm{<span\; class="notranslate">\; R</span>}}<span\; class="notranslate">\; =</span>{\mathrm{<span\; class="notranslate">\; i</span>}}_{\mathrm{<span\; class="notranslate">\; R</span>}}<span\; class="notranslate">\; =</span><span\; class="notranslate">\; -</span>{\mathrm{<span\; class="notranslate">\; i</span>}}_{\mathrm{<span\; class="notranslate">\; c</span>}}<span\; class="notranslate">\; =</span><span\; class="notranslate">\; -</span>\mathrm{<span\; class="notranslate">\; C</span>}\frac{{\mathrm{<span\; class="notranslate">\; du</span>}}_{\mathrm{<span\; class="notranslate">\; I</span>}}}{\mathrm{<span\; class="notranslate">\; dt</span>}}$

${\mathrm{<span\; class="notranslate">\; u</span>}}_{\mathrm{<span\; class="notranslate">\; o</span>}}<span\; class="notranslate">\; =</span><span\; class="notranslate">\; -</span>\mathrm{<span\; class="notranslate">\; RC</span>}\frac{{\mathrm{<span\; class="notranslate">\; du</span>}}_{\mathrm{<span\; class="notranslate">\; I</span>}}}{\mathrm{<span\; class="notranslate">\; dt</span>}}$

Among them, u ₀ is the voltage, R is the resistance, i _R is the current flowing through the resistance R, and i _C is the current of the capacitor C. According to the above formula, the output voltage of the overshoot recovery rate detection circuit 102 is the slope value of the input voltage versus time.

FIG. 4 shows a possible circuit form 102 of the overshoot recovery rate detection circuit, including a capacitor 210 , resistors 207 and 209 , and an operational amplifier circuit 208 . Since capacitors, resistors and operational amplifiers are circuit forms well known in the art, no further description is given here. The essence of the overshoot recovery rate detection circuit 102 is a differential circuit, the principle of which is well known to those skilled in the art and will not be repeated here.

FIG. 5 is a possible circuit form of the pull-down bit line circuit. The bit line pull down circuit 106 uses an NMOS transistor as the bit line pull down circuit. The source end of the NMOS is grounded, the gate end is a pull-down control signal, and the drain end is connected to a bit line. Once the pull-low control signal is high, the NMOS transistor can directly ground the bit line.

The latch control signal generating circuit includes a delay circuit module capable of adjusting delay time. Its input signal is a read enable signal, and its output signal is a latch control signal. By adjusting the delay time, the entire readout method can be adapted to different process conditions. FIG. 6 is a possible circuit form of the latch control signal generating circuit 108, which includes a plurality of delay circuits 211 and a multiplexer 212 connected in sequence. The latch control signal generation circuit 108 delays the read enable signal to generate the latch control signal. The delay time is adjusted through the multiplexer 212 to adapt to different process conditions.

Figure 10 is a possible circuit structure of the latch circuit in the present invention, which is used to lock the correct reading result into the latch when the overshoot recovery process has not ended, so as to be used by the lower circuit, when the G terminal When it is at a high level, Q=D, QN=-D; when the G terminal is at a low level, Q and QN maintain the original state to realize latching.

A sense amplifier circuit that compares signals at two inputs and amplifies the output of the comparison. It can be a current type comparison circuit or a voltage type comparison circuit. Fig. 11 is a kind of possible circuit structure of sense amplifier circuit 103 in the present invention, if the level of BIT# is higher than BIT, because the current mirror action of M3 and M4, the current flowing through M4 will be greater than the current of M2, DATA # The parasitic capacitance of the node is the charging state, the level rises to the high level; and vice versa.

Fig. 7 is the simulation result obtained by using the industry standard simulation software Specter. As can be seen from the figure, during the overshoot recovery process, the level difference of the bit line is only 0.1v, but after the overshoot recovery detection circuit, the level difference has reached more than 1.3v.

Example 2

Please refer to Fig. 9, the present invention provides a fast reading device for phase-change memory, which includes a phase-change memory unit 104 to be read, a charging circuit 101 connected to the phase-change memory unit 104 to be read, for sending fixed The current pulse is sent to the phase-change memory cell 104 to be read or the voltage of the bit line is kept to a fixed level; the overshoot recovery rate detection circuit 102 connected with the phase-change memory cell to be read is used to read the phase-change state to be read in the form of a current slope The recovery rate of the bit line level of the memory cell is output in the form of a level; the pull-down bit line circuit 106 connected with the phase-change memory cell to be read is used to quickly pull down the bit line circuit after completing the read operation, so that the read-out The phase-change memory unit carries out the next read and write operation; the sensitive amplifying circuit 103 that is connected with the output end of the overshoot recovery rate detection circuit 102, and the described sensitive amplifying circuit 103 includes two at least input terminals, one input terminal and the overshoot recovery rate The detection circuit 102 output terminal is connected, and the other input terminal is connected with the reference level, is used for comparing the signal of two input terminals and amplifies and outputs the comparison result; The latch circuit 107 connected with the output terminal of the sensitive amplifier circuit 103 is used for When the recovery process is not over, the correct reading result is locked into the latch for use by the lower circuit; the latch control signal generating circuit 108 connected with the latch circuit 107 is used to generate the signal control latch circuit.

Described reference phase-change memory unit comprises reference phase-change memory 105, the charging circuit 101 that is connected with reference phase-change memory 105, is used for sending fixed current pulse to reference phase-change memory or keeps bit line voltage to fixed level; The overshoot recovery rate detection circuit 102 connected to the phase-change memory is used to detect and output the level or current slope; the pull-down bit line circuit 106 connected to the reference phase-change memory is used to quickly pull down the bit line circuit after the read operation is completed , so that the reference phase change memory performs the next read and write operation, and the output end of the overshoot recovery rate detection circuit 102 is connected to the input end of the sensitive amplifier circuit 103 .

Example 3

A fast reading device for phase-change memory, which can compare the recovery rate with a set reference level to determine the state of the phase-change memory unit; it can also compare the recovery rates of two memory units with similar structures, One of them is a memory cell that determines the state, thereby determining the state of the other phase change memory cell. Two memory cells of similar structure, one of which is a phase-change memory cell to be read; the other can be

b) a resistor with a fixed resistance;

c) A phase-change memory cell whose state can be determined;

d) A phase-change memory cell with an undeterminable state.

The present invention also relates to a reading method of a fast reading device for a phase-change memory unit, which is characterized in that the method includes the following steps:

1) Utilize the overshoot recovery rate detection circuit to read the recovery rate after the overshoot of the phase-change memory unit to be read;

In the actual process of reading phase-change memory, because the moment when the bit line gating MOS transistor is turned on, it will go through the process from the saturation region to the linear region, resulting in the level of the bit line at the moment of turning on will exceed the read level in the steady state value. Therefore, the bit line level must experience a process from overshoot to recovery. According to the RC charge and discharge theory, in the case of a certain bit line capacitance, if the resistance of the phase-change memory unit (which can be abstracted as a resistor) is large, the recovery of the bit line will be slow. If the resistance is very large, it may even cause overshoot If the level is still lower than the read level value in a stable state, the bit line level continues to rise; if the resistance value is small, the bit line level recovers quickly. Therefore, by reading the recovery rate of the bit line level after the overshoot, the resistance value of the phase-change memory cell can be judged, thereby realizing the read operation.

2) comparing the recovery rate with the recovery rate or reference level of the set reference storage unit;

3) If the output level of the overshoot recovery rate detection circuit is greater than the reference level or the level of the reference storage unit, the sensitive amplifier circuit outputs a high-level signal, then the phase-change storage unit to be read is in a high-impedance state. If the output level of the impulse recovery rate detection circuit is lower than the reference level or the level of the reference storage unit, the sensitive amplifying circuit outputs a low-level signal, and the phase-change storage unit to be read is in a low-impedance state;

4) The latch circuit latches the high-level signal or the low-level signal output by the sensitive amplifier circuit before the overshoot recovery phenomenon ends.

The state of the phase-change memory cell can only be judged when the level of the bit line changes (the overshoot recovery phenomenon still exists). If the level of the bit line is stable, the overshoot recovery rate detection circuit will not be able to distinguish the phase-change memory cells in different states. Therefore, a latch technology must be used to latch the read signal before the overshoot recovery phenomenon ends.

Principle of the present invention is as follows:

1) RC loop formed by phase change resistance and bit line capacitance;

2) The strobe MOS tube enters the linear region from the saturation region at the moment of switching, resulting in overshoot;

3) After overshoot, phase change resistors in different states have different recovery rates after overshoot;

According to these three characteristics, the state of the phase-change memory cell is read by reading the recovery rate of the bit line level (current) after the overshoot.

First, the bit line gating MOS transistor is turned on, so that the read current (voltage) enters the phase-change memory cell. When the gate MOS transistor (assumed to be NMOS) is not turned on, its source level is floating or grounded, and its drain level is connected to VDD, which should be VDD. During the turn-on process, the gate level rises above the threshold voltage. In this case, since the drain level is at the highest level, the gate MOS is forced into the saturation region. In this way, a relatively large current in the saturation region will flow through the gate MOS transistor, and this current will cause an upward overshoot phenomenon in the level of the bit line. When the path between the gate MOS transistor and the ground is opened, the level of the drain terminal will drop, and finally the MOS transistor enters the linear region, so that the current flowing through the gate MOS transistor becomes smaller, and the overshoot phenomenon recovers. In this process, if the resistance of the phase change unit is small, the overshoot recovery will be faster; if the resistance is large, the overshoot recovery will be slow; if the resistance is very large, the path between the drain terminal of the MOS transistor and the ground will be selected. There will be no "strong" path to VDD, there will be no overshoot, or there will be no recovery after the overshoot, and the bit line level will continue to rise.

Using this feature, after the overshoot phenomenon, the overshoot recovery rate detection circuit (or slope detection circuit) can be used to calculate the slope of the bit line level and display it in the form of a level. Please refer to FIG. 4 , the overshoot recovery rate detection circuit may use a differential circuit composed of an operational amplifier, resistors, and capacitors. The output terminal of the slope detection circuit is connected to a sense amplifier. The other end of the sense amplifier can be a reference level, or a memory unit with a similar structure can be used as a reference. This type of memory cell can be a resistor with a fixed resistance, or a phase-change memory cell with an undeterminable state.

Recovery is very fast due to overshoot. Therefore, a latch circuit must be connected after the output of the sense amplifier to latch the readout result when the overshoot recovery process is not over. The delay signal of the read enable can be directly used as the control signal. In this way, by adjusting the delay time, the entire reading method can be adapted to different process conditions.

The material of the phase-change memory in the present invention can be a phase-change memory material, and its material system can be (Ge, Sb, Te), (Si, Sb, Te), (Si, Sb) or other high-performance material systems .

The device and method of the present invention can also be used for reading in multi-bit storage technology.

The present invention quickly reads the state of the phase-change memory unit by reading the recovery rate of the bit line level after the overshoot, thereby accelerating the overall read rate of the memory. In addition, fast reading is helpful to avoid damage to the phase change unit by the reading operation, so as to achieve the purpose of reducing read disturbance.

The above-mentioned embodiments only illustrate the principles and functions of the present invention, but are not intended to limit the present invention. Anyone skilled in the art can make modifications to the above-mentioned embodiments without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention should be listed in the claims.

Claims (10)

1. A fast reading device for a phase-change memory unit, characterized in that: the device comprises a phase-change memory unit to be read, a phase-change memory unit to be read connected to each other The first charging circuit is used to send a fixed current pulse to the phase-change memory cell to be read or keep the voltage of the bit line to a fixed level; The first overshoot recovery rate detection circuit connected to the phase-change memory unit to be read is used to read the recovery rate of the bit line level of the phase-change memory unit to be read, and output it in the form of a level; The first pull-down bit line circuit connected to the phase-change memory unit to be read is used to quickly pull down the bit-line circuit after the read operation is completed, so that the phase-change memory unit to be read performs the next read and write operation; A sensitive amplifying circuit connected to the output terminal of the first overshoot recovery rate detection circuit, the sensitive amplifying circuit includes at least two input terminals, one input terminal is connected to the output terminal of the first overshoot recovery rate detection circuit, and the other input terminal Connected to the reference level or the reference phase-change storage unit, it is used to compare the signal magnitudes of the two input terminals and amplify and output the comparison result; A latch circuit connected to the output of the sensitive amplifying circuit is used to lock the correct reading result into the latch when the first overshoot recovery process has not ended, so as to be used by the lower circuit; The latch control signal generating circuit connected with the latch circuit is used for generating a signal to control the latch circuit. the 2 . The device for quickly reading phase-change memory cells according to claim 1 , wherein the reference phase-change memory cell is a resistor with a fixed resistance. 3 . the 3. A kind of fast reading device of phase-change memory unit as claimed in claim 1, is characterized in that: described reference phase-change memory unit comprises reference phase-change memory, is connected with reference phase-change memory The second charging circuit is used to send a fixed current pulse to the reference phase change memory or maintain the bit line voltage to a fixed level; The second overshoot recovery rate detection circuit connected to the reference phase change memory is used to read the recovery rate of the bit line level of the reference phase change memory unit and output it in the form of a level; The second pull-down bit line circuit connected to the reference phase change memory is used to quickly pull down the bit line circuit after the read operation is completed, so that the reference phase change memory can perform the next read and write operation, and the output terminal of the second overshoot recovery rate detection circuit Connected to the input terminal of the sensitive amplifier circuit. the 4. A kind of fast reading device of phase-change memory unit as claimed in claim 1, is characterized in that: described first charging circuit comprises the electric current source that is connected with the drain end of a PMOS transistor by two PMOS transistors A set of current mirrors and a gate transistor NMOS transistor, the drain end of the gate transistor NMOS transistor is connected to the drain end of another PMOS transistor, the source end of the gate transistor NMOS transistor is connected to the bit line of the phase-change memory unit to be read, and the gate transistor The gate terminal of the NMOS transistor is connected to the read enable signal. the 5 . The fast reading device for phase-change memory cells according to claim 1 , wherein the first overshoot recovery rate detection circuit is a differential circuit. 6 . the 6. A kind of fast reading device of phase-change memory unit as claimed in claim 5, is characterized in that: described differential circuit comprises operational amplifier, the first resistance that connects operational amplifier output end and input end, the electric capacity that connects operational amplifier input end and a second resistor connected to the other input terminal of the operational amplifier. the 7. A fast reading device for a phase-change memory cell as claimed in claim 1, wherein the first pull-down bit line circuit comprises an NMOS transistor, the source end of the NMOS transistor is grounded, and the gate end is a pull-down control Signal, the drain terminal is connected to the bit line, when the pull-down control signal is high, the NMOS tube bit line is directly grounded. the 8. A kind of fast reading device of phase-change memory unit as claimed in claim 1, is characterized in that: described latch control signal generating circuit, comprises a delay circuit module for adjusting delay time, and its input signal is Read enable signal, the output signal is a latch control signal. the 9. A reading method of a fast reading device for a phase-change memory unit, characterized in that: the method comprises the following steps: 1) Utilize the first overshoot recovery rate detection circuit to read the recovery rate after the overshoot of the phase-change memory unit to be read; 2) compare the recovery rate with the recovery rate or reference level of the reference storage unit set; 3) If the output level of the first overshoot recovery rate detection circuit is greater than the reference level or the level of the reference storage unit, the sensitive amplifying circuit outputs a high-level signal, so the phase-change storage unit to be read is in a high-impedance state , if the output level of the first overshoot recovery rate detection circuit is lower than the reference level or the level of the reference phase-change memory unit, the sensitive amplifier circuit outputs a low-level signal, so the phase-change memory unit to be read is in a low-impedance state ; 4) The latch circuit latches the high-level signal or the low-level signal output by the sensitive amplifier circuit before the overshoot recovery phenomenon ends. the 10. The reading method of a fast reading device for a phase-change memory cell as claimed in claim 9, wherein the reference phase-change memory cell is a resistor with a fixed resistance value. the

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