CN102013027A - Magnetic stripe reader - Google Patents
Magnetic stripe reader Download PDFInfo
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- CN102013027A CN102013027A CN 201010576419 CN201010576419A CN102013027A CN 102013027 A CN102013027 A CN 102013027A CN 201010576419 CN201010576419 CN 201010576419 CN 201010576419 A CN201010576419 A CN 201010576419A CN 102013027 A CN102013027 A CN 102013027A
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Abstract
The invention relates to the technical field of a reader, in particular to a magnetic stripe reader, comprising a reading head, a writing head, an encoder and a control circuit board; wherein the control circuit board is composed of a peripheral control circuit, a singlechip, a serial joint and a set switch, the peripheral control circuit is composed of a decoding circuit, a coding circuit and a magnetic writing circuit, the reading head, the writing head and the encoder are respectively connected with the decoding circuit, the magnetic writing circuit and the coding circuit by virtue of communication wires and then are connected with the singlechip, the serial port of the singlechip is connected with the serial joint by virtue of a communication wire, the serial joint is the input and output of the singlechip, and the singlechip is connected with the set switch by virtue of a communication wire. The encoder provided by the invention adopts two signals, magnetic reading and writing signals are stable and uniform, reading and writing are easy, and card swiping performance is greatly improved.
Description
Technical field
The present invention relates to the read write line technical field, specifically a kind of magnetic stripe read write line.
Background technology
At present, in financial industry, magnetic card and bankbook are the main carriers of account information, and the magnetic stripe read write line remains the major equipment that reads account information, has become the essential product of financial industry.How improving (reading or writing) quality of swiping the card, is the technical barrier that each magnetic stripe read write line manufacturer makes great efforts to capture.
Summary of the invention
The objective of the invention is to overcome the deficiencies in the prior art, a kind of swipe the card magnetic stripe read write line of performance of magnetic stripe machine that improves is provided.
In order to achieve the above object, the present invention proposes a kind of magnetic stripe read write line, comprise reading head, write head, scrambler and control circuit board, it is characterized in that: control circuit board is by peripheral control circuit, single-chip microcomputer, serial ports joint and switch is set forms, peripheral control circuit is by decoding circuit, coding circuit and write magnetic circuit and form, reading head, write head, scrambler adopts connection to connect decoding circuit respectively, write magnetic circuit, insert single-chip microcomputer behind the coding circuit, the serial ports of single-chip microcomputer adopts connection to connect the serial ports joint, the serial ports joint be single-chip microcomputer the input and output single-chip microcomputer with switch employing connection be set be connected;
But the governor circuit of described single-chip microcomputer adopts the online programming STC90C54RD+ chip that contains procedure stores FLASH, expansion RAM, the STC90C54RD+ chip be numbered U5, the pin RST one tunnel of U5 connects resistance R 2 back ground connection, another road of pin RST connects capacitor C 13 backs and inserts supply voltage VCC, pin VCC one tunnel connects capacitor C 14 back ground connection, pin VCC inserts supply voltage VCC, pin P4.6/ in another road
Connect resistance R 3 backs and insert supply voltage VCC, pin GND ground connection, pin XTAL1 one tunnel connects capacitor C 16 back ground connection, a road of pin XTAL2 is inserted after connecting crystal oscillator Q1 in another road of pin XTAL1, another road of pin XTAL2 connects capacitor C 15 back ground connection, and pin P2.0, P2.1, P2.2, P2.3, P2.4, P2.5, P2.6, P2.7 insert respectively ground connection behind switch SW-DIPS is set;
It is the decoding chip LH6516G of U2, U3 that described decoding circuit adopts two block numbers, for U2: pin
One the road inserts the pin P1.3 of U5, pin
Another road connects resistance R 104 backs and inserts voltage MV+, pin OIN one tunnel connects capacitor C 107 back ground connection, another road of pin OIN connects resistance R 105 backs and connects pin OOUT, pin GND ground connection, pin BLAS one tunnel connects resistance R 106 back ground connection, another road of pin BLAS connects capacitor C 106 backs and inserts voltage MV+, and pin REF connects capacitor C 105 back ground connection, pin
Insert the pin P1.2 of U5, pin
Insert the pin of U5
/ P4.3, pin V+ one tunnel connects capacitor C 102 back ground connection, pin V+ inserts voltage MV+ in another road, pin H-IN1, H-IN2 and resistance R 102, capacitor C 103 are in parallel and form two paths of signals receiving end M2S1 and M2S2, and pin SUM connects capacitor C 104 successively, resistance R 103 backs are connected with pin DRIVE; For U3: pin
Insert the pin P1.3 of U5, pin OIN one tunnel connects capacitor C 113 back ground connection, another road of pin OIN connects resistance R 109 backs and connects pin OOUT, pin GND ground connection, pin BLAS one tunnel connects resistance R 110 back ground connection, another road of pin BLAS connects capacitor C 112 backs and inserts voltage MV+, and pin REF connects capacitor C 111 back ground connection, pin
Insert the pin P1.4 of U5, pin
Insert the pin of U5
/ P3.2, pin V+ one tunnel connects capacitor C 108 back ground connection, pin V+ inserts voltage MV+ in another road, pin H-IN1, H-IN2 and resistance R 107, capacitor C 109 are in parallel and form two paths of signals receiving end M3S1 and M3S2, and pin SUM connects capacitor C 110 successively, resistance R 108 backs are connected with pin DRIVE;
Described coding circuit is the two-way pulse signal three-stage amplifier of being made up of amplifier TL064, amplifier LM393, electric capacity, resistance and diode, scrambler adopts the two-way pulse signal to control write head 2 magnetic tracks and write head 3 magnetic tracks respectively and form write head 2 magnetic track pulse signals and write head 3 magnetic track pulse signals, and above-mentioned two-way pulse signal inserts coding circuit; Be provided with four amplifier TL064 in the coding circuit, numbering is respectively U9A, U9B, U9C and U9D, is provided with two amplifier LM393, and numbering is respectively U8A, U8B; Write head 2 magnetic track pulse signals one tunnel connect the input end of resistance R 21, another road connects capacitor C 22 and resistance R 19 successively, the output terminal of resistance R 19 divides two-way, one the road inserts the pin 2 of U9A, the input end after capacitor C 20 and resistance R 17 parallel connections is inserted on another road, output terminal after capacitor C 20 and resistance R 17 parallel connections is connected the pin 1 of U9A and the input end of capacitor C 19 respectively, the output terminal of capacitor C 19 connects the input end of resistance R 16, the output terminal of resistance R 16 divides two-way, one the road inserts the pin 13 of U9D, another road and capacitor C 18, input end after diode D4 in parallel and resistance R 15 parallel connections connects, capacitor C 18, output terminal after diode D4 in parallel and resistance R 15 parallel connections connects the pin 14 of U9D and the input end of resistance R 14 respectively, the output terminal of resistance R 14 divides two-way, one the road inserts the pin 3 of U8A, another road connects the input end of resistance R 13, and the output terminal of resistance R 13 inserts the pin of the pin 1 back access U5 of U8A
/ P3.3, the pin 1 of U8A connect resistance R 12 backs and together insert supply voltage VCC with pin 3, pin 4 ground connection of U8A, and the pin 3 of U9A connects the input end after resistance R 18 and capacitor C 21 parallel connections, and the pin 4 of U9A inserts supply voltage VCC, pin 11 ground connection of U9A; Write head 3 magnetic track pulse signals one tunnel connect the input end of resistance R 31, another road connects capacitor C 28 and resistance R 30 successively, the output terminal of resistance R 30 divides two-way, one the road inserts the pin 6 of U9B, the input end after capacitor C 26 and resistance R 28 parallel connections is inserted on another road, output terminal after capacitor C 26 and resistance R 28 parallel connections is connected the pin 7 of U9B and the input end of capacitor C 25 respectively, the output terminal of capacitor C 25 connects the input end of resistance R 27, the output terminal of resistance R 27 divides two-way, one the road inserts the pin 9 of U9C, another road and capacitor C 24, input end after diode D5 in parallel and resistance R 26 parallel connections connects, capacitor C 24, output terminal after diode D5 in parallel and resistance R 26 parallel connections connects the pin 8 of U9C and the input end of resistance R 25 respectively, the output terminal of resistance R 25 divides two-way, one the road inserts the pin 5 of U8B, another road connects the input end of resistance R 24, and the output terminal of resistance R 24 inserts the pin P4.2/ of the pin 7 back access U5 of U8B
, the pin 7 of U8B connects resistance R 23 backs and inserts supply voltage VCC, and the pin 5 of U9B connects the input end after resistance R 29 and capacitor C 27 parallel connections; The output terminal of resistance R 21 divides two-way, one the tunnel connects resistance R 20 backs inserts power supply power supply VCC, another road connects capacitor C 23 back ground connection, the output terminal of resistance R 31 connects capacitor C 23 back ground connection, the pin 6 of output terminal after output terminal after the pin 2 of U8A, the pin 12 of U9D, resistance R 18 and capacitor C 21 parallel connections, resistance R 29 and capacitor C 27 parallel connections, the pin 10 of U9C and U8B is connected the back successively and divides two-way, one the tunnel connects resistance R 32 backs inserts supply voltage VCC, and another road connects capacitor C 31, C30, the resistance R 33 back ground connection after the parallel connection;
The described magnetic circuit of writing is made up of triode, diode, resistance, electric capacity, triode comprises eight BC807 triodes and four BC817 triodes, the numbering of BC807 triode is respectively T204, T205, T206, T207, T210, T211, T212, T213, the numbering of BC817 triode is respectively T208, T209, T214, T215, diode is 4148 diodes, and numbering is respectively D202, D203, D204, D205, D206, D207, D208, D209; Write head 2 magnetic track W1, the W2 signal receiving end connects the pin P0.1 of the U5 that sends input signal, P0.0, the W1 signal receiving end connects the base stage that T204 is inserted in resistance R 206 backs, be connected resistance ST6 between the base stage of T204 and emitter, the emitter and collector of T204 connects capacitor C 203, the emitter of T204 inserts the base stage of T205, the collector of T204 inserts the collector of T205, connect D202 between the emitter and collector of T205, the emitter of T205 inserts voltage PW+5, the W2 signal receiving end connects the base stage that T207 is inserted in resistance R 207 backs, be connected resistance ST7 between the base stage of T207 and emitter, the emitter and collector of T207 connects capacitor C 204, the emitter of T207 inserts the base stage of T206, the collector of T207 inserts the collector of T206, connect D203 between the emitter and collector of T206, the emitter of T206 inserts voltage PW+5, the collector of T205 inserts the collector of T208, connect D204 between the emitter and collector of T208, the collector of T206 inserts the collector of T209, connect D205 between the emitter and collector of T209, the emitter of T208 and ground connection after the emitter of T209 is connected resistance ST8 respectively, the base stage of T208 connects resistance R 208 backs and inserts resistance R 210, R211, input end after R212 and capacitor C 205 parallel connections, resistance R 210, R211, output terminal after R212 and capacitor C 205 parallel connections inserts the pin 1 of write head 2 magnetic tracks, and base stage connection resistance R 209 backs and the collector of T208 of T209 together inserts the pin 2 of write head 2 magnetic tracks; Write head 3 magnetic track W3, the W4 signal receiving end connects the pin P0.2 of the U5 that sends input signal, P0.3, the W3 signal receiving end connects the base stage that T210 is inserted in resistance R 213 backs, be connected resistance ST9 between the base stage of T210 and emitter, the emitter and collector of T210 connects capacitor C 206, the emitter of T210 inserts the base stage of T211, the collector of T210 inserts the collector of T211, connect D202 between the emitter and collector of T211, the emitter of T211 inserts voltage PW+5, the W4 signal receiving end connects the base stage that T213 is inserted in resistance R 214 backs, be connected resistance ST10 between the base stage of T213 and emitter, the emitter and collector of T213 connects capacitor C 207, the emitter of T213 inserts the base stage of T212, the collector of T213 inserts the collector of T212, connect D207 between the emitter and collector of T212, the emitter of T212 inserts voltage PW+5, the collector of T211 inserts the collector of T214, connect D208 between the emitter and collector of T214, the collector of T212 inserts the collector of T215, connect D209 between the emitter and collector of T215, the emitter of T214 and ground connection after the emitter of T215 is connected resistance ST11 respectively, the base stage of T214 connects resistance R 215 backs and inserts resistance R 217, R218, input end after R219 and capacitor C 208 parallel connections, resistance R 217, R218, output terminal after R219 and capacitor C 208 parallel connections inserts the pin 5 of write head 3 magnetic tracks, and base stage connection resistance R 216 backs and the collector of T214 of T215 together inserts the pin 6 of write head 3 magnetic tracks.
Described scrambler adopts inside and outside double-deck reed to fix.
Scrambler of the present invention adopts two paths of signals, and read-write magnetic signal stable and uniform is convenient to read magnetic and is write magnetic, and the performance of swiping the card improves greatly.
Description of drawings
Fig. 1 is an electric theory diagram of the present invention.
Fig. 2 is the governor circuit figure of single-chip microcomputer among the present invention.
Fig. 3 is decoding circuit figure among the present invention.
Fig. 4 is coding circuit figure among the present invention.
Fig. 5 writes magnetic circuit figure among the present invention.
Fig. 6 is a regular coding device reed structure synoptic diagram of the present invention.
Referring to Fig. 6,1 is scrambler; 2 is inside and outside double-deck reed.
Embodiment
Now in conjunction with the accompanying drawings the present invention is described further.
As shown in Figure 1, the present invention includes reading head, write head, scrambler and control circuit board, control circuit board is by peripheral control circuit, single-chip microcomputer, serial ports joint and switch is set forms, peripheral control circuit is by decoding circuit, coding circuit and write magnetic circuit and form, reading head, write head, scrambler adopts connection to connect decoding circuit respectively, write magnetic circuit, insert single-chip microcomputer behind the coding circuit, the serial ports of single-chip microcomputer adopts connection to connect the serial ports joint, the serial ports joint is used to connect external unit, single-chip microcomputer adopts serial ports to carry out input and output, single-chip microcomputer adopts connection to be connected with switch is set, and the traffic rate that switch is used to be provided with serial ports is set, 2 track densitys and write the magnetic signal data layout, separator.
Be illustrated in figure 2 as governor circuit figure of the present invention, control circuit board is that the STC90C54RD+ chip is the control core with the single-chip microcomputer use, and this chip contains FLASH and the expansion RAM that procedure stores is used, and needn't extend out storage chip, but online programming.The STC90C54RD+ chip be numbered U5, pin RST one tunnel connects resistance R 2 back ground connection, and another road of pin RST connects capacitor C 13 backs and inserts supply voltage VCC, and pin VCC one tunnel connects capacitor C 14 back ground connection, pin VCC inserts supply voltage VCC, pin P4.6/ in another road
Connect resistance R 3 backs and insert supply voltage VCC, pin GND ground connection, pin XTAL1 one tunnel connects capacitor C 16 back ground connection, a road of pin XTAL2 is inserted after connecting crystal oscillator Q1 in another road of pin XTAL1, another road of pin XTAL2 connects capacitor C 15 back ground connection, and pin P2.0, P2.1, P2.2, P2.3, P2.4, P2.5, P2.6, P2.7 insert respectively ground connection behind switch SW-DIPS is set.
As shown in Figure 3, it is the decoding chip LH6516G of U2, U3 that decoding circuit adopts two block numbers, for U2: pin
One the road inserts the pin P1.3 of U5, pin
Another road connects resistance R 104 backs and inserts voltage MV+, pin OIN one tunnel connects capacitor C 107 back ground connection, another road of pin OIN connects resistance R 105 backs and connects pin OOUT, pin GND ground connection, pin BLAS one tunnel connects resistance R 106 back ground connection, another road of pin BLAS connects capacitor C 106 backs and inserts voltage MV+, and pin REF connects capacitor C 105 back ground connection, pin
Insert the pin P1.2 of U5, pin
Insert the pin of U5
/ P4.3, pin V+ one tunnel connects capacitor C 102 back ground connection, voltage MV+ is inserted on another road of pin V+, and pin H-IN1, H-IN2 and resistance R 102, capacitor C 103 are in parallel and form two paths of signals M2S1 and M2S2, and pin SUM connects capacitor C 104 successively, resistance R 103 then is connected with pin DRIVE; For U3: pin
Insert the pin P1.3 of U5, pin OIN one tunnel connects capacitor C 113 back ground connection, another road of pin OIN connects resistance R 109 backs and connects pin OOUT, pin GND ground connection, pin BLAS one tunnel connects resistance R 110 back ground connection, another road of pin BLAS connects capacitor C 112 backs and inserts voltage MV+, and pin REF connects capacitor C 111 back ground connection, pin
Insert the pin P1.4 of U5, pin
Insert the pin of U5
/ P3.2, pin V+ one tunnel connects capacitor C 108 back ground connection, voltage MV+ is inserted on another road of pin V+, and pin H-IN1, H-IN2 and resistance R 107, capacitor C 109 are in parallel and form two paths of signals M3S1 and M3S2, and pin SUM connects capacitor C 110 successively, resistance R 108 then is connected with pin DRIVE.
As shown in Figure 4, coding circuit is the two-way pulse signal three-stage amplifier of being made up of amplifier TL064, amplifier LM393, electric capacity, resistance and diode, scrambler adopts the two-way pulse signal to control write head 2 magnetic tracks and write head 3 magnetic tracks respectively and form write head 2 magnetic track pulse signals and write head 3 magnetic track pulse signals, and above-mentioned two-way pulse signal inserts coding circuit; Be provided with four amplifier TL064 in the coding circuit, numbering is respectively U9A, U9B, U9C and U9D, is provided with two amplifier LM393, and numbering is respectively U8A, U8B; Write head 2 magnetic track pulse signals one tunnel connect the input end of resistance R 21, another road connects capacitor C 22 and resistance R 19 successively, the output terminal of resistance R 19 divides two-way, one the road inserts the pin 2 of U9A, the input end after capacitor C 20 and resistance R 17 parallel connections is inserted on another road, output terminal after capacitor C 20 and resistance R 17 parallel connections is connected the pin 1 of U9A and the input end of capacitor C 19 respectively, the output terminal of capacitor C 19 connects the input end of resistance R 16, the output terminal of resistance R 16 divides two-way, one the road inserts the pin 13 of U9D, another road and capacitor C 18, input end after diode D4 in parallel and resistance R 15 parallel connections connects, capacitor C 18, output terminal after diode D4 in parallel and resistance R 15 parallel connections connects the pin 14 of U9D and the input end of resistance R 14 respectively, the output terminal of resistance R 14 divides two-way, one the road inserts the pin 3 of U8A, another road connects the input end of resistance R 13, and the output terminal of resistance R 13 inserts the pin of the pin 1 back access U5 of U8A
/ P3.3, the pin 1 of U8A connect resistance R 12 backs and together insert supply voltage VCC with pin 3, pin 4 ground connection of U8A, and the pin 3 of U9A connects the input end after resistance R 18 and capacitor C 21 parallel connections, and the pin 4 of U9A inserts supply voltage VCC, pin 11 ground connection of U9A; Write head 3 magnetic track pulse signals one tunnel connect the input end of resistance R 31, another road connects capacitor C 28 and resistance R 30 successively, the output terminal of resistance R 30 divides two-way, one the road inserts the pin 6 of U9B, the input end after capacitor C 26 and resistance R 28 parallel connections is inserted on another road, output terminal after capacitor C 26 and resistance R 28 parallel connections is connected the pin 7 of U9B and the input end of capacitor C 25 respectively, the output terminal of capacitor C 25 connects the input end of resistance R 27, the output terminal of resistance R 27 divides two-way, one the road inserts the pin 9 of U9C, another road and capacitor C 24, input end after diode D5 in parallel and resistance R 26 parallel connections connects, capacitor C 24, output terminal after diode D5 in parallel and resistance R 26 parallel connections connects the pin 8 of U9C and the input end of resistance R 25 respectively, the output terminal of resistance R 25 divides two-way, one the road inserts the pin 5 of U8B, another road connects the input end of resistance R 24, and the output terminal of resistance R 24 inserts the pin P4.2/ of the pin 7 back access U5 of U8B
, the pin 7 of U8B connects resistance R 23 backs and inserts supply voltage VCC, and the pin 5 of U9B connects the input end after resistance R 29 and capacitor C 27 parallel connections; The output terminal of resistance R 21 divides two-way, one the tunnel connects resistance R 20 backs inserts power supply power supply VCC, another road connects capacitor C 23 back ground connection, the output terminal of resistance R 31 connects capacitor C 23 back ground connection, the pin 6 of output terminal after output terminal after the pin 2 of U8A, the pin 12 of U9D, resistance R 18 and capacitor C 21 parallel connections, resistance R 29 and capacitor C 27 parallel connections, the pin 10 of U9C and U8B is connected the back successively and divides two-way, one the tunnel connects resistance R 32 backs inserts supply voltage VCC, and another road connects capacitor C 31, C30, the resistance R 33 back ground connection after the parallel connection.
As shown in Figure 5, writing magnetic circuit is made up of triode, diode, resistance, electric capacity, triode comprises eight BC807 triodes and four BC817 triodes, the numbering of BC807 triode is respectively T204, T205, T206, T207, T210, T211, T212, T213, the numbering of BC817 triode is respectively T208, T209, T214, T215, diode is 4148 diodes, and numbering is respectively D202, D203, D204, D205, D206, D207, D208, D209; Write head 2 magnetic track W1, the W2 signal receiving end connects the pin P0.1 of the U5 that sends input signal, P0.0, the W1 signal receiving end connects the base stage that T204 is inserted in resistance R 206 backs, be connected resistance ST6 between the base stage of T204 and emitter, the emitter and collector of T204 connects capacitor C 203, the emitter of T204 inserts the base stage of T205, the collector of T204 inserts the collector of T205, connect D202 between the emitter and collector of T205, the emitter of T205 inserts voltage PW+5, the W2 signal receiving end connects the base stage that T207 is inserted in resistance R 207 backs, be connected resistance ST7 between the base stage of T207 and emitter, the emitter and collector of T207 connects capacitor C 204, the emitter of T207 inserts the base stage of T206, the collector of T207 inserts the collector of T206, connect D203 between the emitter and collector of T206, the emitter of T206 inserts voltage PW+5, the collector of T205 inserts the collector of T208, connect D204 between the emitter and collector of T208, the collector of T206 inserts the collector of T209, connect D205 between the emitter and collector of T209, the emitter of T208 and ground connection after the emitter of T209 is connected resistance ST8 respectively, the base stage of T208 connects resistance R 208 backs and inserts resistance R 210, R211, input end after R212 and capacitor C 205 parallel connections, resistance R 210, R211, output terminal after R212 and capacitor C 205 parallel connections inserts the pin 1 of write head 2 magnetic tracks, and base stage connection resistance R 209 backs and the collector of T208 of T209 together inserts the pin 2 of write head 2 magnetic tracks; Write head 3 magnetic track W3, the W4 signal receiving end connects the pin P0.2 of the U5 that sends input signal, P0.3, the W3 signal receiving end connects the base stage that T210 is inserted in resistance R 213 backs, be connected resistance ST9 between the base stage of T210 and emitter, the emitter and collector of T210 connects capacitor C 206, the emitter of T210 inserts the base stage of T211, the collector of T210 inserts the collector of T211, connect D202 between the emitter and collector of T211, the emitter of T211 inserts voltage PW+5, the W4 signal receiving end connects the base stage that T213 is inserted in resistance R 214 backs, be connected resistance ST10 between the base stage of T213 and emitter, the emitter and collector of T213 connects capacitor C 207, the emitter of T213 inserts the base stage of T212, the collector of T213 inserts the collector of T212, connect D207 between the emitter and collector of T212, the emitter of T212 inserts voltage PW+5, the collector of T211 inserts the collector of T214, connect D208 between the emitter and collector of T214, the collector of T212 inserts the collector of T215, connect D209 between the emitter and collector of T215, the emitter of T214 and ground connection after the emitter of T215 is connected resistance ST11 respectively, the base stage of T214 connects resistance R 215 backs and inserts resistance R 217, R218, input end after R219 and capacitor C 208 parallel connections, resistance R 217, R218, output terminal after R219 and capacitor C 208 parallel connections inserts the pin 5 of write head 3 magnetic tracks, and base stage connection resistance R 216 backs and the collector of T214 of T215 together inserts the pin 6 of write head 3 magnetic tracks.
Referring to Fig. 6, the reed that is used for fixing scrambler 1 among the present invention is inside and outside double-deck reed 2, and enough pressure can be provided, scrambler is contacted with write head well, can effectively cushion the pressure jump that thick cassette tape comes, guarantee the effect of swiping the card better, improve magnetic stripe machine performance greatly.
Principle of work of the present invention is as follows:
One, writes magnetic
Receive when writing the magnetic order, be connected on the pin P3.3 and P4.2 of singlechip chip U5 as interrupt source INT1 and INT3 after the write head 2 magnetic track pulse signals that scrambler produces and three grades of amplifications of the encoded circuit of write head 3 magnetic track pulse signals, single-chip microcomputer utilizes these Interrupt Process write head 2 magnetic tracks or write head 3 magnetic tracks.Write head 2 track data are write W1, the W2 input signal of magnetic circuit by pin P0.1, the P0.0 output conduct of singlechip chip U5; Write head 3 track data are write W3, the W4 input signal of magnetic circuit by pin P0.2, the P0.3 output conduct of singlechip chip U5.Writing magnetic circuit becomes simulating signal to write on the magnetic stripe by write head the digital signal processing of single-chip microcomputer output.
Two, read magnetic
Receive when reading the magnetic order that write head 2 magnetic track signal M2S2, M2S1 are decoded into pin P4.3, the P1.2 that digital signal enters singlechip chip U5 by M2S2, the M2S1 signal receiving end of decoding circuit through decoding chip LH6516G; Write head 3 magnetic track signal M3S2, M3S1 are decoded into pin P3.2, the P1.4 that digital signal enters singlechip chip U5 by M3S2, the N3S1 signal receiving end of decoding chip LH6516G through decoding chip LH6516G; Single-chip microcomputer is reduced into account data with the digital signal of importing and exports by serial ports.
Claims (2)
1. magnetic stripe read write line, comprise reading head, write head, scrambler and control circuit board, it is characterized in that: control circuit board is by peripheral control circuit, single-chip microcomputer, serial ports joint and switch is set forms, peripheral control circuit is by decoding circuit, coding circuit and write magnetic circuit and form, reading head, write head, scrambler adopts connection to connect decoding circuit respectively, write magnetic circuit, insert single-chip microcomputer behind the coding circuit, the serial ports of single-chip microcomputer adopts connection to connect the serial ports joint, the serial ports joint be single-chip microcomputer the input and output single-chip microcomputer with switch employing connection be set be connected;
But the governor circuit of described single-chip microcomputer adopts the online programming STC90C54RD+ chip that contains procedure stores FLASH, expansion RAM, the STC90C54RD+ chip be numbered U5, the pin RST one tunnel of U5 connects resistance R 2 back ground connection, another road of pin RST connects capacitor C 13 backs and inserts supply voltage VCC, pin VCC one tunnel connects capacitor C 14 back ground connection, pin VCC inserts supply voltage VCC, pin P4.6/ in another road
Connect resistance R 3 backs and insert supply voltage VCC, pin GND ground connection, pin XTAL1 one tunnel connects capacitor C 16 back ground connection, a road of pin XTAL2 is inserted after connecting crystal oscillator Q1 in another road of pin XTAL1, another road of pin XTAL2 connects capacitor C 15 back ground connection, and pin P2.0, P2.1, P2.2, P2.3, P2.4, P2.5, P2.6, P2.7 insert respectively ground connection behind switch SW-DIPS is set;
It is the decoding chip LH6516G of U2, U3 that described decoding circuit adopts two block numbers, for U2: pin
One the road inserts the pin P1.3 of U5, pin
Another road connects resistance R 104 backs and inserts voltage MV+, pin OIN one tunnel connects capacitor C 107 back ground connection, another road of pin OIN connects resistance R 105 backs and connects pin OOUT, pin GND ground connection, pin BLAS one tunnel connects resistance R 106 back ground connection, another road of pin BLAS connects capacitor C 106 backs and inserts voltage MV+, and pin REF connects capacitor C 105 back ground connection, pin
Insert the pin P1.2 of U5, pin
Insert the pin of U5
/ P4.3, pin V+ one tunnel connects capacitor C 102 back ground connection, pin V+ inserts voltage MV+ in another road, pin H-IN1, H-IN2 and resistance R 102, capacitor C 103 are in parallel and form two paths of signals receiving end M2S1 and M2S2, and pin SUM connects capacitor C 104 successively, resistance R 103 backs are connected with pin DRIVE; For U3: pin
Insert the pin P1.3 of U5, pin OIN one tunnel connects capacitor C 113 back ground connection, another road of pin OIN connects resistance R 109 backs and connects pin OOUT, pin GND ground connection, pin BLAS one tunnel connects resistance R 110 back ground connection, another road of pin BLAS connects capacitor C 112 backs and inserts voltage MV+, and pin REF connects capacitor C 111 back ground connection, pin
Insert the pin P1.4 of U5, pin
Insert the pin of U5
/ P3.2, pin V+ one tunnel connects capacitor C 108 back ground connection, pin V+ inserts voltage MV+ in another road, pin H-IN1, H-IN2 and resistance R 107, capacitor C 109 are in parallel and form two paths of signals receiving end M3S1 and M3S2, and pin SUM connects capacitor C 110 successively, resistance R 108 backs are connected with pin DRIVE;
Described coding circuit is the two-way pulse signal three-stage amplifier of being made up of amplifier TL064, amplifier LM393, electric capacity, resistance and diode, scrambler adopts the two-way pulse signal to control write head 2 magnetic tracks and write head 3 magnetic tracks respectively and form write head 2 magnetic track pulse signals and write head 3 magnetic track pulse signals, and above-mentioned two-way pulse signal inserts coding circuit; Be provided with four amplifier TL064 in the coding circuit, numbering is respectively U9A, U9B, U9C and U9D, is provided with two amplifier LM393, and numbering is respectively U8A, U8B; Write head 2 magnetic track pulse signals one tunnel connect the input end of resistance R 21, another road connects capacitor C 22 and resistance R 19 successively, the output terminal of resistance R 19 divides two-way, one the road inserts the pin 2 of U9A, the input end after capacitor C 20 and resistance R 17 parallel connections is inserted on another road, output terminal after capacitor C 20 and resistance R 17 parallel connections is connected the pin 1 of U9A and the input end of capacitor C 19 respectively, the output terminal of capacitor C 19 connects the input end of resistance R 16, the output terminal of resistance R 16 divides two-way, one the road inserts the pin 13 of U9D, another road and capacitor C 18, input end after diode D4 in parallel and resistance R 15 parallel connections connects, capacitor C 18, output terminal after diode D4 in parallel and resistance R 15 parallel connections connects the pin 14 of U9D and the input end of resistance R 14 respectively, the output terminal of resistance R 14 divides two-way, one the road inserts the pin 3 of U8A, another road connects the input end of resistance R 13, and the output terminal of resistance R 13 inserts the pin of the pin 1 back access U5 of U8A
/ P3.3, the pin 1 of U8A connect resistance R 12 backs and together insert supply voltage VCC with pin 3, pin 4 ground connection of U8A, and the pin 3 of U9A connects the input end after resistance R 18 and capacitor C 21 parallel connections, and the pin 4 of U9A inserts supply voltage VCC, pin 11 ground connection of U9A; Write head 3 magnetic track pulse signals one tunnel connect the input end of resistance R 31, another road connects capacitor C 28 and resistance R 30 successively, the output terminal of resistance R 30 divides two-way, one the road inserts the pin 6 of U9B, the input end after capacitor C 26 and resistance R 28 parallel connections is inserted on another road, output terminal after capacitor C 26 and resistance R 28 parallel connections is connected the pin 7 of U9B and the input end of capacitor C 25 respectively, the output terminal of capacitor C 25 connects the input end of resistance R 27, the output terminal of resistance R 27 divides two-way, one the road inserts the pin 9 of U9C, another road and capacitor C 24, input end after diode D5 in parallel and resistance R 26 parallel connections connects, capacitor C 24, output terminal after diode D5 in parallel and resistance R 26 parallel connections connects the pin 8 of U9C and the input end of resistance R 25 respectively, the output terminal of resistance R 25 divides two-way, one the road inserts the pin 5 of U8B, another road connects the input end of resistance R 24, and the output terminal of resistance R 24 inserts the pin P4.2/ of the pin 7 back access U5 of U8B
, the pin 7 of U8B connects resistance R 23 backs and inserts supply voltage VCC, and the pin 5 of U9B connects the input end after resistance R 29 and capacitor C 27 parallel connections; The output terminal of resistance R 21 divides two-way, one the tunnel connects resistance R 20 backs inserts power supply power supply VCC, another road connects capacitor C 23 back ground connection, the output terminal of resistance R 31 connects capacitor C 23 back ground connection, the pin 6 of output terminal after output terminal after the pin 2 of U8A, the pin 12 of U9D, resistance R 18 and capacitor C 21 parallel connections, resistance R 29 and capacitor C 27 parallel connections, the pin 10 of U9C and U8B is connected the back successively and divides two-way, one the tunnel connects resistance R 32 backs inserts supply voltage VCC, and another road connects capacitor C 31, C30, the resistance R 33 back ground connection after the parallel connection;
The described magnetic circuit of writing is made up of triode, diode, resistance, electric capacity, triode comprises eight BC807 triodes and four BC817 triodes, the numbering of BC807 triode is respectively T204, T205, T206, T207, T210, T211, T212, T213, the numbering of BC817 triode is respectively T208, T209, T214, T215, diode is 4148 diodes, and numbering is respectively D202, D203, D204, D205, D206, D207, D208, D209; Write head 2 magnetic track W1, the W2 signal receiving end connects the pin P0.1 of the U5 that sends input signal, P0.0, the W1 signal receiving end connects the base stage that T204 is inserted in resistance R 206 backs, be connected resistance ST6 between the base stage of T204 and emitter, the emitter and collector of T204 connects capacitor C 203, the emitter of T204 inserts the base stage of T205, the collector of T204 inserts the collector of T205, connect D202 between the emitter and collector of T205, the emitter of T205 inserts voltage PW+5, the W2 signal receiving end connects the base stage that T207 is inserted in resistance R 207 backs, be connected resistance ST7 between the base stage of T207 and emitter, the emitter and collector of T207 connects capacitor C 204, the emitter of T207 inserts the base stage of T206, the collector of T207 inserts the collector of T206, connect D203 between the emitter and collector of T206, the emitter of T206 inserts voltage PW+5, the collector of T205 inserts the collector of T208, connect D204 between the emitter and collector of T208, the collector of T206 inserts the collector of T209, connect D205 between the emitter and collector of T209, the emitter of T208 and ground connection after the emitter of T209 is connected resistance ST8 respectively, the base stage of T208 connects resistance R 208 backs and inserts resistance R 210, R211, input end after R212 and capacitor C 205 parallel connections, resistance R 210, R211, output terminal after R212 and capacitor C 205 parallel connections inserts the pin 1 of write head 2 magnetic tracks, and base stage connection resistance R 209 backs and the collector of T208 of T209 together inserts the pin 2 of write head 2 magnetic tracks; Write head 3 magnetic track W3, the W4 signal receiving end connects the pin P0.2 of the U5 that sends input signal, P0.3, the W3 signal receiving end connects the base stage that T210 is inserted in resistance R 213 backs, be connected resistance ST9 between the base stage of T210 and emitter, the emitter and collector of T210 connects capacitor C 206, the emitter of T210 inserts the base stage of T211, the collector of T210 inserts the collector of T211, connect D202 between the emitter and collector of T211, the emitter of T211 inserts voltage PW+5, the W4 signal receiving end connects the base stage that T213 is inserted in resistance R 214 backs, be connected resistance ST10 between the base stage of T213 and emitter, the emitter and collector of T213 connects capacitor C 207, the emitter of T213 inserts the base stage of T212, the collector of T213 inserts the collector of T212, connect D207 between the emitter and collector of T212, the emitter of T212 inserts voltage PW+5, the collector of T211 inserts the collector of T214, connect D208 between the emitter and collector of T214, the collector of T212 inserts the collector of T215, connect D209 between the emitter and collector of T215, the emitter of T214 and ground connection after the emitter of T215 is connected resistance ST11 respectively, the base stage of T214 connects resistance R 215 backs and inserts resistance R 217, R218, input end after R219 and capacitor C 208 parallel connections, resistance R 217, R218, output terminal after R219 and capacitor C 208 parallel connections inserts the pin 5 of write head 3 magnetic tracks, and base stage connection resistance R 216 backs and the collector of T214 of T215 together inserts the pin 6 of write head 3 magnetic tracks.
2. a kind of magnetic stripe read write line according to claim 1 is characterized in that: described scrambler (1) adopts inside and outside double-deck reed (2) fixing.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201010576419A CN102013027B (en) | 2010-12-07 | 2010-12-07 | Magnetic stripe reader |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201010576419A CN102013027B (en) | 2010-12-07 | 2010-12-07 | Magnetic stripe reader |
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| Publication Number | Publication Date |
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| CN102013027A true CN102013027A (en) | 2011-04-13 |
| CN102013027B CN102013027B (en) | 2012-10-10 |
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| CN201010576419A Expired - Fee Related CN102013027B (en) | 2010-12-07 | 2010-12-07 | Magnetic stripe reader |
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN2357368Y (en) * | 1999-02-12 | 2000-01-05 | 北京科瑞奇技术开发有限公司 | Intelligent anti-forge finance POS apparatus |
| CN201166878Y (en) * | 2008-03-07 | 2008-12-17 | 惠东 | Multifunctional automatic goods-selling system |
| CN201285550Y (en) * | 2008-03-31 | 2009-08-05 | 上海哈诚电子科技有限公司 | Draw channel type magnetic card read-write machine |
-
2010
- 2010-12-07 CN CN201010576419A patent/CN102013027B/en not_active Expired - Fee Related
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN2357368Y (en) * | 1999-02-12 | 2000-01-05 | 北京科瑞奇技术开发有限公司 | Intelligent anti-forge finance POS apparatus |
| CN201166878Y (en) * | 2008-03-07 | 2008-12-17 | 惠东 | Multifunctional automatic goods-selling system |
| CN201285550Y (en) * | 2008-03-31 | 2009-08-05 | 上海哈诚电子科技有限公司 | Draw channel type magnetic card read-write machine |
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| CN102013027B (en) | 2012-10-10 |
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