CN102012881A - Bus monitor-based system chip bus priority dynamic configuration device - Google Patents
Bus monitor-based system chip bus priority dynamic configuration device Download PDFInfo
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Abstract
The invention discloses a bus monitor-based system chip bus priority dynamic configuration device, which comprises four counters, a timer and a dynamic priority configuration module. The four counters are used for accumulating overlap cycle number of access initiated simultaneously by a plurality of pieces of equipment, memory access times, memory access cycle number comprising equipment request time delay and external memory time delay, and memory access cycle number comprising the equipment request time delay; and the dynamic priority configuration module is used for multiplying or summing real-time weight of each equipment and memory access time delay of each equipment, wherein the memory access time delay is the memory access cycle number comprising equipment request time delay and external memory time delay or the memory access cycle number comprising the equipment request time delay, and the priority is set according to the product or the sum, wherein the product or the sum is greater, the priority is higher. The dynamic configuration device can effectively respond to a request of a low-priority internet protocol (IP) and has good real-time property.
Description
Technical field
The present invention relates to the System on Chip/SoC field, especially a kind of priority dynamic-configuration based on bus monitor.
Background technology
System on Chip/SoC with the major function of system comprehensively in chip piece.Compare with traditional design, because System on Chip/SoC is integrated in total system on the chip, make the performance of product greatly improve, volume significantly dwindles.In addition, System on Chip/SoC is applicable to more complicated system, has the reliability of lower design cost and Geng Gao.In present integrated circuit (IC) design theory, IP (Intellectual Property) is the elementary cell of construction system chip.IP satisfies specific specifications, and can be in design multiplexing functional module, claims IP kernel again.
Along with the development of integrated circuit (IC) design and manufacturing technology, the IP number in the System on Chip/SoC constantly increases.Because each IP concurrent working, along with the IP number increases, the accessing competition rate of resource also improves thereupon.
The method of conventional process accessing competition is the static priority scheduling.After the static priority scheduling was meant that priority well, in system's operational process, priority can not change.This method is set static priority for each IP, and the operational process medium priority remains unchanged in system, and when a plurality of IP initiated request of access simultaneously, the IP of high priority preferentially obtained access right.
Different with the software scheduling, hardware scheduling can not be seized, and this is by the decision of bus mechanism.Be after low priority I P obtains access right, high priority IP initiates after the request of access low priority I P such as need and visits and just obtain access right after finishing.
The advantage of static priority is that scheduling is simple, and system overhead is little.Its shortcoming is the situation that the request of low priority I P can't meet with a response for a long time possible occur, is not suitable for the demanding system of real-time.
As having A, B, three IP of C in certain audio/video player system, wherein A is used to control LCD, and B is used to carry data, and C is used for the video file decoding.Three IP need access memory.Be generally and guarantee the video playback smoothness, the priority of its access memory is A, B, C from high to low.Wherein the data access amount of A and B is basicly stable, and the data access amount of C is determined by the picture intensity of variation.When picture altered a great deal, C needed mass data.The C that is in lowest priority possibly can't in time obtain the source data of latest frame, thereby can't in time decode the data of latest frame, and B can't obtain the data of latest frame.A will control the picture of the former frame of liquid crystal display displays, cause video playback not smooth.
Summary of the invention
For the request that overcomes the low priority I P that has existing systems chip bus static priority configuration mechanism can't in time respond, the deficiency of real-time difference, the invention provides the good System on Chip/SoC bus priority dynamic-configuration device of request, real-time of a kind of significant response low priority I P based on bus monitor.
The technical solution adopted for the present invention to solve the technical problems is:
A kind of System on Chip/SoC bus priority dynamic-configuration device based on bus monitor, described System on Chip/SoC bus priority dynamic-configuration device comprises:
Initiate the overlapping periodicity of internal storage access, internal storage access number of times simultaneously, comprise the internal storage access periodicity of device request time-delay and external memory time-delay and four counters that comprise the internal storage access periodicity of device request time-delay in order to a plurality of equipment of accumulative total;
A timer;
And in order to the real-time weight of each equipment and the internal storage access time-delay of each equipment are done product or addition, described internal storage access is delayed time to the internal storage access periodicity that comprises device request time-delay and external memory time-delay or is comprised the internal storage access periodicity that device request is delayed time, and according to product or with size priority is set: product or and the high more priority dynamic-configuration module of big more then priority.
Further, in the described counter in order to accumulative total internal storage access number of times, when choice of equipment signal and device ready signal simultaneously effectively, and equipment state then shows the initiation internal storage access, this Counter Value increase by 1 this moment when be idle.
Further again, describedly be used for the counter that accumulative total comprises the internal storage access periodicity of device request time-delay and external memory time-delay, when choice of equipment signal and device ready signal simultaneously effectively, and equipment state shows equipment initiation internal storage access when be the free time; If internal storage access finishes invalidating signal, show that then the Device memory visit do not finish, this moment this Counter Value weekly the phase increase by 1, it is effective to finish signal until internal storage access.
Further, describedly be used for the counter that accumulative total comprises the internal storage access periodicity of device request time-delay, when choice of equipment signal and device ready signal simultaneously effectively, and equipment state shows equipment initiation internal storage access when be idle; If the moderator OPADD is identical with the device request address, show that then this equipment obtains internal storage access power, the phase increase by 1 weekly of this Counter Value this moment, different until the moderator OPADD with the device request address.
The described a plurality of equipment of accumulative total that are used for are initiated the counter of the overlapping periodicity of internal storage access simultaneously, when choice of equipment signal and device ready signal simultaneously effectively, and equipment state shows equipment initiation internal storage access when be idle; If internal storage access finishes invalidating signal, show that then the Device memory visit do not finish; When two or more equipment are in the internal storage access unfinished state, show that then the visit of a plurality of Device memory is overlapping, this moment this Counter Value weekly the phase increase by 1, until having only one or do not have equipment to be in the internal storage access unfinished state.
As preferred a kind of scheme: when addition is done in the internal storage access time-delay of the real-time weight of each equipment and each equipment, at first default coefficient is multiply by in the internal storage access time-delay of described each equipment and obtain intermediate value, described intermediate value has the identical order of magnitude with the real-time weight of described each equipment.
Technical conceive of the present invention is: dynamic priority configuration is meant that priority can change along with time or system state change, in system's operational process according to the situation configuration preference level of each IP, to obtain more performance.
The advantage of dynamic priority is that dispatching algorithm is flexible, can prevent that the request of access of some IP from can not get response always.Its shortcoming is the priority Algorithm of Dynamic Configuration that needs operation relevant, increases system overhead.
The present invention adopts bus priority dynamic-configuration mechanism, has improved the problem that the request of low priority I P can't in time respond, and makes System on Chip/SoC can move real-time system.
Based on the System on Chip/SoC bus priority dynamic-configuration mechanism of bus monitor, finish by the software and hardware combination.Wherein hardware comprises four counters, and a timer, software comprise a kind of priority Algorithm of Dynamic Configuration.Wherein four counters are respectively applied for accumulative total
A. many equipment are initiated the overlapping periodicity of internal storage access simultaneously;
B. internal storage access number of times;
C. the internal storage access periodicity that comprises device request time-delay and external memory time-delay;
D. the internal storage access periodicity that comprises the device request time-delay.
Its medium priority Algorithm of Dynamic Configuration, the priority of each equipment is by the real-time weight of each equipment and the common decision of the internal storage access time-delay of each equipment (comprise the internal storage access periodicity of device request time-delay and external memory time-delay or comprise the internal storage access periodicity that device request is delayed time).The real-time weight of equipment is a static configuration, and real-time weight indication equipment is to the requirement of real-time response, and equal when Device memory visit time-delay, the real-time weight is high more, and priority is high more.The time-delay of the internal storage access of equipment is read from hardware register at set intervals, and when the real-time weight is identical, Device memory visit time-delay is big more, and priority is high more.
Beneficial effect of the present invention mainly shows: request, the real-time of significant response low priority I P are good.
Description of drawings
Fig. 1 is the realization circuit diagram of accumulative total internal storage access time counter.
Fig. 2 comprises the realization circuit diagram of the internal storage access periodicity counter of device request time-delay and external memory time-delay for accumulative total.
Fig. 3 comprises the realization circuit diagram of the internal storage access periodicity counter of device request time-delay for accumulative total.
Fig. 4 initiates the realization circuit diagram of the overlapping periodicity counter of internal storage access simultaneously for a plurality of equipment of accumulative total.
Fig. 5 is a bus priority dynamic-configuration mechanism process flow diagram.
Fig. 6 is a Timer interrupt service routine process flow diagram.
Fig. 7 is a priority Algorithm of Dynamic Configuration process flow diagram.
Fig. 8 is priority Algorithm of Dynamic Configuration implementing procedure figure.
Embodiment
Below in conjunction with accompanying drawing the present invention is further described.
With reference to Fig. 1～Fig. 8, a kind of System on Chip/SoC bus priority dynamic-configuration device based on bus monitor, described System on Chip/SoC bus priority dynamic-configuration device comprises:
Initiate the overlapping periodicity of internal storage access, internal storage access number of times simultaneously, comprise the internal storage access periodicity of device request time-delay and external memory time-delay and four counters that comprise the internal storage access periodicity of device request time-delay in order to a plurality of equipment of accumulative total;
A timer;
And in order to the real-time weight of each equipment and the internal storage access time-delay of each equipment are done product or addition, described internal storage access is delayed time to the internal storage access periodicity that comprises device request time-delay and external memory time-delay or is comprised the internal storage access periodicity that device request is delayed time, and according to product or with size priority is set: product or and the high more priority dynamic-configuration module of big more then priority.
In the described counter in order to accumulative total internal storage access number of times, when choice of equipment signal and device ready signal simultaneously effectively, and equipment state then shows the initiation internal storage access, this Counter Value increase by 1 this moment when be idle.
Describedly be used for the counter that accumulative total comprises the internal storage access periodicity of device request time-delay and external memory time-delay, when choice of equipment signal and device ready signal simultaneously effectively, and equipment state shows equipment initiation internal storage access when be the free time; If internal storage access finishes invalidating signal, show that then the Device memory visit do not finish, this moment this Counter Value weekly the phase increase by 1, it is effective to finish signal until internal storage access.
Describedly be used for the counter that accumulative total comprises the internal storage access periodicity of device request time-delay, when choice of equipment signal and device ready signal simultaneously effectively, and equipment state shows equipment initiation internal storage access when be idle; If the moderator OPADD is identical with the device request address, show that then this equipment obtains internal storage access power, the phase increase by 1 weekly of this Counter Value this moment, different until the moderator OPADD with the device request address.
The described a plurality of equipment of accumulative total that are used for are initiated the counter of the overlapping periodicity of internal storage access simultaneously, when choice of equipment signal and device ready signal simultaneously effectively, and equipment state shows equipment initiation internal storage access when be idle; If internal storage access finishes invalidating signal, show that then the Device memory visit do not finish; When two or more equipment are in the internal storage access unfinished state, show that then the visit of a plurality of Device memory is overlapping, this moment this Counter Value weekly the phase increase by 1, until having only one or do not have equipment to be in the internal storage access unfinished state.
Hardware realizes that four counters are 64, are made up of two 32 digit counters based on the AMBA bus; When adding 1 for 0xffffffff and counter for low 32, high 32 digit counters add 1.Choice of equipment signal i_mnt_hesl, device ready signal i_mnt_hready, device transmission signal i_mnt_htrans by the AMBA bus judge whether to initiate internal storage access.32 digit counters are made of 32 bit registers, 32 totalizers, data selectors, wherein the register clock is AMBA bus clock signal i_mnt_clk, register is input as data selector output, two inputs of data selector are respectively register output and totalizer output, and totalizer is input as register output and 1.When data selector selected signal to be 0, data selector was output as register output, otherwise was totalizer output.
Please refer to Fig. 1, realize circuit diagram for the counter that is used for accumulative total internal storage access number of times, the data selector in its low 32 digit counters selects signal to be produced by choice of equipment signal i_mnt_hsel, device ready signal i_mnt_hready, device transmission signal i_mnt_htrans.When choice of equipment signal i_mnt_hsel and device ready signal i_mnt_hready be 1 and device transmission signal i_mnt_htrans be not equal to 0, then show the initiation internal storage access, this moment data selector to select signal be 1.
Please refer to Fig. 2, for being used for the counter realization circuit that accumulative total comprises the internal storage access periodicity of device request time-delay and external memory time-delay, the data selector in its low 32 digit counters selects signal to be produced by device replied signal i_mnt_hready_resp, device ready signal i_mnt_hready, choice of equipment signal i_mnt_hsel, device transmission signal i_mnt_htrans.When choice of equipment signal i_mnt_hsel and device ready signal i_mnt_hready be 1 and device transmission signal i_mnt_htrans be not equal to 0, then show the initiation internal storage access, if device replied signal i_mnt_hready_resp is 0, show and carry out internal storage access that data selector selection this moment signal is 1.
Please refer to Fig. 3, for being used for the counter realization circuit that accumulative total comprises the internal storage access periodicity of device request time-delay, data selector in its low 32 digit counters selects signal by device address signal i_mnt_haddr, choice of equipment signal i_mnt_hsel, device transmission signal i_mnt_htrans, moderator address signal i_mnt_haddr_arb, moderator ready signal i_mnt_hready_arb, moderator is selected signal i_mnt_hsel_arb, moderator transmission signals i_mnt_htrans_arb produces, when choice of equipment signal i_mnt_hsel and device ready signal i_mnt_hready be 1 and device transmission signal i_mnt_htrans be not equal to 0, then show the initiation internal storage access, when moderator select signal i_mnt_hsel_arb and moderator ready signal i_mnt_hsel_arb be 1 and moderator transmission signals i_mnt_htrans_arb be not equal to 0, show that then moderator selects certain equipment to carry out internal storage access.When device address signal i_mnt_haddr equates with moderator address signal i_mnt_haddr_arb, show that then moderator selects this equipment to carry out internal storage access, promptly this equipment obtains internal storage access power, this moment data selector to select signal be 1.
Please refer to Fig. 4, initiate the counter realization circuit of the overlapping periodicity of internal storage access simultaneously for being used for a plurality of equipment of accumulative total, the data selector in its low 32 digit counters selects signal to be produced by device replied signal i_mnt_hready_resp, choice of equipment signal i_mnt_hsel, device ready signal i_mnt_hready, the device transmission signal i_mnt_htrans of all devices.When choice of equipment signal i_mnt_hsel and device ready signal i_mnt_hready be 1 and device transmission signal i_mnt_htrans be not equal to 0, then show the initiation internal storage access, if device replied signal i_mnt_hready_resp is 0, shows and carry out internal storage access.When any two or more equipment are carrying out internal storage access, show that the visit internal storage access is overlapping, data selector selection this moment signal is 1.
Bus monitor comprises 52 registers.
Each register details.
Phase successively decreases 1, interruption of generation when counting up to 0 to the Timer timer weekly since an initial value.Its key property is: 32 bit wide counters; The timer initial value can be joined; Support free-running operation pattern and user definition operational mode.
The Timer timer has 3 registers commonly used.
| Register name | Address offset | Read/write | The replacement value | Describe |
| ?TimerLoadCount | 0x00 | Read/write | 32’b0 | The Timer value of being written into |
| ?TimerControlReg | 0x08 | Read/write | 3’b0 | The Timer control register |
| ?TimerEOI | 0x0C | Read | 1’b0 | Removing Timer interrupts |
3 register details commonly used.
Please refer to Fig. 5, be system's operational flow diagram.Behind the system initialization, start the Timer timer, after the Timer timer is finished counting, trigger and interrupt, enter the Timer interrupt service routine.Wherein the bus priority dynamic-configuration is finished in the Timer interrupt service routine.
Please refer to Fig. 6.Be Timer interrupt service routine flow process.At first remove and interrupt, in case retaining enters interrupt service routine after going out interrupt service routine immediately.Follow running priority level Algorithm of Dynamic Configuration.Restart the Timer timer at last.
Priority Algorithm of Dynamic Configuration 1 is carried out the priority configuration according to the internal storage access periodicity that comprises device request time-delay and external memory time-delay of each equipment and the product of each equipment real-time weight, and product value is big more, and priority is high more.
Please refer to Fig. 7.Be priority Algorithm of Dynamic Configuration flow process.At first read each equipment and block time-delay, can obtain by the related register that reads bus monitor.Then each equipment is blocked time-delay and its real-time multiplied by weight, the real-time weighted value is provided with in system initialization.According to product priority is set at last, product is big more, and priority is high more.
Please refer to Fig. 8.Be priority Algorithm of Dynamic Configuration implementing procedure figure.
Definition structure type struct_device in the priority Algorithm of Dynamic Configuration comprises structure component weight, delay, devicenum, respectively the real-time weight of indication equipment, obstruction time-delay and device number.Definition struct_device type array device[8].Its false code is:
struct?struct_device{
char?weight；
long?long?delay；
char?devicenum；
}；
struct?struct_device?device[8]；
A. each equipment of initialization, real-time weighted value scope is 0 to 255, device number is determined by hardware connection mode.If number of devices is less than 8, then the real-time weight with redundant equipment is made as 0, and device number is made as 8.Its false code is:
for(i＝0；i＜number；i++){
device[i].delay＝0；
device[i].weight＝weight[i]；
device[i].devicenum＝i；
}
for(i＝number；i＜8；i++){
device[i].delay＝0；
device[i].weight＝0；
device[i].devicenum＝8；
}
B. dispose the register TimerLoadCount of Timer timer, its value is made as (0.02 * Timer timer clock frequency), promptly per 20 milliseconds are carried out the priority dynamic-configuration one time.The register TimerControlReg of configuration Timer timer is made as 0x00000003 with its value, does not promptly shield Timer and interrupts, and the user definition operation starts the Timer timer.
C. enter the Timer interrupt service routine, read the register TimerEOI of Timer timer, remove Timer and interrupt.
D. obtain the obstruction time-delay of each equipment by reading register MACSSTATHx and MACSSTATLx, and with the real-time multiplied by weight.Its false code is:
device[i].delay＝get_delay(device[i].devicenum)；
product[i]＝device[i].delay*device[i].weight；
E. according to product the device array is resequenced, product is big more, before the corresponding array element ordering more.Its false code is:
for(i＝0；i＜number-1；i++){
for(j＝i+1；j＜number；j++){
if(product[i]＜product[j]){
temp＝device[i]；
device[i]＝device[j]；
device[j]＝temp；
}
}
}
F. determine priority controller bit wide according to number of devices, please refer to register MCTRL.According to bit wide and the ordering of device array element, each priority facility is set.Its false code is:
priority＝0；
for(i＝0；i＜number；i++)
priority|＝I＜＜(width*device[i].devicenum+4)；
*MCTRL&＝0x7；*MCTRL|＝priority；
G. repeating step b is to step f.
Priority Algorithm of Dynamic Configuration 2, according to the internal storage access periodicity that comprises device request time-delay and external memory time-delay of each equipment divided by the engineer's scale constant after with each equipment real-time weight addition and carry out that priority disposes and value is big more, priority is high more.
Please refer to Fig. 7.Be priority Algorithm of Dynamic Configuration flow process.At first read each equipment and block time-delay, can obtain by the related register that reads bus monitor.Then each equipment is blocked time-delay divided by behind the engineer's scale constant SCALE with its real-time weight addition, the real-time weighted value is provided with in system initialization.Last basis and priority and big more is set, priority is high more.
Please refer to Fig. 8.Be priority Algorithm of Dynamic Configuration implementing procedure figure.
Definition structure type struct_device in the priority Algorithm of Dynamic Configuration comprises structure component weight, delay, devicenum, respectively the real-time weight of indication equipment, obstruction time-delay and device number.Definition struct_device type array device[8].Its false code is:
struct?struct_device{
char?weight；
long?long?delay；
char?devicenum；
}；
struct?struct_device?device[8]；
A. each equipment of initialization, real-time weighted value scope is 0 to 255, device number is determined by hardware connection mode.If number of devices is less than 8, then the real-time weight with redundant equipment is made as 0, and device number is made as 8.Its false code is:
for(i＝0；i＜number；i++){
device[i].delay＝0；
device[i].weight＝weight[i]；
device[i].devicenum＝i；
}
for(i＝number；i＜8；i++){
device[i].delay＝0；
device[i].weight＝0；
device[i].devicenum＝8；
}
B. dispose the register TimerLoadCount of Timer timer, its value is made as (0.02 * Timer timer clock frequency), promptly per 20 milliseconds are carried out the priority dynamic-configuration one time.The register TimerControlReg of configuration Timer timer is made as 0x00000003 with its value, does not promptly shield Timer and interrupts, and the user definition operation starts the Timer timer.
C. enter the Timer interrupt service routine, read the register TimerEOI of Timer timer, remove Timer and interrupt.
D. obtain the obstruction time-delay of each equipment by reading register MACSSTATHx and MACSSTATLx, divided by behind the engineer's scale constant SCALE with the addition of real-time weight.Its false code is:
device[i].delay＝get_delay(device[i].devicenum)/SCALE；
sum[i]＝device[i].delay+device[i].weight；
E. basis and value are with device array rearrangement and big more, before the corresponding array element ordering more.Its false code is:
for(i＝0；i＜number-1；i++){
for(j＝i+1；j＜number；j++){
if(sum[i]＜sum[j]){
temp＝device[i]；
device[i]＝device[j]；
device[j]＝temp；
}
}
}
F. determine priority controller bit wide according to number of devices, please refer to register MCTRL.According to bit wide and the ordering of device array element, each priority facility is set.Its false code is:
priority＝0；
for(i＝0；i＜number；i++)
priority|＝I＜＜(width*device[i].devicenum+4)；
*MCTRL&＝0x7；*MCTRL|＝priority；
G. repeating step b is to step f.
Claims (10)
1. System on Chip/SoC bus priority dynamic-configuration device based on bus monitor, it is characterized in that: described System on Chip/SoC bus priority dynamic-configuration device comprises:
Initiate the overlapping periodicity of internal storage access, internal storage access number of times simultaneously, comprise the internal storage access periodicity of device request time-delay and external memory time-delay and four counters that comprise the internal storage access periodicity of device request time-delay in order to a plurality of equipment of accumulative total;
A timer;
And in order to the real-time weight of each equipment and the internal storage access time-delay of each equipment are done product or addition, described internal storage access is delayed time to the internal storage access periodicity that comprises device request time-delay and external memory time-delay or is comprised the internal storage access periodicity that device request is delayed time, and according to product or with size priority is set: product or and the high more priority dynamic-configuration module of big more then priority.
2. the System on Chip/SoC bus priority dynamic-configuration device based on bus monitor as claimed in claim 1, it is characterized in that: in the described counter in order to accumulative total internal storage access number of times, when choice of equipment signal and device ready signal simultaneously effectively, and when equipment state is not idle, then show the initiation internal storage access, this moment, this Counter Value increased by 1.
3. the System on Chip/SoC bus priority dynamic-configuration device based on bus monitor as claimed in claim 1 or 2, it is characterized in that: describedly be used for the counter that accumulative total comprises the internal storage access periodicity that device request time-delay and external memory delay time, when choice of equipment signal and device ready signal simultaneously effectively, and when equipment state is not idle, show equipment initiation internal storage access; If internal storage access finishes invalidating signal, show that then the Device memory visit do not finish, this moment this Counter Value weekly the phase increase by 1, it is effective to finish signal until internal storage access.
4. the System on Chip/SoC bus priority dynamic-configuration device based on bus monitor as claimed in claim 1 or 2, it is characterized in that: describedly be used for the counter that accumulative total comprises the internal storage access periodicity of device request time-delay, when choice of equipment signal and device ready signal simultaneously effectively, and when equipment state is not idle, show equipment initiation internal storage access; If the moderator OPADD is identical with the device request address, show that then this equipment obtains internal storage access power, the phase increase by 1 weekly of this Counter Value this moment, different until the moderator OPADD with the device request address.
5. the System on Chip/SoC bus priority dynamic-configuration device based on bus monitor as claimed in claim 3, it is characterized in that: describedly be used for the counter that accumulative total comprises the internal storage access periodicity of device request time-delay, when choice of equipment signal and device ready signal simultaneously effectively, and when equipment state is not idle, show equipment initiation internal storage access; If the moderator OPADD is identical with the device request address, show that then this equipment obtains internal storage access power, the phase increase by 1 weekly of this Counter Value this moment, different until the moderator OPADD with the device request address.
6. the System on Chip/SoC bus priority dynamic-configuration device based on bus monitor as claimed in claim 1 or 2, it is characterized in that: the described a plurality of equipment of accumulative total that are used for are initiated the counter of the overlapping periodicity of internal storage access simultaneously, when choice of equipment signal and device ready signal simultaneously effectively, and when equipment state is not idle, show equipment initiation internal storage access; If internal storage access finishes invalidating signal, show that then the Device memory visit do not finish; When two or more equipment are in the internal storage access unfinished state, show that then the visit of a plurality of Device memory is overlapping, this moment this Counter Value weekly the phase increase by 1, until having only one or do not have equipment to be in the internal storage access unfinished state.
7. the System on Chip/SoC bus priority dynamic-configuration device based on bus monitor as claimed in claim 3, it is characterized in that: the described a plurality of equipment of accumulative total that are used for are initiated the counter of the overlapping periodicity of internal storage access simultaneously, when choice of equipment signal and device ready signal simultaneously effectively, and when equipment state is not idle, show equipment initiation internal storage access; If internal storage access finishes invalidating signal, show that then the Device memory visit do not finish; When two or more equipment are in the internal storage access unfinished state, show that then the visit of a plurality of Device memory is overlapping, this moment this Counter Value weekly the phase increase by 1, until having only one or do not have equipment to be in the internal storage access unfinished state.
8. the System on Chip/SoC bus priority dynamic-configuration device based on bus monitor as claimed in claim 4, it is characterized in that: the described a plurality of equipment of accumulative total that are used for are initiated the counter of the overlapping periodicity of internal storage access simultaneously, when choice of equipment signal and device ready signal simultaneously effectively, and when equipment state is not idle, show equipment initiation internal storage access; If internal storage access finishes invalidating signal, show that then the Device memory visit do not finish; When two or more equipment are in the internal storage access unfinished state, show that then the visit of a plurality of Device memory is overlapping, this moment this Counter Value weekly the phase increase by 1, until having only one or do not have equipment to be in the internal storage access unfinished state.
9. the System on Chip/SoC bus priority dynamic-configuration device based on bus monitor as claimed in claim 5, it is characterized in that: the described a plurality of equipment of accumulative total that are used for are initiated the counter of the overlapping periodicity of internal storage access simultaneously, when choice of equipment signal and device ready signal simultaneously effectively, and when equipment state is not idle, show equipment initiation internal storage access; If internal storage access finishes invalidating signal, show that then the Device memory visit do not finish; When two or more equipment are in the internal storage access unfinished state, show that then the visit of a plurality of Device memory is overlapping, this moment this Counter Value weekly the phase increase by 1, until having only one or do not have equipment to be in the internal storage access unfinished state.
10. the System on Chip/SoC bus priority dynamic-configuration device based on bus monitor as claimed in claim 1 or 2, it is characterized in that: when addition is done in the internal storage access time-delay of the real-time weight of each equipment and each equipment, at first default coefficient is multiply by in the internal storage access time-delay of described each equipment and obtain intermediate value, described intermediate value has the identical order of magnitude with the real-time weight of described each equipment.
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| CN102012881B (en) | 2012-09-05 |
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