CN102012803A - Configurable matrix register unit for supporting multi-width SIMD and multi-granularity SIMT - Google Patents

Abstract

The invention relates to a configurable matrix register unit for supporting multi-width single instruction multiple data stream (SIMD) and multi-granularity single instruction multiple threads (SIMT). The configurable matrix register unit comprises a matrix register and a control register SR; the matrix register of which the size is N*N is divided into M*M blocks, wherein N is a positive integer and is the power of 2, and M is an integer which is more than or equal to 0 and is the power of 2; the block modes of the matrix register and the multi-thread numbers simultaneously processed by a vector processing unit are recorded in the control register; and the width of the control register is log2C+log2T, wherein C is the number of the number of the block modes of the matrix register, and T is the number of multi-thread modes which can be processed by a vector processor. The configurable matrix register unit has the advantages that: the principle is simple; the configurable matrix register unit is simple and convenient to operate; the block size and the thread number can be configured flexibly; the access to vector data in the mode of multi-width SIMD and multi-granularity SIMT is supported at the same time and the like.

Description

Configurable matrix register unit supporting multi-width SIMD and multi-granularity SIMT

technical field

The present invention mainly relates to the design field of vector registers in vector processors, in particular to a matrix register with configurable block size and thread number in vector processors to support single instruction stream multiple data streams (SIMD) and single The vector operation unit operating in the instruction stream multithreading (SIMT) mode performs multi-width and multi-granularity access to data.

Background technique

With the in-depth research of 4G wireless communication technology and video image processing technology, vector processors have been widely used. Rapidly evolving wireless communication protocols and video image processing algorithms require a large number of matrix operations, such as channel estimation, MIMO equalization, and DCT transformation. The parallel granularity of matrix operations in different algorithms is different, and the size of the matrix blocks processed by the algorithms is also different. Only when the vector processor provides efficient support for these matrix operations with different numbers and different block sizes, can it better adapt to this kind of data-intensive type applications to meet real-time data processing requirements.

The core algorithms of wireless communication protocols and video image processing usually exhibit data-level parallelism and thread-level parallelism at the same time. Vector processors for such applications usually use Very Long Instruction Word (VLIW), Single Instruction Multiple Data (SIMD) architecture, and will also provide support for Single Instruction Stream Multi-Threading (SIMT) technology to obtain sufficient parallel computing capabilities. The above two types of algorithms usually have the following characteristics: With the rapid evolution of the protocol, the length of the vectors processed by the algorithm is also changing, and at the same time, the thread-level parallelism that can be developed in the algorithm is also changing. For example, in the 3G wireless communication protocol, the evolution of the protocol makes the number of antennas of the base station and the handheld end constantly changing, which leads to the constant change of the vector length in the channel equalization matrix, which means that the vector data width that the vector processing unit can process And the number of threads processed at the same time is changing. The above characteristics put forward strong requirements on whether the vector processor can provide sufficient and effective support for multi-width SIMD processing and multi-granularity SIMT processing from the architecture level. Therefore, the present invention proposes a matrix register with configurable block size and thread number, which can meet the vector operation requirements of different parallel granularities and block sizes in the algorithm.

The storage unit array of the matrix register is generally composed of N*M (M, N are integers greater than 1) storage units, and the bit width of each storage unit is generally 4, 8, 12, 16, 32. It can be regarded as composed of N row vector registers VR ₀ -VR _N-1 or M column vector registers CVR ₀ -CVR _M-1 , and N and M are usually powers of 2. Each row vector register contains M elements (storage units) E _{i, 0} -E _{i, M-1} (i=0, 1, 2...N-1), and each column vector register contains N elements E _{0 , i} -E _{M-1, i} (i=0, 1, 2...M-1). The matrix register completes the read and write of row and column vectors under the control of read and write enable, read and write addresses and row and column selection signals.

Existing research provides access to block data of a fixed size in the above-mentioned matrix registers. These technologies read and write a row vector or a column vector of the matrix at a time. The length of the vector is fixed. When the length of the vector is greater than or less than the fixed length, Usually, multiple short vectors are combined into one long vector for parallel processing, or a long vector is split into several short vectors for step-by-step processing, which cannot flexibly handle matrix data of different sizes, and does not support multi-width SIMD processing. It also does not support simultaneous access to multiple matrix data in the way of multi-granularity SIMT, neither can obtain enough flexibility, nor can it develop enough parallelism, especially thread-level parallelism.

In summary, how to provide efficient and flexible processing of matrix data in vector processors, provide flexible and sufficient parallel operands for multi-granularity SIMT and multi-width SIMD processing of vector processors, and improve the performance of vector processors and array processors. The efficiency of parallel processing to meet the needs of large-scale matrix operations in applications such as wireless communication and image processing is still a hot issue in this field.

Contents of the invention

The technical problem to be solved by the present invention lies in: aiming at the technical problems existing in the prior art, the present invention provides a simple principle, easy operation, flexible configuration of block size and number of threads, and simultaneous support for multi-width SIMD and multi-granularity SIMT mode access Matrix register unit for vector data.

In order to solve the problems of the technologies described above, the present invention adopts the following technical solutions:

A configurable matrix register unit supporting multi-width SIMD and multi-granularity SIMT, characterized in that: it includes a matrix register and a control register SR, and the matrix register of the size N*N is divided into M*M blocks, wherein N is a positive integer and is a power of 2, and M is an integer greater than or equal to 0 and is a power of 2; the matrix register block mode and the number of multi-threads processed by the vector processing unit are recorded in the control register, and the width of the control register is log ₂ C+log ₂ T, where C is the number of block modes of the matrix register, and T is the number of multi-thread modes that the vector processor can handle.

As a further improvement of the present invention:

When M is 0, it means that the matrix register is not divided into blocks, and the vector operation unit can access one row vector or column vector in the matrix register at a time; when M is not 0, the vector operation unit accesses according to the number of threads processed at the same time One or more sub-row vectors or sub-column vectors of the same length in the matrix register, and these same-length sub-row vectors or sub-column vectors come from different block matrices.

When the vector operation part accesses the matrix register, the address decoding logic unit decodes according to the content of the control register SR, the read-write address and the row and column selection signal, selects a row vector or column vector of the matrix register to read and write, and Or select one or more sub-row vectors or sub-column vectors to read and write.

The control register SR is an independent control register, or stored in reserved bits of other control registers, and the length of reserved bits of other control registers is an integer greater than log ₂ C+log ₂ T.

Compared with the prior art, the present invention has the advantages of: the present invention supports multi-width SIMD and multi-granularity SIMT modes to access the matrix register unit of vector data, simple in principle, easy to operate, flexible in configuration of block size and number of threads, and can be used in vector processing The processor can efficiently and flexibly process matrix data, and provide flexible and sufficient parallel operands for the multi-granularity SIMT and multi-width SIMD processing of vector processors, thereby improving the parallel processing efficiency of vector processors and array processors and satisfying Applications such as wireless communication and image processing require large-scale matrix operations.

Description of drawings

Fig. 1 is the overall structural representation of matrix register of the present invention;

Fig. 2 is a schematic diagram of the architectural framework of a vector processor;

Fig. 3 is the structural representation of SR register among the present invention;

Fig. 4 is a schematic diagram of the storage cell array structure of the matrix register of the present invention;

Fig. 5 is a schematic diagram of the row address space when the matrix register of the present invention is not divided into blocks;

Fig. 6 is a schematic diagram of the column address space when the matrix register of the present invention is not divided into blocks;

Fig. 7 is a schematic diagram of the downlink address space in the single-thread mode when the matrix register of the present invention is divided into blocks;

Fig. 8 is a schematic diagram of the following address space in the single-threaded mode when the matrix register of the present invention is divided into blocks;

Fig. 9 is a schematic diagram of the downlink address space in the M-thread mode when the matrix register of the present invention is divided into blocks;

Fig. 10 is a schematic diagram of the following address space in the M-thread mode when the matrix register of the present invention is divided into blocks;

Fig. 11 is a schematic diagram of the decoding path in the present invention.

Detailed ways

The present invention will be further described in detail below in conjunction with the accompanying drawings and specific embodiments.

As shown in FIG. 1 , it is a schematic diagram of the overall structure of the matrix register of the present invention. The configurable matrix register unit supporting multi-width SIMD and multi-granularity SIMT of the present invention includes a matrix register and a control register SR.

When the read and write enable signal is valid, the address decoding logic unit performs decoding under the control of the row and column selection signal and the control register SR according to the content of the read and write address, and selects a row vector or column vector of the matrix register to read and write. Or select one or more sub-row vectors or sub-column vectors to read and write. The matrix register is composed of N*N storage unit arrays, each unit has a bit width of W and a storage capacity of (N*N*W) bits. By configuring some fields of the control register SR, the matrix register can be divided into blocks. When the content in the control register SR represents that the block mode of the matrix register is M*M, it means that the matrix register is divided into M sub-blocks by rows and columns at the same time, and is divided into M*M sub-blocks, and the size of each sub-block is (N /M)*(N/M), M is generally 0, 2, 4, 8..., and M does not exceed N/2. When M is 0, it means that the matrix register is not divided into blocks (also called block mode is 0*0), when M is not 0, each row vector register or column vector register is logically divided into M sub-row vector registers or sub-column vector registers, and each sub-row vector register or sub-column vector register contains N/M storage units, at this time, the length of the read and write unit of the vector operation unit to the matrix register is the length of the sub-row vector register or the sub-column vector register, and one or more sub-row vectors or sub-column vectors can be selected for reading each time Write. In the present invention, the functional parts of the vector operation unit can access the matrix registers in the same way as accessing ordinary registers, and the matrix registers also provide the column access function, and can meet the vector read and write of different vector lengths, and also support SIMT access method. The maximum bandwidth of each read and write of the matrix register is N*W bits.

FIG. 3 is a schematic diagram of the structure of the control register SR in the present invention. The block mode of the current matrix register and the number of threads that the arithmetic unit is processing at the same time are recorded in the control register SR. In order to reduce the cost and improve the reusability of design, the present invention uses SR as the control register of the processor, and the programmer can pass Existing instructions for accessing the control registers are used to access the SR, and no additional instructions are required. The bit width of valid data in SR is the smallest integer greater than (log ₂ C+log ₂ T) (C is the number of block modes of the matrix register, T is the number of multi-thread modes that the vector processor can handle, C and T are integer greater than 1). SR can exist independently as a dedicated control register, or the control register in the processor generally has reserved bits, if the number of reserved bits in the original control register of the processor is greater than or equal to log ₂ C+log ₂ T, it can be There is no need to add an additional SR register, otherwise, a control register SR needs to be added. Regardless of the situation, the programmer can access the SR through the existing instructions for accessing the control register, so the dynamic configuration of the SR can be realized without adding additional instructions.

Each access of the vector processing unit to the matrix register needs to provide three signals: read and write enable, read and write address, row and column selection signal. The address decoding logic unit decodes according to the content of the control register SR, read and write addresses, and row and column selection signals, selects a row vector or column vector of the matrix register for reading and writing, and can also select one or more sub-row vectors or sub-column vectors to read and write.

The invention designs a complete address mapping scheme. Under different block mode and thread mode, the matrix register presents different address views, and these address views provide complete and flexible access methods for programmers. The rules of the address mapping scheme are as follows: inter-blocks follow the order of first up, then down, then left, then right, the row addresses within the block follow the order of first up, then down, and the column addresses follow the order of first left, then right, and the number of threads increases linearly. When L(L≤max(M)), L consecutive blocks in the row direction share a column vector address space, and L consecutive blocks in the column direction share a row vector address space, that is, when the number of threads is L, the vector processing The unit can simultaneously access L sub-row vectors or L sub-column vectors of the matrix register, each sub-row vector or sub-column vector is processed by V vector processing units, and V is the length of the sub-row vector or sub-column vector.

Fig. 2 is the architectural framework of the vector processor in the present invention. A vector processor is generally composed of N parallel processing units (PE), each processing unit has i functional units, these functional units can be MAC, ALU, division, shifting units, etc., and each functional unit can perform matrix processing as needed Registers are read and written. N PEs constitute a SIMD processing method, and each PE generally adopts a VLIW structure, and multiple functional components perform parallel operations. The size of the cell array of the matrix register is N*N, logically forming N row vector registers VR ₀ -VR _N-1 and N column vector registers CVR ₀ -CVR _N-1 . Each row vector register VR _i includes N storage units E _{i, 0} -E _{i, N-1} (i=0, 1, 2...N-1), and each column vector register CVR _i includes N storage units E _0,i -E _N-1,i (i=0, 1, 2...N-1). The matrix register is designed as a multi-port read and write mode, and can provide source operands for multiple functional components of N PEs at the same time, and can also support data writing of multiple functional components of N PEs.

Fig. 4 is a schematic diagram of the structure of the storage cell array of the matrix register in the present invention. The storage unit array of the matrix register generally consists of N*N storage units, and N is usually a power of 2. The bit width of each storage unit is W, and W is generally 4, 8, 12, 16, 32. Logically, the array can be regarded as N row vector registers VR ₀ -VR _N-1 or N column vector registers CVR ₀ -CVR _N-1 , and each row vector register contains N elements (storage units) E _{i , 0} -E _{i, N-1} (i=0, 1, 2...N-1). Taking VR ₀ as an example, the row vector register includes storage units E _0,0 -E _0,N-1 . The memory cell array is divided into N memory cell columns of N*W bits by column, and each column is composed of N elements of the same column. The N memory cell columns are in one-to-one correspondence with the N column vector registers CVR ₀ -CVR _N−1 , and are used to realize the access function of the corresponding column vector registers. Taking CVR _N-1 as an example, the column vector register includes the last elements E _{i, N-1} (i=0, 1, 2...N-1) of all row vector registers VR ₀ -VR _N-1 .

Fig. 5 is a schematic diagram of the row address space when the matrix register of the present invention is not divided into blocks. When the blocking mode field in the SR indicates that the matrix register is not blocked, the matrix register only supports single-threaded operations. The matrix register is composed of N row vector registers, and each row vector register includes N storage units E _i,0 -E _i,N-1 (i=0,1,2...N-1). The functional parts of the vector operation unit can read and write a row vector register, and the data bandwidth of each read and write is N*W bits. The address of the row vector register increases linearly from top to bottom. The vector operation unit can access different row vectors of the matrix register according to different row addresses.

Fig. 6 is a schematic diagram of the column address space when the matrix register of the present invention is not divided into blocks. When the blocking mode field in the SR indicates that the matrix register is not blocked, the matrix register only supports single-threaded operations. The matrix register is made up of N column vector registers, and each column vector register contains N storage units E _{0, i} -E _{N-1, i} (i=0, 1, 2...N-1) the function of the vector operation unit The component can read and write to a column vector register, and the data bandwidth of each read and write is N*W bits. The addresses of the column vector registers are addressed linearly from left to right. The vector operation unit can access different column vectors of the matrix register according to different column addresses.

FIG. 7 is a schematic diagram of the downstream address space in the single-thread mode when the matrix register is divided into blocks according to the present invention. When the block mode field in the SR indicates that the matrix register block mode is M*M and the thread mode field indicates that the current operation is a single-thread operation, the matrix register consists of N*M sub-row vector registers, and each sub-row vector register contains N /M storage units E _i,0 -E _i,N/M-1 (i=0, 1, 2...(N-1)*M). The functional parts of the vector operation unit can read and write a sub-row vector register, and the data bandwidth of each read and write is (N/M)*W bits. The addressing of the sub-row vector register follows the following rules: the order between blocks is first up, then down, then left, then right, and the addressing within a block is linearly increased from top to bottom. The vector operation unit can access different sub-row vectors of the matrix register according to different row addresses. When the values of M are different, support for SIMD operations of different lengths is realized, that is, multi-width SIMD access is supported.

FIG. 8 is a schematic diagram of the following address space in the single-thread mode when the matrix register is divided into blocks according to the present invention. When the block mode field in the SR indicates that the matrix register block mode is M*M and the thread mode field indicates that the current operation is a single-thread operation, the matrix register consists of N*M sub-column vector registers, and each sub-column vector register contains N /M memory cells E _0,i -E _{N/M-1. i} (i=0, 1, 2...(N-1)*M). The functional parts of the vector operation unit can read and write a sub-column vector register, and the data bandwidth for each read and write is (N/M)*W bits. The addressing of the sub-column vector register follows the following rules: the order between blocks is first up, then down, then left, then right, and the addressing within a block is linearly increased from left to right. The vector operation unit can access different sub-column vectors of the matrix register according to different column addresses. When the values of M are different, support for SIMD operations of different lengths is realized, that is, multi-width SIMD access is supported.

FIG. 9 is a schematic diagram of the downstream address space in the M-thread mode when the matrix register is divided into blocks according to the present invention. When the block mode field in the SR indicates that the block mode of the matrix register is M*M and the thread mode field indicates that the current operation is a multi-thread (the number of threads is L) operation, the matrix register is composed of N*M/L sub-row vector registers , each sub-row vector register includes N/M storage units E _i,0 -E _i,N/M-1 (i=0,1,2...(N-1)*M/L). The functional parts of the vector operation unit can read and write to L sub-row vector registers, and the data bandwidth of each read and write is (L*N/M)*W bits. The addressing of sub-row vector registers follows the following rules: between blocks follow the sequence of first up, then down, then left, then right; within a block, addressing increases linearly from top to bottom; consecutive L blocks in the column direction share a row In the address space, the vector operation unit can access L different sub-row vectors of the matrix register according to different row addresses. These L different sub-row vectors share the same address, but come from different matrix data blocks, that is, L different sub-row vectors A row vector is essentially a multi-threaded data access. Figure 9 shows the sub-row vector addressing mode when L is equal to M. When the values of M are different, support for SIMD operations of different lengths is realized, that is, multi-width SIMD access is supported. When the value of L is different, thread-level parallelism of different granularities is realized, that is, the access mode of multi-granularity SIMT is supported.

FIG. 10 is a schematic diagram of the following address space in the M-thread mode when the matrix register is divided into blocks according to the present invention. When the block mode field in the SR indicates that the block mode of the matrix register is M*M and the thread mode field indicates that the current operation is a multi-thread (the number of threads is L) operation, the matrix register is composed of N*M/L sub-column vector registers , each sub-column vector register includes N/M storage units E _0,i -E _N/M-1,i (i=0,1,2...(N-1)*M/L). The functional parts of the vector operation unit can read and write L sub-column vector registers, and the data bandwidth of each read and write is (L*N/M)*W bits. The addressing of the sub-column vector registers follows the following rules: the order between blocks is first up, then down, then left, then right, within the block, the addressing is increased linearly from left to right, and the consecutive L blocks in the row direction share a column In the address space, the vector operation unit can access L different sub-column vectors of the matrix register according to different row addresses. These L different sub-column vectors share the same address, but come from different matrix data blocks, that is, L different sub-column vectors. A column vector is essentially a multi-threaded data access. Figure 10 shows the sub-column vector addressing mode when L is equal to M. When the values of M are different, support for SIMD operations of different lengths is realized, that is, multi-width SIMD access is supported. When the value of L is different, thread-level parallelism of different granularities is realized, that is, the access mode of multi-granularity SIMT is supported.

Fig. 11 is a schematic diagram of the decoding path of the matrix register of the present invention. The decoding path is composed of address decoding logic, read and write data buffer unit and read and write data bus. When the vector processing unit reads and writes the matrix register, the address decoding logic performs address decoding according to the read and write addresses, row and column selection signals, and the content of SR, and selects one or more row/column vectors, or selects one or more sub-rows / sub-column vector to read and write. When the matrix register is read, when a certain storage unit is selected by the decoding logic, the content of the storage unit is read out and placed on the read data bus of the row where the storage unit is located, and then sent to the read data buffer. The read data buffer unit organizes the data of different storage units into a vector form and returns it to the vector operation unit. When performing a write operation on the matrix register, the write data buffer unit splits the vector data from the vector operation unit into multiple data to be written to different storage units. When a certain storage unit is selected by the decoding logic, the content to be written into the storage unit is placed on the write data bus of the row where the storage unit is located, and then written into the storage unit when the clock is valid.

The above are only preferred implementations of the present invention, and the protection scope of the present invention is not limited to the above-mentioned embodiments, and all technical solutions under the idea of the present invention belong to the protection scope of the present invention. It should be pointed out that for those skilled in the art, some improvements and modifications without departing from the principle of the present invention should be regarded as the protection scope of the present invention.

Claims (4)

1. A configurable matrix register unit that supports multi-width SIMD and multi-granularity SIMT, is characterized in that: comprise matrix register and control register SR, the matrix register of described size N*N is divided into M*M block, and wherein N is positive An integer and a power of 2, M is an integer greater than or equal to 0 and a power of 2; the matrix register block mode and the number of multithreads processed by the vector processing unit are recorded in the control register, and the width of the control register is log ₂ C+log ₂ T, where C is the number of block modes of the matrix register, and T is the number of multi-thread modes that the vector processor can handle. 2. The configurable matrix register unit supporting multi-width SIMD and multi-granularity SIMT according to claim 1 is characterized in that: when M is 0, it means that the matrix register is not divided into blocks, and the vector operation unit can access the matrix register at every turn A row vector or column vector in ; when M is not 0, the vector operation unit accesses one or more sub-row vectors or sub-column vectors of the same length in the matrix register according to the number of threads processed at the same time, these same length The sub-row or sub-column vectors of are from different block matrices. 3. The configurable matrix register unit supporting multi-width SIMD and multi-granularity SIMT according to claim 2, is characterized in that: when the vector operation part accesses the matrix register, the address decoding logic unit is based on the matrix register SR Content, read and write addresses, and row and column selection signals are decoded, and a row vector or column vector of the matrix register is selected for reading and writing, or one or more sub-row vectors or sub-column vectors are selected for reading and writing. 4. The configurable matrix register unit supporting multi-width SIMD and multi-granularity SIMT according to claim 1, 2 or 3, characterized in that: the control register SR is an independent control register, or is stored in other control registers In the reserved bits of the other control registers, and the length of the reserved bits of other control registers is an integer greater than log ₂ C+log ₂ T.

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