CN102005450A - Electrostatic discharge protection structure applied to VDMOS (Vertical Diffusion Metal Oxide Semiconductor) device - Google Patents

Abstract

The invention discloses an ESD protection structure applied to a VDMOS device. The VDMOS device includes an N+ substrate, an N- epitaxial layer and a gate oxide layer stacked in sequence from bottom to top. The ESD protection structure is formed by injecting The P+ doped region below the oxygen layer, the doped polysilicon arranged above the gate oxide layer, and the gate oxide layer between the P+ doped region and the doped polysilicon, and the doped polysilicon consists of n+1 N+ implanted regions Composed of n P-implantation regions, all N+ implantation regions and P-implantation regions are arranged along the same direction and arranged at intervals from each other, n is a natural number greater than 1. The ESD protection structure of the present invention is arranged on the gate oxide layer of the VDMOS device, and the P+ doped region does not need to be adjusted before the growth step of the field oxide layer of the VDMOS device, so it can be compatible with the manufacturing process of the VDMOS device without the ESD protection structure, thereby improving the Process operability and controllability.

Description

An Electrostatic Discharge Protection Structure Applied to VDMOS Devices

technical field

The invention relates to the field of semiconductor power devices and their manufacture, in particular to an electrostatic discharge protection structure applied to VDMOS devices.

Background technique

Power MOS field effect transistor is a new generation of power electronic switching device developed on the basis of MOS integrated circuit technology, which is used to meet the requirements of high voltage and high current for power electronic equipment. Since the birth of the new vertical conductive double-diffused VDMOS (Vertical Double-diffused Metal Oxide Semiconductor) structure, power MOSFET devices have developed rapidly. VDMOS has the advantages of both bipolar transistors and ordinary MOS devices. It has the characteristics of large input impedance, high withstand voltage, low on-resistance, low driving power, fast switching speed, and high operating frequency. Therefore, it is widely used in switching power supplies, automobiles, etc. Electronics, motor speed control, motor drive, audio amplifier, high-frequency oscillator and other fields have broad development and application prospects. The conventional VDMOS structure is shown in Figure 1. It includes drain electrode 11 , N+ substrate 12 , N- epitaxial layer 13 , P-body region 14 , P+ region 15 , N+ source region 16 , gate oxide layer 17 , polysilicon gate electrode 18 and metal source electrode 19 . G, D, and S represent the gate, drain, and source of the device, respectively.

However, with the continuous improvement of the technology level, the size of VDMOS devices continues to shrink, and the gate oxide layer becomes thinner and thinner, which greatly increases the probability of devices being damaged by ESD (Electro-Static Discharge). Therefore, improving the electrostatic discharge protection ability of VDMOS devices has a non-negligible effect on improving product reliability. The failures caused by ESD include two types: destructive failures and latent failures. Destructive failure will lead to breakdown of the oxide layer, PN junction, and even insulation layer of the device, resulting in complete loss of function of the device and failure to work normally. Although the potential failure will not directly destroy the functionality of the device, it will cause damage inside the device, thereby weakening the ability of the device to resist electrical overstress, shortening the working life of the device, etc., thereby weakening the reliability of its application circuit.

Currently, ESD structures applied to VDMOS devices have attracted extensive research. Commonly used ESD protection structures include SCR (silicon controlled silicon), GGNMOS (gate-grounded NMOS), GGPMOS (gate-grounded PMOS), diodes formed of polysilicon/bulk silicon, body silicon diodes, and resistors. The SCR, GGNMOS, and GGPMOS structures are more complex in process implementation, and it is difficult to be compatible with the VDMOS process, and at the same time, it will cause an increase in device manufacturing costs. Therefore, such ESD protection structures are often used in I/O protection structures of integrated circuits, but are rarely used in discrete components. ESD protection structures such as diodes formed of polysilicon/bulk silicon and bulk silicon diodes are relatively simple to implement, but there are disadvantages such as large drain-source current, obvious parasitic effects, and large substrate coupling noise, which will cause damage to the device and is not conducive to the protection of the device. normal work. The use of polysilicon diodes as the ESD protection structure of VDMOS devices has gradually become the current mainstream trend. The polysilicon diode protection structure not only has strong robustness, but also effectively reduces the leakage current because the structure is separated from the bulk silicon, eliminating substrate coupling noise and parasitic effects.

Commonly used polysilicon diode protection structures are shown in Figure 2. Including N+ substrate 12, N- epitaxial layer 13, P+ doped region 21, field oxygen layer 22 (thick oxide layer, generally thicker than 5000A), polysilicon 23, 24, wherein 23 is the cathode of polysilicon diode (N+ doped region ), 24 is the anode (P-doped region) of the polysilicon diode. The cathode is connected to the gate electrode (ie, G pole) of the VDMOS device, and the anode is connected to the source electrode (ie, S pole). When the VDMOS device works normally, the polysilicon diode is in the off state, which will not affect the potential on the gate and source electrodes. However, when an instantaneous high voltage is generated between the gate and source electrodes due to static electricity, the polysilicon diode will break down and quickly discharge the electrostatic current to clamp the gate-source voltage, thereby preventing the gate oxide layer from being struck by the instantaneous high voltage. wear. And when the gate-source of the VDMOS device is subjected to a high negative voltage instantaneous impact, the diode conducts forward and discharges the electrostatic current.

Although the commonly used polysilicon diode protection structure (as shown in Figure 2) can better protect the gate oxide layer, since the structure is made on the field oxide, it has the problem of incompatibility with the mainstream VDMOS process. At present, the first step in the manufacturing process of a VDMOS device without an ESD protection structure is to firstly perform field oxygen growth and etching. The ESD protection structure is generally made in the cell area inside the field limiting ring. In order to ensure a certain drain-source breakdown voltage, P+ impurities must be implanted under the field oxygen layer of the polysilicon diode. Therefore, if a polysilicon diode is to be manufactured, the current mature VDMOS device manufacturing process must be adjusted, and the P+ implantation must be adjusted before the growth and etching steps of the field oxide layer. However, this will bring problems such as the difficulty in precise control of the structure of the VDMOS device when making the field limiting ring, resulting in a large error between the actual tape-out effect and the design value.

Contents of the invention

The invention provides an ESD protection structure applied to VDMOS devices, the structure technology is easy to realize, compatible with the VDMOS device technology, and the manufacturing cost is low.

An ESD protection structure applied to a VDMOS device, the VDMOS device includes an N+ substrate, an N- epitaxial layer and a gate oxide layer stacked sequentially from bottom to top, and the ESD protection structure is composed of The P+ doped region, the doped polysilicon disposed above the gate oxide layer, and the gate oxide layer between the P+ doped region and the doped polysilicon, the doped polysilicon consists of n+1 N+ implanted regions and n P - the composition of the implanted regions, all the N+ implanted regions and the P- implanted regions are arranged along the same direction and arranged at intervals from each other, and n is a natural number greater than 1.

Each group of consecutively arranged N+ injection regions, P- injection regions and N+ injection regions forms an NPN structure. The first-level NPN structure is equivalent to two reverse-biased diodes connected to the anode. The above-mentioned ESD protection structure includes multiple NPN structures. A plurality of reverse-biased diodes with anodes connected in series. The more NPN stages, the higher the turn-on voltage of the ESD protection structure. The number of stages n is selected according to design requirements, and n is preferably 2-10. The turn-on voltage of the ESD protection structure is required to be less than the intrinsic breakdown voltage of the gate oxide layer, and greater than the gate-source bias voltage for normal operation of the VDMOS device. The two outermost N+ injection regions of doped polysilicon are respectively connected to the gate electrode and source electrode of the VDMOS device. When the gate electrode or source electrode of the device is impacted by a forward or reverse ESD high voltage pulse, the ESD protection structure will It can effectively clamp the gate-source voltage, discharge the static current, and avoid the breakdown of the gate oxide layer.

The P+ doped region is formed by ion-implanted boron, and this region forms a body diode with the N- epitaxial layer, which ensures that the ESD protection structure has the same breakdown voltage as other regions such as the cell region, so as to avoid premature An avalanche breakdown occurs. The thickness of the P+ doped region is preferably 3.0-4.5um, and its doping concentration is preferably 1E19-1E20cm ^-3 .

The thickness of the gate oxide layer affects electrical parameters such as threshold voltage and switching speed of the device. VDMOS devices with different withstand voltages have different gate oxide layer thicknesses. For devices with a withstand voltage of 100V-700V, the thickness of the gate oxide layer is generally between 50nm and 100nm.

The thickness of the doped polysilicon is preferably 400nm-600nm.

The N+ implantation region and the P- implantation region are strip-shaped or circular, and the doping concentrations of the N+ implantation region and the P- implantation region are preferably 1E19˜1E20 cm ⁻³ and 1E16˜4E16 cm ⁻³ respectively.

The ESD protection structure of the present invention is arranged on the gate oxide layer of the VDMOS device, and the P+ doped region does not need to be adjusted before the growth step of the field oxide layer of the VDMOS device, so it can be compatible with the VDMOS device manufacturing process without the ESD protection structure, improving the Process operability and controllability.

The ESD protection structure of the present invention has the advantages of simple structure, strong process operability, good robustness, small leakage current, stability and reliability, etc., and can be widely used in various power VDMOS devices or other products.

Description of drawings

Figure 1 is a cross-sectional view of a conventional VDMOS structure;

Figure 2 is a cross-sectional view of a commonly used polysilicon diode protection structure;

Fig. 3 is the sectional view of VDMOS device ESD protection structure of the present invention;

FIG. 4 is a top view of the ESD protection structure shown in FIG. 3;

Fig. 5 is the equivalent circuit diagram of ESD protection structure of the present invention;

Fig. 6 is the HBM test result of the ESD protection structure of the present invention.

Detailed ways

As shown in Fig. 1, a kind of VDMOS device comprises stacked N+ substrate 12 and N-epitaxial layer 13, and N-epitaxial layer 13 is provided with P-body region 14 and gate oxide layer 17, in P-body region 14 A separate P+ region 15 and N+ source region 16 are provided, and a metal source electrode 19 connecting the P+ region 15 and N+ source region 16 is provided on the surface of the P-body region 14. The gate oxide layer 17 is covered with a polysilicon gate electrode 18, The structure is the same as the traditional VDMOS device structure.

The N+ substrate 12 has a high doping concentration of about 5E18cm ⁻³ , a very low resistivity and a very small series resistance, and is used as the lead-out position of the drain electrode of the VDMOS device.

The thickness and resistivity of the N- epitaxial layer 13 determine the drain-source breakdown voltage of the entire VDMOS device, and a large proportion of the total resistance of the device is formed by the resistance of the epitaxial layer. For example, for 100V-200V VDMOS devices, the epitaxial layer resistance accounts for more than 70% of the total resistance. For 300V-500V VDMOS devices, the epitaxial layer resistance accounts for more than 80% of the total resistance. For VDMOS devices above 600V, the epitaxial layer resistance accounts for more than 90% of the total resistance. In this embodiment, the thickness of the N- epitaxial layer 13 is 40um, and the resistivity is 14Ω·cm.

As shown in Figure 3 and Figure 4, an ESD protection structure applied to the above-mentioned VDMOS device, the structure is set on the epitaxial layer 13 of the VDMOS device, mainly including P+ doped region 31, gate oxide layer 17, and P+ doped The impurity region 33 corresponds to the doped polysilicon on the gate oxide layer 17 and the gate oxide layer 17 between them.

In this embodiment, the thickness of the gate oxide layer 17 is 100nm, and the intrinsic breakdown voltage is 80V; the thickness of the P+ doped region 21 is 3.6um, and the doping concentration is 1E19 ⁻³ .

The doped polysilicon is composed of 8 N+ implant regions 32 and 7 P- implant regions 33 (the doped region in the central region of FIG. 3 is omitted), and the N+ implant regions 32 and the P- implant regions 33 are strip-shaped and arranged at intervals. Therefore, both outermost sides are N+ implantation regions. In this embodiment, the thickness of the doped polysilicon is 500nm, and the doping concentrations of the N+ implanted region and the P- implanted region are preferably 1E19cm ^-3 and 4E16cm ^-3 respectively

In this way, each continuous N+ implantation region, P- implantation region and N+ implantation region constitutes an NPN structure, and the first-level NPN structure is equivalent to two reverse-biased diodes connected to the anode, and the above-mentioned doped polysilicon is equivalent to a seven-level NPN structure. Of course, they can be in other arbitrary shapes, as long as they are arranged in the same direction and arranged at intervals from each other. The two outermost N+ injection regions of the ESD protection structure are respectively provided with lead holes 41 for connecting the gate electrode and the source electrode of the VDMOS device.

The equivalent circuit of the above ESD protection structure is shown in FIG. 5 , wherein G, D, and S represent gate electrode, drain electrode, and source electrode, respectively. The turn-on voltage V _trig of the ESD protection structure is greater than the maximum gate-source bias voltage V _gs(max) of the VDMOS device, and smaller than the breakdown voltage BV _oxide of the gate oxide layer, that is, V _gs(max) <V _trig <BV _oxide .

When the device is working normally, the gate-source bias voltage is less than the turn-on voltage of the ESD protection structure, and the ESD protection structure is in a closed state, which will not affect the potential on the gate electrode and the source electrode. When the high-voltage pulse of ESD is impacted in the direction or reverse direction, the ESD protection structure will be turned on, and the ESD current will be quickly discharged to clamp the gate-source voltage, effectively preventing the gate oxide layer 17 from being broken down.

After testing, the forward turn-on voltage of the ESD protection structure (positive voltage is applied to the gate, the source is grounded) is 39V, the reverse turn-on voltage (positive voltage is applied to the source, the gate is grounded) is 40V, and the forward and reverse leakage current Both are less than 30nA. At the same time, the HBM (Human Body Charged Discharge Model) test results of the protective structure are shown in Figure 6, and the HBM is greater than 7KV (4.9A×1.5KV=7.35KV), reaching the use standard.

Claims (9)

1. esd protection structure that is applied to the VDMOS device; described VDMOS device comprises N+ substrate, N-epitaxial loayer and the grid oxide layer that stacks gradually from bottom to up; it is characterized in that: described esd protection structure constitutes by annotating the P+ doped region in the grid oxide layer below, the doped polycrystalline silicon of being located at the grid oxide layer top and the grid oxide layer between P+ doped region and the doped polycrystalline silicon; described doped polycrystalline silicon is made up of n+1 N+ injection region and n P-injection region; all N+ injection regions and P-injection region are along same direction arrangement and apart from one another by setting, n is the natural number greater than 1.

2. esd protection structure according to claim 1 is characterized in that: described n is 2～10.

3. esd protection structure according to claim 1 is characterized in that: the thickness of described P+ doped region is between 3.0～4.5um.

4. esd protection structure according to claim 1 is characterized in that: the doping content of described P+ doped region is 1E19～1E20cm ^-3

5. esd protection structure according to claim 1 is characterized in that: the thickness of described grid oxide layer is 50nm～120nm.

6. esd protection structure according to claim 1 is characterized in that: the thickness of described doped polycrystalline silicon is 400nm～600nm.

7. esd protection structure according to claim 1 is characterized in that: described N+ injection region doping content is 1E19～1E20cm ^-3

8. esd protection structure according to claim 1 is characterized in that: the doping content of described P-injection region is 1E16～4E16cm ^-3

9. esd protection structure according to claim 1 is characterized in that: described N+ injection region and P-injection region are bar shaped or circle.

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