CN101995546B - Automatic testing system and method for programmable logic devices based on boundary scan - Google Patents
Automatic testing system and method for programmable logic devices based on boundary scan Download PDFInfo
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Abstract
本发明属于电子技术领域，具体为一种基于边界扫描的可编程逻辑器件自动测试系统与方法。所述测试方法包括芯片配置文件的生成、下载配置FPGA芯片、测试向量的生成和加载，以及测试结果比较等，并构建了相应的测试系统，全部实现自动化。本发明由软件自动生成用户待测项目的测试向量，结合JTAG自动下载测试软件实现对用户电路的硬件功能在线测试。使用脚本化测试环境，使得一系列繁琐的人工测试操作转化为全自动的软件流程，大大提升测试的速度和准确性。
The invention belongs to the field of electronic technology, in particular to a boundary scan-based programmable logic device automatic testing system and method. The test method includes generation of chip configuration files, download and configuration of FPGA chips, generation and loading of test vectors, comparison of test results, etc., and a corresponding test system is constructed to realize automation. The invention automatically generates the test vector of the user's item to be tested by software, and realizes the online test of the hardware function of the user's circuit in combination with the JTAG automatic download test software. Using a scripted testing environment, a series of tedious manual testing operations are transformed into a fully automatic software process, which greatly improves the speed and accuracy of testing.
Description
Technical field
The invention belongs to electronic technology field, be specifically related to a kind of automatic test approach of programming device.
Background technology
Field programmable gate array (Field Programmable Gate Array, FPGA), it is at programmable logic array (Programmable Array Logic, PAL), generic array logic (Generic Array Logic, GAL), the product that further develops on the basis of the programming device such as CPLD (Complex Programmable Logic Device, CPLD).It is at first as special IC (Application Specific Integrated Circuit, ASIC) approach of prototype functional verification and occurring, both solve the deficiency of custom circuit, overcome again the limited shortcoming of original programming device gate circuit number.
Because the FPGA design cycle is short, Time To Market is fast, non-repetition engineering cost (Non-Recursive Engineering, NRE) low characteristics, have dynamically reconfigurable characteristic in addition, thereby in the fields such as commercial communication, consumer electronics product, automobile, medical treatment, obtain a wide range of applications.
Yet along with the explosive growth of fpga chip complicacy and density, the challenge that chip testing is faced is also increasing.Traditional method of testing is that chip is placed on the special exploitation motherboard, bit stream file is downloaded in the chip, then produce the input signal of appointment by signal generator, act on the port on the chip, be whether the signal of external each output pins of observation such as LED lamp of chip meets expection, the correctness of artificial judgment bit stream file by CRO coupling or mother matrix again.This method efficient is very low, can not do batch testing, can only observe roughly the signal intensity situation of limited output pin, and is easy to occur mistake.
The second method of testing is to use commercial on-line debugging software, such as the SignalTap of altera corp and the ChipScope of Xilinx company etc.This type of debugging software design software general and product company supports the use, can catch with the display chip system in the state [1] of live signal, but these debugging softwares are only supported the chip that own company produces, and whole flow process also must be carried out in corresponding supporting design software.This method versatility is not high, can not be used for testing self-designed fpga chip and autonomous design software flow process.
The third method is to use commercial test macro, such as the Agilent 93000 Pin Scale test machines [2] of Agilent Technologies.This method has high universalizable, high accuracy, but its corresponding software kit is comparatively complicated, and learning cost is higher, and the hardware support kit price is very expensive, does not meet the requirement of testing fast at lower cost.
In order to overcome the various shortcoming of above method, the present invention has realized a kind of based on JTAG(Joint Test Action Group) the automatic download test method of [3] boundary scan technique, satisfied fast and accurately mass test request.
List of references
[1]Altera, “Design Debugging Using the SignalTap II Embedded Logic Analyzer”, 2009；
[2]Verigy, V93000 Technical Documentation Center, “Verigy V93000 SmarTest 6.5.3 Help Documentation”, 2010；
[3]IEEE Standards, Piscataway, N.J., “ANSI/IEEE Std 1149.1-1990 Standard Test Access Port and Boundary-Scan Architecture”, 1993。
Summary of the invention
The object of the present invention is to provide a kind of energy to satisfy fast and accurately mass test request, and low programmable logic device (PLD) Auto-Test System and the method for learning cost.
Programmable logic device (PLD) automatic test approach provided by the invention is a kind of based on JTAG(Joint Test Action Group) the automatic download test method of [3] boundary scan technique.Specifically comprise generation, the download configuration fpga chip of chip configuration file, generation and the loading of test vector, and test result relatively waits, and made up corresponding test macro, all realize robotization, make things convenient for the user that design circuit is carried out simulation hardware, greatly improve efficient and the accuracy of test.Be specifically described as follows:
1. based on the jtag boundary scanning technique
The jtag test method provides very high test coverage, in any case simultaneously complicated circuit only needs simple 4 ports (if comprise asynchronous reset signal TRST then be 5 ports) can realize test, this interface is known as again TAP(Test Access Port), this scheme has alleviated chip does not greatly have enough physical addresss to be used for the problem of access.These TAP ports are respectively: test clock TCK(input), test mode selects the TMS(input), serial test data input TDI(input), serial test data output TDO(output).
The core of jtag test is the TAP controller, and its effect is that the tms signal of serial input is deciphered, and makes border scanning system enter corresponding mode of operation, and produces needed each control signal under this pattern.In the IEEE1149.1 standard, the decoding state of TMS list entries and TAP controller has been provided constitutional diagram as shown in Figure 1, the value of 0 or 1 numeral TMS on the arrow limit.
After system powers on, the TAP controller enters (Test-Logic-Reset) state that resets, the mode of operation of JTAG at first will be set, need the update instruction register for this reason, concrete state flow path switch is as follows: " free time " (Run-Test/Idle), " selection data register " (Select-DR-Scan), " selection instruction register " (Select-IR-Scan), " catch instruction " (Capture-IR), " instruction shift " (Shift-IR), (Exit1-IR), " instruction comes into force " (Update-IR) gets back to " free time " state at last " to finish 1 "." catching instruction " state in said process, old director data is loaded in the middle of the order register; Then enter into " instruction shift " state, under this state, by the driving of TCK, a new specific instruction can be pushed in the middle of the order register; Again to " instruction comes into force " state, just now be input to instruction in the order register with decoded and make instruction formally effective, specify TDI, TDO port be connected with specific data register (as shown in Figure 2); At last, enter into " free time " state, wait for the next round control flow.
The test data register group that is shown in Figure 2, mainly comprise boundary scan register (Boundary Scan Register), bypass register (Bypass Register), device identification register (Identification Register), configuration register (Config Register) and order register (Instruction Register).Boundary scan register is most important work register in the boundary scan testing, and it finishes the input of test vector, the essential operation of the tests such as output latch and displacement (Fig. 2 make a circle outward register be boundary scan register); Bypass register is exactly a bit register in fact, and it gets up the boundary scan chain short circuit of this chip, is mainly used in multi-chip series connection test, and whether the basic function that also can be used for testing JTAG is normal; The device identification register is one 32 standard register, and its content comprises the information such as the version number, device model, manufacturer of this chip, and whether can be used for test chip working properly; Configuration register is mainly used in configuration download and the retaking of a year or grade of chip, and it is as the impact damper of 32 bus datas, the parallel-serial conversion the when string when being used for realizing disposing and conversion and retaking of a year or grade; Order register namely is used for selecting the register of mode of operation, selects one of above-mentioned test data register group to be connected between TDI and the TDO according to specific order code.
Access by the selected data register of specific instruction, still need to take " free time " as starting point, enter successively " selection data register ", " capture-data " (Capture-DR), " data displacement " (Shift-DR), (Exit1-DR), " data come into force " (Update-DR) gets back to " free time " state at last " to finish 1 ".Having selected the boundary scan register link as example, " capture-data " state in said process, current chip pin output state data are caught in the data register; Then enter into " data displacement " state, under this state, by the driving of TCK, can be with a new test vector data-pushing in the middle of data register, old pin output state data are exported from the TDO port simultaneously; To " data come into force " state, the test vector that just now was input in the data register will formally be loaded on the chip pin by latch again; At last, get back to " free time " state, finish a loading of taking turns test vector.
2. based on the programmable logic device (PLD) Auto-Test System of JTAG
In order to realize above-mentioned automatic test approach, the present invention has at first proposed a cover and has been used for the automatically system of test.System forms as shown in Figure 3, is divided into the hardware and software two large divisions: hardware components comprises the computing machine for the operation automatic testing software, and programmable chip test board to be measured; Software section comprises composing software, test vector generator, serial ports control software and the regression test system that they are combined.Wherein:
Described composing software matches with chip to be measured, and it is used for user's projects file is compiled into the chip configuration file, and this document is downloaded to fpga chip just can become chip configuration the needed function of user.
Described test vector generator, use the perl script language compilation, it carries out emulation by call traditional simulation software (ModelSim instrument) under command line environment to user's design to be measured, and the waveform recording file conversion that generates after the emulation is become needed test vector form.In this way, can generate like clockwork the test vector of various projects, the coverage rate of test vector also can effectively be guaranteed.
Described serial ports control software uses C Plus Plus to write, and the general chained library control serial ports that it uses Windows XP operating system to provide makes it transmit and receive data by certain format.Because the TAP port of JTAG has 4, is respectively TCK, TMS, TDI, TDO, and the data of serial ports output have 8, and we stipulate that corresponding relation is as follows:
| The serial ports port | B7 | B6 | B5 | B4 | B3 | B2 | B1 | B0 |
| The TAP port | TDO | TMS | TCK | TDI |
Described regression test system, the irrelevant TCL script of usage platform is realized, can seamlessly call above-mentioned all test subsystems.By setting up regression testing policy, make things convenient for the user to carry out the system testing of many versions, do not introduce new mistake or cause other codes to produce mistake with the modification of confirming each version.Automatic regression test will significantly reduce the cost in the stages such as system testing, maintenance upgrade.
3. based on the programmable logic device (PLD) automatic test approach of JTAG
In order to finish the purpose of full-automatic test, concrete steps of the present invention following (as shown in Figure 4):
(1). use TCL script environment Automatically invoked to be used for generating the perl script of a series of documents.This script can call composing software user's project source program is compiled into bit stream file for the download configuration fpga chip; Call simultaneously the test vector file that test vector generator generates prescribed form.
(2). the serial ports of PC is connected to the jtag test port (TAP) of FPGA, and the jtag port of operation serial ports control software control chip changes the state of its TAP controller, makes it to move respectively following test pattern:
A) test bypass.Whether send the Bypass instruction, this instruction is connected to bypass register between TDI and the TDO port, be used for test JTAG and work.
Detailed process is: control first the JTAG state machine and enter " instruction shift " state, send Bypass order code (being " 1111 " in the test chip), the state of a control machine enters " data displacement " state again, one group of data that input is fixing, read again the output of TDO, and whether consistent with Output rusults with software approach inspection input.If two groups of data consistents then show JTAG normal operation.
B) test identification code.Whether send the IDCode instruction, this instruction is connected to the device identification register between TDI and the TDO port, be used for test chip and work.
Detailed process is: control first the JTAG state machine and enter " instruction shift " state, send IDCode order code (being " 1001 " in the test chip), the state of a control machine enters " data displacement " state again, input random one group 32 data, read 32 outputs of TDO, the data of output should be consistent with predefined device identification code in the chip under normal circumstances again.If two groups of data consistents then show chip normal operation.
C) configuring chip.Send the ConfigIn instruction, this instruction is connected to configuration register between TDI and the TDO port, is used for downloading the chip configuration file.
Detailed process is: control first the JTAG state machine and enter " instruction shift " state, send ConfigIn order code (being " 0101 " in the test chip), the state of a control machine enters " data displacement " state again, then read in the chip configuration file that step (1) generates, be downloaded to fpga chip by the TDI port, so far the function of chip has disposed and has finished.
D) test vector loads and compares.Send the Extest instruction, this instruction is connected to boundary scan register between TDI and the TDO port, is used for carrying out testing authentication according to test vector.
Detailed process is: control first the JTAG state machine and enter " instruction shift " state, send Extest order code (being " 0000 " in the test chip), the state of a control machine enters " data displacement " state again, then read in step (1) and generate test vector file, load successively by TDI and respectively to organize test vector, and from the Output rusults that TDO reads chip, compare with expected results.All consistent such as comparative result, then test is passed through, otherwise is defective.
(3). the statistical test result generates waveform and relatively reports.
Use TCL script environment automatically to read in the next project in the tabulation to be measured and repeat above process.
Description of drawings
The boundary scan state machine that Fig. 1 ieee standard 1149.1-1990 formulates.
Fig. 2 boundary scan register group.
Fig. 3 Auto-Test System forms.
Fig. 4 automatic test approach process flow diagram.
Embodiment
For the testing requirement of analog subscriber, we have chosen various example to be measured and have amounted to 105, and wherein pure combinational circuit example amounts to 51, and the sequential circuit example amounts to 56; On function, comprise simple totalizer, multiplier, comparer, encryption and decryption logic, also comprise the application such as complicated singing, VGA port are controlled, communication.In addition, a fpga chip that test board is selected is supported the jtag boundary scanning technique, and supporting with it composing software is arranged, and satisfies test request.
Only need to input an order under command line environment during test, just can carry out comprehensively, compile, download, test and add up all 105 examples, whole process need not manually-operated, greatly makes things convenient for the user to carry out repeated test.Empirical tests, most examples all can pass through by disposable test, and the example of test crash can relatively be reported the problem of finding existence by checking waveform, the relevant issues of manual amendment's source file finally also can be tested and be passed through.
Take simple totalizer project adder4 as example, its source program comprises adder4.v and adder4_test.v, and the former is the behavioral scaling net meter file, and the latter is simulation document.During operation regression test system, at first can call perl script and automatically generate bit stream file adder4.bit and the test vector file adder4.txt that is used for configuring chip.Then can call serial ports control software and carry out jtag test, after carrying out successively the test of bypass test and identification code, bit stream file is downloaded to FPGA, read in test vector file and load test vector by boundary scan chain, read behind the result of test with the expected results that simulates relatively, obtain at last relatively report file adder4.rpt of waveform.
In whole testing process, the user only needs simply to input an order just can finish whole testing process automatically.And if use old-fashioned pure manual test, not only efficient is extremely low, and various mistakes very easily occur; Again with respect to the SignalTap of altera corp and the ChipScope of Xilinx company, although these instrument tests accurately, but in test process, still need certain manual operations, for large batch of test assignment, the user still needs to expend the plenty of time and energy operates, and it is only applicable to the separately chip of company's production; Last Agilent 93000 Pin Scale test machines for Agilent Technologies, although its test accuracy, versatility and speed are all high, but also need the user to be ready in advance bit stream file and test vector, the supporting software application threshold of this machine is high in addition, needs the cost plenty of time learn its using method.
When using Auto-Test System that the present invention proposes and method, reality finds, this cover instrument not only is very easy to the user to the simulation hardware test of engineering code, also can be used in fpga chip itself is carried out hardware testing such as the test of interconnection traversal, quite have practicality.
Claims (6)
1. based on the FPGA chip Auto-Test System of boundary scan, it is characterized in that comprising the hardware and software two large divisions: hardware components comprises the computing machine for the operation automatic testing software, and FPGA chip testing plate to be measured; Software section comprises composing software, test vector generator, serial ports control software and the regression test system that they are combined; Wherein:
Described composing software matches with fpga chip to be measured, and it is used for user's projects file is compiled into the chip configuration file, and this document is downloaded to fpga chip, and fpga chip is configured to the needed function of user;
Described test vector generator by call simulation software under command line environment, carries out emulation to user's design to be measured, and the waveform recording file conversion that generates after the emulation is become needed test vector form;
Described serial ports control software, the general chained library control serial ports that uses Windows XP operating system to provide makes it transmit and receive data by certain format; Corresponding to 4 TAP port: TCK, TMS, TDI, the TDO of JTAG, the data of serial ports output have 8, and its corresponding relation is as follows:
Described regression test system, the irrelevant TCL script of usage platform realizes that it seamlessly calls above-mentioned all test subsystems; By setting up regression testing policy, realize that the user carries out the system testing of many versions, do not introduce new mistake or cause other codes to produce mistake with the modification of confirming each version.
2. FPGA chip automatic test approach based on boundary scan is characterized in that concrete steps are as follows:
(1) use TCL script environment Automatically invoked to be used for generating the perl script of a series of documents, this script calls composing software user's project source program is compiled into bit stream file for the download configuration fpga chip; Call simultaneously the test vector file that test vector generator generates prescribed form;
(2) serial ports of PC is connected to the jtag test port of FPGA, the jtag test port of operation serial ports control software control fpga chip changes the state of its TAP controller, makes it to move respectively following test pattern:
A), the test bypass sends the Bypass instruction, whether this instruction is connected to bypass register between TDI and the TDO port, be used for test JTAG and work;
B), the test identification code sends the IDCode instruction, whether this instruction is connected to the device identification register between TDI and the TDO port, be used for the test fpga chip and work;
C), configuring chip sends the ConfigIn instruction, this instruction is connected to configuration register between TDI and the TDO port, is used for downloading the fpga chip configuration file;
D), test vector loads and relatively send the Extest instruction, this instruction is connected to boundary scan register between TDI and the TDO port, is used for carrying out testing authentication according to test vector;
(3) statistical test result generates waveform and relatively reports;
(4) use TCL script environment reads in the next project in the tabulation to be measured automatically, and repeats above process.
3. method according to claim 2, the concrete steps that it is characterized in that described test bypass are: control first the JTAG state machine and enter " instruction shift " state, send the Bypass order code, the state of a control machine enters " data displacement " state again, one group of data that input is fixing, read again the output of TDO, and whether consistent with Output rusults with software approach inspection input; If two groups of data consistents then show JTAG normal operation.
4. method according to claim 2, the concrete steps that it is characterized in that described test identification code are: control first the JTAG state machine and enter " instruction shift " state, send the IDCode order code, the state of a control machine enters " data displacement " state again, input random one group 32 data, read again 32 outputs of TDO, if the default identification code of these group data and chip internal is consistent then show the chip normal operation.
5. method according to claim 2, the concrete steps that it is characterized in that described configuring chip are: control first the JTAG state machine and enter " instruction shift " state, send the ConfigIn order code, the state of a control machine enters " data displacement " state again, then read in the chip configuration file that step (1) generates, be downloaded to fpga chip by the TDI port.
6. method according to claim 2, it is characterized in that described test vector loads and concrete steps relatively are: control first the JTAG state machine and enter " instruction shift " state, send the Extest order code, the state of a control machine enters " data displacement " state again, then read in step (1) and generate test vector file, load successively by TDI and respectively to organize test vector, and read the Output rusults of chip from TDO, compare with expected results, all consistent such as comparative result, then test is passed through, otherwise is defective.
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| CN116500422A (en) * | 2023-05-08 | 2023-07-28 | 海光集成电路设计(北京)有限公司 | A chip parallel test system and test method based on a system-level test platform |
| CN116718900B (en) * | 2023-08-03 | 2023-11-10 | 上海灵动微电子股份有限公司 | Digital IP test system and method |
| CN117829052B (en) * | 2024-01-15 | 2024-06-25 | 上海宏泰芯半导体科技有限公司 | ModelSim and test system joint simulation debugging method |
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