CN101984485B - Display with bidirectional transfer shift register - Google Patents

Abstract

The invention relates to a display with a bidirectional transfer shift register, which comprises a display panel, a first transmission line, a second transmission line and a third transmission line, wherein the display panel is provided with N grid lines; a first group of dummy shift registers; a second set of dummy shift registers; a plurality of effective shift registers coupled between the two sets of dummy shift registers; and a first direction start trigger signal generator coupled to the first effective shift register for inputting a first direction start trigger signal to the first effective shift register to enable a first gate line. The first active shift register is coupled to the first group of dummy shift registers, and the Nth active shift register is coupled to the second group of dummy shift registers.

Description

Display with bidirectional transfer shift register

technical field

The present invention relates to a display with a bidirectional transfer shift register, in particular to a display that directly inputs a start trigger signal into a dummy shift register other than the first stage.

Background technique

FIG. 1 is a schematic diagram of a prior art liquid crystal display 100 . The liquid crystal display 100 includes a display area 102 , a plurality of gate lines 104 , a multi-stage effective shift register 106 and a multi-stage dummy shift register 108 . Wherein, the effective shift register 106 refers to a shift register whose output is directly connected to the display area 102 . In this illustration, due to the design of traditional displays, it is necessary to add a multi-stage dummy shift register 108 at the end of the transmission, so that there will be multi-stage dummy shift before and after the effective output stage of the shift register with bidirectional transmission function. register. However, when the downlink start trigger signal 110 or upload start trigger signal 112 is triggered, the effective scan line of the first stage will have a delay due to the dummy shift register, so that the output of the data line needs an additional memory to register, so Increase production difficulty and cost.

Please refer to FIG. 2A , FIG. 2B and FIG. 2C . 2A is a circuit block diagram of an effective shift register and a dummy shift register in FIG. 1, FIG. 2B is a timing diagram of driving all gate lines 104 according to a top-down driving sequence, and FIG. 2C is a timing diagram according to a bottom-up driving sequence. The timing diagram for driving all the gate lines 104 according to the driving sequence. When the downlink start trigger signal generator 200 inputs the downlink start trigger signal (ST_D) 202 to the first-stage dummy shift register 210 through the output signal to trigger the dummy shift register 210, the dummy register 210 will cooperate with the first clock The pulse signal ( CK1 ) transmits the downlink trigger signal 204 , and the downlink trigger signal ( Dummy_U1 ) 204 is sent to the second-stage dummy shift register 212 through an output signal in conjunction with the first clock pulse signal ( CK1 ). After the download trigger signal 204 is sent to the second-stage dummy shift register 212 to trigger the second-stage dummy shift register 212, the second-stage dummy shift register 212 will cooperate with the second clock pulse signal (CK2) to download and download The trigger signal 206 sends the downlink trigger signal (Dummy_U2) 206 to the first-stage effective shift register 214 through the output signal in conjunction with the second clock pulse signal (CK2). When the output signal sends the downlink trigger signal 206 to the first-stage effective shift register 214 to trigger the first-stage effective shift register 214, the first-stage effective shift register 214 will cooperate with the first clock pulse signal (CK1), The downlink trigger signal (ST_1) 208 is sent to the second-stage effective shift register 216 through the output signal in conjunction with the first clock pulse signal (CK1). By analogy, until the last stage of the dummy register outputs the downlink trigger signal. Conversely, when an upload start trigger signal generator 201 inputs the upload start trigger signal (ST_U) 222 to the last dummy shift register 230 through the output signal to trigger the last dummy shift register 230, the last dummy shift register 230 will be triggered. The shift register 230 cooperates with the second clock signal ( CK2 ) to send the upload trigger signal ( Dummy_D2 ) 224 to the dummy shift register 232 of the penultimate stage through the output signal in conjunction with the second clock signal ( CK2 ). When the output signal sends the upload trigger signal 224 to the penultimate second-stage shift register 232 to trigger the penultimate second-stage shift register 232, the penultimate second-stage dummy shift register 232 will cooperate with the first clock pulse signal (CK1), The upload trigger signal (Dummy_D1) 226 is sent to the last effective shift register 234 through the output signal in conjunction with the first clock pulse signal (CK1). When the output signal sends the upload trigger signal 226 to the last stage of effective shift register 234 to trigger the last stage of effective shift register 234, the last stage of effective shift register 234 will cooperate with the second clock pulse signal (CK2) to The upload trigger signal (ST_1080) 228 is sent to the penultimate second-stage effective shift register 236 through the output signal line in conjunction with the second clock pulse signal (CK2). By analogy, until the first stage dummy register outputs an upload trigger signal.

Please refer to FIG. 2A and FIG. 2B again. The downlink start trigger signal 202 is input into the first-stage dummy shift register 210 in the form of a pulse, and then the first-stage dummy shift register 210 sends the pulse (download trigger signal 204) Output to the second-stage dummy shift register 212, and the second-stage dummy shift register 212 outputs the pulse (download trigger signal 206) to the first-stage effective shift register 214, and the first-stage effective shift register 214 Then output the pulse (download trigger signal 208 ) to the second-stage effective shift register. On the other hand, when the downlink trigger signal 208 and the first clock signal (CK1) act simultaneously, the first valid data (D1) will be read. Subsequently, the output signal line of each stage of effective registers will sequentially send a pulse as the initial input signal of the next stage of effective registers (ST_2, ST_3, ST_4...), and the effective data (D2, D3, D4.. .) will be read successively according to the above-mentioned transmission method, until the output signal line of the dummy shift register 230 of the last stage sends out the last stage pulse (Dummy_D2). The transfer shift of the above-mentioned start pulse is a down transfer shift, and each stage of shift register maintains the same direction to complete data transfer. Please refer to FIG. 2A and FIG. 2C again. The upload start trigger signal 222 is input into the last-stage dummy shift register 230 in the form of a pulse, and then the last-stage dummy shift register 230 outputs the pulse (upload trigger signal 224) to The penultimate second-stage dummy shift register 232, and the penultimate second-stage dummy shift register 232 outputs the pulse (upload trigger signal 226) to the last-stage effective shift register 234, and the last-stage effective shift register 234 again This pulse (upload trigger signal 228 ) is output to the penultimate stage effective shift register 236 . On the other hand, when the upload trigger signal 228 and the second clock signal (CK2) act simultaneously, the first valid data (D1) will be read. Subsequently, the output signal line of each stage of effective registers will sequentially send a pulse as the initial input signal of the upper stage of effective registers (ST_1079, ST_1078, ST_1077...), and the effective data (D2, D3, D4.. .) will be read successively according to the above-mentioned transmission method, until the output signal line of the dummy shift register 210 of the first stage sends out the last stage pulse (Dummy_U1). The transmission shift of the above-mentioned start pulse is an upload shift, and each stage of shift register maintains the same direction to complete data transmission.

Since the prior art inputs the start trigger signal into the dummy shift register at the end, if it has bidirectional transmission function, the data signal must be delayed for a certain period of time, thus increasing the time for transmitting the trigger signal. Therefore, the present invention designs a bidirectional transfer shift register, which does not need to input the start trigger signal into the last dummy shift register, so as to avoid the time delay caused by the number of dummy shift registers.

Contents of the invention

The present invention provides a display, comprising: a display panel with N gate lines; a first group of dummy shift registers including at least one dummy shift register; a second group of dummy shift registers including at least one dummy shift register Shift register; a plurality of effective shift registers, coupled between the two sets of dummy shift registers, a first effective shift register coupled to the first set of dummy shift registers, an Nth effective shift register The bit register is coupled to the second group of dummy shift registers; and a first direction start trigger signal generator is coupled to the first effective shift register for inputting to the first effective shift register A first direction initiation trigger signal enables a first gate line.

The present invention further provides a display, comprising: a display panel having N gate lines; a first group of dummy shift registers having m dummy shift registers, wherein the i-th dummy shift register is coupled to A (i+1)th dummy shift register, and m-1≥i≥1; a second group of dummy shift registers; a plurality of effective shift registers, coupled between the two groups of dummy shift registers , a first effective shift register is coupled to an m-th dummy shift register of the first set of dummy shift registers, and an N-th effective shift register is coupled to the second set of dummy shift registers; and a first direction start trigger signal generator, coupled to a jth dummy shift register of the first set of dummy shift registers, for inputting a first direction start to the jth dummy shift register start trigger signal; where j≠1.

The present invention can directly input the initial trigger signal into the non-first-stage dummy shift register, so as to avoid the traditional delay of transmitting the trigger signal caused by inputting the initial trigger signal into the first-stage dummy shift register, which consumes additional transmission The time to trigger the signal. The invention not only can output data in time, but also saves the problem of extra temporary storage in extra memory. Also through the difference of the input position, it can be flexibly applied to the design of any shift register.

Description of drawings

Fig. 1 is the schematic diagram of the liquid crystal display of prior art;

Fig. 2A is the circuit block diagram of effective shift register and dummy shift register in Fig. 1;

FIG. 2B is a timing diagram of driving all gate lines according to a top-down driving sequence;

FIG. 2C is a timing diagram of driving all gate lines according to a bottom-up driving sequence;

3A is a schematic diagram of a display of the present invention;

3B is a timing diagram of driving all gate lines according to a top-down driving sequence of the present invention;

3C is a timing diagram of driving all gate lines according to a bottom-up driving sequence of the present invention;

Fig. 4A is the circuit block diagram of the shift register of the first embodiment of the present invention;

FIG. 4B is a partial timing diagram of transfer shift from top to bottom according to the first embodiment of the present invention;

FIG. 4C is a partial timing diagram of transfer shifting from bottom to top in the first embodiment of the present invention;

Fig. 5A is the circuit block diagram of the shift register of the second embodiment of the present invention;

Fig. 5B is a partial timing diagram of shift transfer from top to bottom in the second embodiment;

FIG. 5C is a partial timing diagram of shift transfer from bottom to top in the second embodiment;

Fig. 6A is the circuit block diagram of the shift register of the third embodiment of the present invention;

FIG. 6B is a partial timing diagram of shift transfer from top to bottom in the third embodiment;

FIG. 6C is a partial timing diagram of shift transfer from bottom to top in the third embodiment;

Fig. 7A is the circuit block diagram of the shift register of the 4th embodiment of the present invention;

Fig. 7B is a partial timing diagram of transferring shift from top to bottom in the fourth embodiment;

FIG. 7C is a partial timing diagram of transferring shift from bottom to top in the fourth embodiment;

Fig. 8A is the circuit block diagram of the shift register of the fifth embodiment of the present invention;

Fig. 8B is a partial timing diagram of shift transfer from top to bottom in the fifth embodiment;

FIG. 8C is a partial timing diagram of bottom-up shift transfer in the fifth embodiment.

Among them, reference signs

100, 300: display 102: display area

104, 304: gate line

110, 202, 402, 502, 602, 702, 802: download start trigger signal

112, 222, 422, 522, 622, 722, 822: upload start trigger signal

204, 206, 208, 404, 406, 408, 504, 506, 508, 604, 606, 608, 704, 706, 708, 804, 806, 808: download trigger signal

224, 226, 228, 424, 426, 428, 524, 526, 528, 624, 626, 628, 724, 726, 728, 824, 826, 828: upload trigger signal

108, 210, 212, 230, 232, 418, 420, 518, 520, 610, 618, 620, 710, 720, 730, 732, 818, 820, 830: dummy shift register

106, 302, 214, 216, 234, 236, 410, 412, 414, 416, 430, 432, 434, 436, 510, 512, 514, 516, 530, 532, 534, 536, 612, 614, 616, 630, 632, 634, 636, 712, 714, 716, 734, 736, 810, 812, 814, 816, 832, 834, 836: effective shift register

200, 400: Download start trigger signal generator

201, 401: upload start trigger signal generator

CK1: the first clock pulse signal

CK2: Second clock pulse signal

CK3: The third clock pulse signal

Dummy_D1, Dummy_D2, Dummy_U1, Dummy_U2, ST_D1～ST_D1080, ST_U1～ST_U1080, ST_D, ST_U, ST_D_d1, ST_U_d1, ST_U_d2: trigger signal

D1～D8: valid data

Detailed ways

3A is a schematic diagram of a display 300 of the present invention. The display 300 includes a display area, a plurality of gate lines 304, a multi-stage effective shift register 302, and two sets of dummy shift registers respectively coupled to the first and last effective shift registers. The shift register 302, two groups of dummy shift registers respectively include at least one dummy shift register. The downlink start trigger signal and upload start trigger signal of the display 300 are respectively directly input to the effective shift registers 302 of the first stage and the last stage, so that the design structure has the characteristics of bidirectional transmission function and the data signal does not need to be delayed. In addition, the timing relationship can be the same as that of general unidirectional transmission, as shown in Figures 3B and 3C, Figure 3B is a timing diagram of driving all gate lines 304 according to the driving sequence from top to bottom in the present invention, Figure 3C It is a timing diagram of driving all the gate lines 304 according to the driving sequence from bottom to top in the present invention.

Please refer to Figures 3A, 3B. When the resolution is preset to 1080 gate lines, the downlink start trigger signal (ST_D) is input to the first-stage effective shift register through the output signal line in the form of a pulse, and the first-stage effective shift register will The next trigger signal (ST_1) is output to the second-stage effective shift register in the form of a pulse through the output signal line, and the first valid data (D1) will be read out. Then, when the second-stage effective shift register receives the downlink trigger signal (ST_1), it will output the downlink trigger signal (ST_2) to the third-stage effective shift register in the form of a pulse through the output signal line, and read Take out the second valid data (D2). By analogy, until the dummy shift register of the last stage outputs a downlink trigger signal (Dummy_D2 ) through the output signal line, the transfer action of downlink shift is completed.

Please refer to FIG. 3A, FIG. 3C. When the resolution is preset to 1080 gate lines, an upload start trigger signal (ST_U) is input to the 1080th-level effective shift register in the form of a pulse through the output signal line, and the 1080-level effective shift register will convert a The upload trigger signal (ST_1080) is output to the 1079th effective shift register in the form of a pulse through the output signal line, and the first effective data (D1) will be read out. Then, when the 1079th stage effective shift register receives the upload trigger signal (ST_1080), it will output an upload trigger signal (ST_1079) to the 1078th stage effective shift register in the form of a pulse through the output signal line, and read Output the second valid data (D2). By analogy, until the dummy shift register of the first stage outputs the upload trigger signal (Dummy_U1 ) through the output signal line, the transfer operation of the upload shift is completed.

Please refer to FIG. 4A , FIG. 4B and FIG. 4C . FIG. 4A is a circuit block diagram of a shift register according to the first embodiment of the present invention. FIG. 4B is a partial timing diagram of shift transfer from top to bottom in the first embodiment, and FIG. 4C is a partial timing diagram of shift transfer from bottom to top in the first embodiment. In this embodiment, the two groups of dummy shift registers respectively include two dummy shift registers.

Please refer to FIG. 4A, after the downlink start trigger signal generator 400 inputs the downlink start trigger signal (ST_D) 402 into the first-stage effective shift register 410 through the output signal line to trigger the first-stage effective shift register 410, The first-stage effective shift register 410 cooperates with the first clock signal (CK1) to send the downlink trigger signal (ST_D1) 404 to the second-stage effective shift register 412 through the output signal line. After the downlink trigger signal (ST_D1) 404 is sent to the second-stage effective shift register 412 to trigger the second-stage effective shift register 412, the second-stage effective shift register 412 will cooperate with the second clock pulse signal (CK2) to The downlink trigger signal (ST_D2) 406 is sent to the third-stage effective shift register 414 through the output signal line. After the downlink trigger signal (ST_D2) 406 is sent to the third-stage effective shift register 414 to trigger the third-stage effective shift register 414, the third-stage effective shift register 414 will cooperate with the first clock pulse signal (CK1) to The downlink trigger signal (ST_D3) 408 is sent to the fourth-stage effective shift register 416 through the output signal line. By analogy, until the dummy shift register 418 of the last stage receives the downlink trigger signal. Conversely, when the upload start trigger signal generator 401 inputs an upload start trigger signal (ST_U) 422 to the last stage of effective shift register 430 through the output signal line to trigger the last stage of effective shift register 430, the effective shift The register 430 cooperates with the second clock pulse signal ( CK2 ) to send the upload trigger signal ( ST_U1 ) 424 to the penultimate second-stage effective shift register 432 through the output signal line. When the upload start trigger signal (ST_U1) 424 is sent to the penultimate second-stage effective shift register 432 to trigger the penultimate second-stage effective shift register 432, the penultimate second-stage effective shift register 432 will cooperate with the first clock pulse signal (CK1), sending the upload trigger signal (ST_U2) 426 to the penultimate third-stage effective shift register 434 through the output signal line. When the upload trigger signal (ST_U2) 426 is sent to the penultimate third-stage effective shift register 434 to trigger the penultimate third-stage effective shift register 434, the penultimate third-stage effective shift register 434 will cooperate with the second clock pulse signal (CK2 ), the upload trigger signal (ST_U3) 428 is sent to the penultimate fourth-stage effective shift register 436 through the output signal line. By analogy, until the first-stage dummy shift register 420 receives the upload trigger signal.

Please refer to FIG. 4A and FIG. 4B again. The downlink start trigger signal 402 is input into the first-stage effective shift register 410 in the form of a pulse, and then the first-stage effective shift register 410 sends the pulse (download trigger signal 404) output to the second-stage effective shift register 412. On the other hand, when the downlink trigger signal 404 and the first clock pulse signal (CK1) act simultaneously, the first valid data (D1) will be read. Then, the second-stage effective shift register 412 outputs the pulse (the downlink trigger signal 406 ) to the third-stage effective shift register 414 . Moreover, when the downlink trigger signal 406 and the second clock pulse signal (CK2) act simultaneously, the second valid data (D2) will be read. Subsequently, the third-stage effective shift register 414 outputs the pulse (download trigger signal 408 ) to the fourth-stage effective shift register 416 . On the other hand, when the downlink trigger signal 408 and the first clock signal (CK1) act simultaneously, the third valid data (D3) will be read. By analogy, the output signal line of each stage of shift register will sequentially send a pulse (ST_D4, ..., ST_D1080, Dummy_D1) to trigger the shift register of the next stage, and the data (D4, D5, D6 . . . ) will be read successively according to the above-mentioned transmission method, until the dummy shift register 418 of the last stage receives the last stage pulse Dummy_D1. The transfer shift of the above-mentioned start pulse is a down transfer shift, and each stage of shift register maintains the same direction to complete data transfer.

Please refer to FIG. 4A and FIG. 4C again, the upload start trigger signal 422 is input into the last-stage effective shift register 430 in the form of a pulse, and then the last-stage effective shift register 430 outputs the pulse (upload trigger signal 424) to the penultimate stage of effective shift register 432 . On the other hand, when the upload trigger signal 424 and the second clock signal (CK2) act simultaneously, the first valid data (D1) will be read. Then, the second-to-last effective shift register 432 outputs the pulse (upload trigger signal 426 ) to the third-to-last effective shift register 434 . Moreover, when the upload trigger signal 426 and the first clock pulse signal (CK1) act simultaneously, the second valid data (D2) will be read. Then, the third-to-last effective shift register 434 outputs the pulse (upload trigger signal 428 ) to the fourth-to-last effective shift register 436 . On the other hand, when the upload trigger signal 428 and the second clock signal (CK2) act simultaneously, the third valid data (D3) will be read. By analogy, the output signal line of each stage of shift register will sequentially send a pulse (ST_U4, ..., ST_U1080, Dummy_U1) to trigger the shift register of the previous stage, and the data (D4, D5, D6 . . . ) will be read successively according to the above-mentioned transmission method, until the dummy shift register 420 of the first stage receives the pulse Dummy_U1 of the last stage. The transmission shift of the above-mentioned start pulse is an upload shift, and each stage of shift register maintains the same direction to complete data transmission. In this embodiment, each dummy shift register can be a shift register for bidirectional transmission, or a shift register for unidirectional transmission, because the dummy shift register in FIG. 4A is only used for unidirectional transmission of trigger signals .

Please refer to FIG. 5A , FIG. 5B and FIG. 5C . FIG. 5A is a circuit block diagram of a shift register according to a second embodiment of the present invention. FIG. 5B is a partial timing diagram of shift transfer from top to bottom in the second embodiment, and FIG. 5C is a partial timing diagram of shift transfer from bottom to top in the second embodiment. In this embodiment, two groups of dummy shift registers respectively include three dummy shift registers.

Please refer to FIG. 5A, when the downlink start trigger signal generator 400 outputs a downlink start trigger signal (ST_D) 502 through the output signal line and inputs the first stage effective shift register 510 to trigger the effective shift register 510, the first stage The effective shift register 510 cooperates with the first clock pulse signal ( CK1 ) to send the downlink trigger signal ( ST_D1 ) 504 to the second stage effective shift register 512 through the output signal line. After the downstream trigger signal (ST_D1) 504 is sent to the second-stage effective shift register 512 to trigger the second-stage effective shift register 512, the second-stage effective shift register 512 will cooperate with the second clock pulse signal (CK2) to The downlink trigger signal (ST_D2) 506 is sent to the third-stage effective shift register 514 through the output signal line to trigger the third-stage effective shift register 514, and the third-stage effective shift register 514 will cooperate with the third-stage clock pulse signal ( CK3), sending the downlink trigger signal (ST_D3) 508 to the fourth-stage effective shift register 516 through the output signal line. By analogy, until the dummy shift register 518 of the last stage receives the downlink trigger signal. Conversely, when the upload start trigger signal generator 401 inputs an upload start trigger signal (ST_U) 522 to the last stage of effective shift register 530 through the output signal line to trigger the last stage of effective shift register 530, the effective shift The register 530 cooperates with the third clock pulse signal ( CK3 ) to send the upload trigger signal ( ST_U1 ) 524 to the penultimate stage effective shift register 532 through the output signal line. When the upload start trigger signal (ST_U1) 524 is sent to the penultimate second-stage effective shift register 532 to trigger the penultimate second-stage effective shift register 532, the penultimate second-stage effective shift register 532 will cooperate with the second clock pulse signal (CK2), sending the upload trigger signal (ST_U2) 526 to the penultimate third-stage effective shift register 534 through the output signal line. When the upload trigger signal (ST_U2) 526 is sent to the penultimate third-stage effective shift register 534 to trigger the penultimate third-stage effective shift register 534, the penultimate third-stage effective shift register 534 will cooperate with the first clock pulse signal (CK1 ), the upload trigger signal (ST_U3) 528 is sent to the penultimate fourth-stage effective shift register 536 through the output signal line. By analogy, until the first-stage dummy shift register 520 receives the upload trigger signal. Please refer to FIG. 5A and FIG. 5B again. The downlink start trigger signal 502 is input into the first-stage effective shift register 510 in the form of a pulse, and then the first-stage effective shift register 510 sends the pulse (download trigger signal 504) output to the second-stage effective shift register 512. On the other hand, when the downlink trigger signal 504 and the first clock pulse signal (CK1) act simultaneously, the first valid data (D1) will be read. Then, the second-stage effective shift register 512 outputs the pulse (the downlink trigger signal 506 ) to the third-stage effective shift register 514 . Moreover, when the downlink trigger signal 506 and the second clock pulse signal (CK2) act simultaneously, the second valid data (D2) will be read. Subsequently, the third-stage effective shift register 514 outputs the pulse (download trigger signal 508 ) to the fourth-stage effective shift register 516 . On the other hand, when the downlink trigger signal 508 and the third clock pulse signal (CK3) act simultaneously, the third valid data (D3) will be read. By analogy, the output signal line of each stage of shift register will sequentially send a pulse (ST_D4, ..., ST_D1080, Dummy_D1, Dummy_D2) to trigger the shift register of the next stage, and the data (D4, D5 , D6 . . . ) will be read out successively according to the above-mentioned transmission method, until the dummy shift register 518 of the last stage receives the pulse Dummy_D2 of the last stage. The transfer shift of the above-mentioned start pulse is a down transfer shift, and each stage of shift register maintains the same direction to complete data transfer.

Please refer to FIG. 5A and FIG. 5C again, the upload start trigger signal 522 is input into the last-stage effective shift register 530 in the form of a pulse, and then, the last-stage effective shift register 530 outputs the pulse (upload trigger signal 524) to the penultimate stage of effective shift register 532 . On the other hand, when the upload trigger signal 524 and the third clock signal (CK3) act simultaneously, the first valid data (D1) will be read. Then, the second-to-last effective shift register 532 outputs the pulse (upload trigger signal 526 ) to the third-to-last effective shift register 534 . Moreover, when the upload trigger signal 526 and the second clock pulse signal (CK2) act simultaneously, the second valid data (D2) will be read. Then, the third-to-last effective shift register 534 outputs the pulse (upload trigger signal 528 ) to the fourth-to-last effective shift register 536 . On the other hand, when the upload trigger signal 528 and the first clock signal (CK1) act simultaneously, the third valid data (D3) will be read. By analogy, the output signal line of each stage of shift register will sequentially send a pulse (ST_U4, ..., ST_U1080, Dummy_U1, Dummy_U2) to trigger the upper stage of shift register, and the data (D4, D5 , D6 . . . ) will be read out successively according to the above transmission method until the dummy shift register 520 of the first stage receives the last stage pulse Dummy_U2. The transmission shift of the above-mentioned start pulse is an upload shift, and each stage of shift register maintains the same direction to complete data transmission. In this embodiment, each dummy shift register can be a shift register for bidirectional transmission, or a shift register for unidirectional transmission, because the dummy shift register in FIG. 5A is only used for unidirectional transmission of trigger signals .

Please refer to FIG. 6A , FIG. 6B and FIG. 6C . FIG. 6A is a circuit block diagram of a shift register according to a third embodiment of the present invention. FIG. 6B is a partial timing diagram of shift transfer from top to bottom in the third embodiment, and FIG. 6C is a partial timing diagram of shift transfer from bottom to top in the third embodiment. In this embodiment, the two groups of dummy shift registers respectively include two dummy shift registers.

Please refer to FIG. 6A , when the downlink start trigger signal generator 400 outputs a downlink start trigger signal (ST_D) 602 through the output signal line and enters the second stage dummy shift register 610 to trigger the dummy shift register 610, the second stage The dummy shift register 610 cooperates with the second clock signal ( CK2 ) to send the downlink trigger signal ( ST_D_d1 ) 604 to the first stage effective shift register 612 through the output signal line. After the downlink trigger signal (ST_D_d1) 604 is sent to the first-stage effective shift register 612 to trigger the first-stage effective shift register 612, the first-stage effective shift register 612 will cooperate with the first clock pulse signal (CK1) to The downlink trigger signal (ST_D1) 606 is sent to the second-stage effective shift register 614 through the output signal line to trigger the second-stage effective shift register 614, and the second-stage effective shift register 614 will cooperate with the second clock pulse signal ( CK2), sending the downlink trigger signal (ST_D2) 608 to the third-stage effective shift register 616 through the output signal line. By analogy, until the dummy shift register 618 of the last stage receives the downlink trigger signal. Conversely, when the upload start trigger signal generator 401 inputs an upload start trigger signal (ST_U) 622 to the last stage of effective shift register 630 through the output signal line to trigger the last stage of effective shift register 630, the effective shift The register 630 cooperates with the second clock pulse signal ( CK2 ) to send the upload trigger signal ( ST_U1 ) 624 to the penultimate stage effective shift register 632 through the output signal line. When the upload start trigger signal (ST_U1) 624 is sent to the penultimate second-stage effective shift register 632 to trigger the penultimate second-stage effective shift register 632, the penultimate second-stage effective shift register 632 will cooperate with the first clock pulse signal (CK1), sending the upload trigger signal (ST_U2) 626 to the penultimate third-stage effective shift register 634 through the output signal line. When the upload trigger signal (ST_U2) 626 is sent to the penultimate third-stage effective shift register 634 to trigger the penultimate third-stage effective shift register 634, the penultimate third-stage effective shift register 634 will cooperate with the second clock pulse signal (CK2 ), the upload trigger signal (ST_U3) 628 is sent to the penultimate fourth-stage effective shift register 636 through the output signal line. By analogy, until the first-stage dummy shift register 620 receives the upload trigger signal.

Please refer to FIG. 6A and FIG. 6B again. The downlink start trigger signal 602 is input into the second-stage dummy shift register 610 in the form of a pulse, and then the second-stage dummy shift register 610 sends the pulse (download trigger signal 604) output to the first-stage effective shift register 612. Next, the first-stage effective shift register 612 outputs the pulse (download start trigger signal 606 ) to the second-stage effective shift register 614 . Moreover, when the downlink trigger signal 606 and the first clock pulse signal (CK1) act simultaneously, the first valid data (D1) will be read. Subsequently, the second-stage effective shift register 614 outputs the pulse (download trigger signal 608 ) to the third-stage effective shift register 616 . On the other hand, when the downlink trigger signal 608 and the second clock pulse signal (CK2) act simultaneously, the second valid data (D2) will be read. By analogy, the output signal line of each stage of shift register will sequentially send a pulse (ST_D4, ... ST_D1080, Dummy_D1) to trigger the next stage of shift register, and the data (D3, D4, D5, D6 . . . ) will be read successively according to the above-mentioned transmission method, until the dummy shift register 618 of the last stage receives the pulse Dummy_D1 of the last stage. The transfer shift of the above-mentioned start pulse is a down transfer shift, and each stage of shift register maintains the same direction to complete data transfer.

Please refer to FIG. 6A and FIG. 6C again, the upload start trigger signal 622 is input into the last-stage effective shift register 630 in the form of a pulse, and then, the last-stage effective shift register 630 outputs the pulse (upload trigger signal 624) to the penultimate stage of effective shift register 632 . On the other hand, when the upload trigger signal 624 and the second clock pulse signal (CK2) act simultaneously, the first valid data (D1) will be read. Then, the penultimate second-stage effective shift register 632 outputs the pulse (upload trigger signal 626 ) to the penultimate third-stage effective shift register 634 . Moreover, when the upload trigger signal 626 and the first clock pulse signal (CK1) act simultaneously, the second valid data (D2) will be read. Then, the third-to-last effective shift register 634 outputs the pulse (upload trigger signal 628 ) to the fourth-to-last effective shift register 636 . On the other hand, when the upload trigger signal 628 and the second clock pulse signal (CK2) act simultaneously, the third valid data (D3) will be read. By analogy, the output signal line of each stage of shift register will sequentially send a pulse (ST_U4, ..., ST_U1080, Dummy_U1) to trigger the shift register of the previous stage, and the data (D4, D5, D6 . . . ) will be read successively according to the above-mentioned transmission method until the dummy shift register 620 of the first stage receives the pulse Dummy_U1 of the last stage. The transmission shift of the above-mentioned start pulse is an upload shift, and each stage of shift register maintains the same direction to complete data transmission. In this embodiment, except that the dummy shift register 610 must be a bidirectional transmission shift register, other dummy shift registers can also be unidirectional transmission shift registers, because other dummy shift registers are only used for unidirectional transmission trigger signal.

Please refer to FIG. 7A , FIG. 7B and FIG. 7C . FIG. 7A is a circuit block diagram of a shift register according to a fourth embodiment of the present invention. FIG. 7B is a partial timing diagram of shift transfer from top to bottom in the fourth embodiment, and FIG. 7C is a partial timing diagram of shift transfer from bottom to top in the fourth embodiment. In this embodiment, the two groups of dummy shift registers respectively include two dummy shift registers.

Please refer to FIG. 7A, when the downlink start trigger signal generator 400 outputs a downlink start trigger signal (ST_D) 702 through the output signal line and enters the second stage dummy shift register 710 to trigger the dummy shift register 710, the second stage The dummy shift register 710 cooperates with the second clock signal ( CK2 ) to send the downlink trigger signal ( ST_D_d1 ) to the first stage effective shift register 712 through the output signal line. After the downlink trigger signal (ST_D_d1) 704 is sent to the first-stage effective shift register 712 to trigger the first-stage effective shift register 712, the first-stage effective shift register 712 will cooperate with the first clock pulse signal (CK1) to The downlink trigger signal (ST_D1) 706 is sent to the second-stage effective shift register 714 through the output signal line to trigger the second-stage effective shift register 714, and the second-stage effective shift register 714 will cooperate with the second clock pulse signal ( CK2), sending the downlink trigger signal (ST_D2) 708 to the third-stage effective shift register 716 through the output signal line. And so on, until the dummy shift register 730 of the last stage receives the downlink trigger signal. Conversely, when the upload start trigger signal generator 401 inputs an upload start trigger signal (ST_U) 722 to the last dummy shift register 730 through the output signal line to trigger the last dummy shift register 730, the dummy shift The register 730 cooperates with the second clock signal ( CK2 ) to send the upload trigger signal ( ST_U_d1 ) 724 to the dummy shift register 732 of the penultimate stage through the output signal line. When the upload start trigger signal (ST_U_d1) 724 is sent to the penultimate second-stage dummy shift register 732 to trigger the penultimate second-stage dummy shift register 732, the penultimate second-stage dummy shift register 732 will cooperate with the first clock pulse signal (CK1), after the upload trigger signal line (ST_U_d2) 726 is sent to the last effective shift register 734 through the output signal line to trigger the last effective shift register 734, the last effective shift register 734 will cooperate with the first The second clock pulse signal (CK2) sends the upload trigger signal (ST_U1) 728 to the penultimate stage effective shift register 736 through the output signal line. By analogy, until the first-stage dummy shift register 720 receives the upload trigger signal.

Please refer to FIG. 7A and FIG. 7B again. The downlink start trigger signal 702 is input into the second-stage dummy shift register 710 in the form of a pulse, and then the second-stage dummy shift register 710 sends the pulse (download trigger signal 704) output to the first-stage effective shift register 712. Then, the first-stage effective shift register 712 outputs the pulse (download start trigger signal 706 ) to the second-stage effective shift register 714 . Moreover, when the downlink trigger signal 706 and the first clock pulse signal (CK1) act simultaneously, the first valid data (D1) will be read. Subsequently, the second-stage effective shift register 714 outputs the pulse (download trigger signal 708 ) to the third-stage effective shift register 716 . On the other hand, when the downlink trigger signal 708 and the second clock pulse signal (CK2) act simultaneously, the second valid data (D2) will be read. By analogy, the output signal line of each stage of shift register will sequentially send a pulse (ST_D3, ... ST_D1080, Dummy_D1) to trigger the next stage of shift register, and the data (D3, D4, D5, D6 . . . ) will be read successively according to the above-mentioned transmission method, until the dummy shift register 730 of the last stage receives the pulse Dummy_D1 of the last stage. The transfer shift of the above-mentioned start pulse is a down transfer shift, and each stage of shift register maintains the same direction to complete data transfer.

Please refer to FIG. 7A and FIG. 7C again. The upload start trigger signal 722 is input into the last stage dummy shift register 730 in the form of a pulse, and then the last stage dummy shift register 730 outputs the pulse (upload trigger signal 724) to the dummy shift register 732 of the penultimate stage. Then, the dummy shift register 732 of the penultimate stage outputs the pulse (upload trigger signal 726 ) to the effective shift register 734 of the last stage. Subsequently, the last-stage effective shift register 734 outputs the pulse (upload trigger signal 728) to the penultimate second-stage effective shift register 736. On the other hand, when the upload trigger signal 728 is synchronized with the second clock pulse signal (CK2) When activated, the first valid data (D1) will be read. By analogy, the output signal line of each stage of shift register will sequentially send a pulse (ST_U2, ..., ST_U1080, Dummy_U1) to trigger the shift register of the previous stage, and the data (D2, D3, D4 . . . ) will be read successively according to the above-mentioned transmission method until the dummy shift register 720 of the first stage receives the pulse Dummy_U1 of the last stage. The transmission shift of the above-mentioned start pulse is an upload shift, and each stage of shift register maintains the same direction to complete data transmission. In this embodiment, except that the dummy shift register 720 can be a one-way or two-way transmission shift register, other dummy shift registers must be bidirectional transmission shift registers, because other dummy shift registers may be used for Perform bidirectional transmission of trigger signals.

Please refer to FIG. 8A , FIG. 8B and FIG. 8C . FIG. 8A is a circuit block diagram of a shift register according to a fifth embodiment of the present invention. FIG. 8B is a partial timing diagram of shift transfer from top to bottom in the fifth embodiment, and FIG. 8C is a partial timing diagram of shift transfer from bottom to top in the fifth embodiment. In this embodiment, the two groups of dummy shift registers respectively include two dummy shift registers.

Please refer to FIG. 8A, after the downlink start trigger signal generator 400 inputs the downlink start trigger signal (ST_D) 802 into the first-stage effective shift register 810 through the output signal line to trigger the first-stage effective shift register 810, The first-stage effective shift register 810 cooperates with the first clock signal (CK1) to send the downlink trigger signal (ST_D1) 804 to the second-stage effective shift register 812 through the output signal line. After the downlink trigger signal (ST_D1) 804 is sent to the second-stage effective shift register 812 to trigger the second-stage effective shift register 812, the second-stage effective shift register 812 will cooperate with the second clock pulse signal (CK2) to The downlink trigger signal (ST_D2) 806 is sent to the third-stage effective shift register 814 through the output signal line. After the downlink trigger signal (ST_D2) 806 is sent to the third-stage effective shift register 814 to trigger the third-stage effective shift register 814, the third-stage effective shift register 814 will cooperate with the first clock pulse signal (CK1) to The downlink trigger signal (ST_D3) 808 is sent to the fourth stage effective shift register 816 through the output signal line. And so on, until the dummy shift register 818 of the last stage receives the downlink trigger signal. Conversely, when the upload start trigger signal generator 401 inputs an upload start trigger signal (ST_U) 822 to the penultimate second-stage dummy shift register 830 through the output signal line to trigger the penultimate second-stage dummy shift register 830, the countdown The second-stage dummy shift register 830 cooperates with the first clock signal (CK1) to send the upload trigger signal (ST_U_d1) 824 to the penultimate first-stage effective shift register 832 through the output signal line. When the upload trigger signal (ST_U_d1) 824 is sent to the penultimate first-stage effective shift register 832 to trigger the penultimate first-stage effective shift register 832, the penultimate first-stage effective shift register 832 will cooperate with the second clock pulse signal (CK2 ), the upload trigger signal (ST_U1) 826 is sent to the penultimate second-stage effective shift register 834 through the output signal line. When the upload trigger signal (ST_U1) 826 is sent to the penultimate second-stage effective shift register 834 to trigger the penultimate second-stage effective shift register 834, the penultimate second-stage effective shift register 834 will cooperate with the first clock pulse signal (CK1 ), the upload trigger signal (ST_U2) 828 is sent to the penultimate third-stage effective shift register 836 through the output signal line. By analogy, until the first-stage dummy shift register 820 receives the upload trigger signal.

Please refer to FIG. 8A and FIG. 8B again. The downlink start trigger signal (ST_D) 802 is input into the first-stage effective shift register 810 in the form of a pulse, and then the first-stage effective shift register 810 sends the pulse (download trigger Signal 804) is output to the second-stage effective shift register 812. On the other hand, when the downlink trigger signal (ST_D1) 804 and the first clock signal (CK1) act simultaneously, the first valid data (D1) will be read. Then, the second-stage effective shift register 812 outputs the pulse (download trigger signal 806 ) to the third-stage effective shift register 814 . Moreover, when the downlink trigger signal (ST_D2) 806 and the second clock pulse signal (CK2) act simultaneously, the second valid data (D2) will be read. Subsequently, the third-stage effective shift register 814 outputs the pulse (download trigger signal 808 ) to the fourth-stage effective shift register 816 . On the other hand, when the downlink trigger signal (ST_D3) 808 and the first clock pulse signal (CK1) act simultaneously, the third valid data (D3) will be read. By analogy, the output signal line of each stage of shift register will sequentially send a pulse (ST_D4, ..., ST_D1080, Dummy_D1) to trigger the shift register of the next stage, and the data (D4, D5, D6 . . . ) will be read successively according to the above transmission method, until the dummy shift register 818 of the last stage receives the last stage pulse Dummy_D1. The transfer shift of the above-mentioned start pulse is a down transfer shift, and each stage of shift register maintains the same direction to complete data transfer.

Please refer to FIG. 8A and FIG. 8C again, the upload start trigger signal (ST_U) 822 is input into the penultimate second-stage dummy shift register 830 in the form of a pulse, and then the penultimate second-stage dummy shift register 830 sends the pulse (upload The trigger signal 824) is output to the penultimate effective shift register 832. Then, the penultimate first-stage effective shift register 832 outputs the pulse (upload trigger signal 826 ) to the penultimate second-stage effective shift register 834 . On the other hand, when the upload trigger signal (ST_U1) 826 and the second clock signal (CK2) act simultaneously, the first valid data (D1) will be read. Then, the second-to-last effective shift register 834 outputs the pulse (upload trigger signal 828 ) to the third-to-last effective shift register 836 . Moreover, when the upload trigger signal (ST_U2) 828 and the first clock pulse signal (CK1) act simultaneously, the second valid data (D2) will be read. By analogy, the output signal line of each stage of shift register will sequentially send a pulse (ST_U3, ..., ST_U1080, Dummy_U1) to trigger the shift register of the previous stage, and the data (D3, D4, D5, D6 . . . ) will be read out successively according to the above-mentioned transmission method, until the dummy shift register 820 of the first stage receives the pulse Dummy_U1 of the last stage. The transmission shift of the above-mentioned start pulse is an upload shift, and each stage of shift register maintains the same direction to complete data transmission. In this embodiment, each dummy shift register can be a shift register for unidirectional transfer as well as a shift register for unidirectional transfer, because the dummy shift register in FIG. 8A is only used for triggering unidirectional transfer Signal.

In the present invention, at least one start trigger signal among the upload start trigger signal and the downlink start trigger signal can be directly input into a non-first-stage dummy shift register, so as to avoid the traditional dummy shift register caused by inputting the start trigger signal into the first stage. The shift register causes a delay in transmitting the trigger signal, consuming additional time for transmitting the trigger signal. The invention not only can output data in real time, but also saves the problem of extra temporary storage in extra memory. Also through the difference of the input position, it can be flexibly applied to the design of any shift register.

Certainly, the present invention also can have other multiple embodiments, without departing from the spirit and essence of the present invention, those skilled in the art can make various corresponding changes and deformations according to the present invention, but these corresponding Changes and deformations should belong to the scope of protection of the appended claims of the present invention.

Claims (16)

1. A display, characterized in that it comprises: A display panel with N gate lines; A first set of dummy shift registers, including at least one dummy shift register; a second set of dummy shift registers, including at least one dummy shift register; A plurality of effective shift registers are coupled between the two sets of dummy shift registers, a first effective shift register is coupled to the first set of dummy shift registers, and an Nth effective shift register is coupled to in the second set of dummy shift registers; and A first direction start trigger signal generator, coupled to the first effective shift register, for directly inputting a first direction start trigger signal to the first effective shift register, so as to enable a first gate lines to avoid delay in transmitting the first direction start trigger signal due to inputting the first direction start trigger signal into the first set of dummy shift registers. 2. The display according to claim 1, further comprising a second direction start trigger signal generator coupled to the Nth effective shift register for shifting the Nth effective shift register The register inputs a second direction start trigger signal to enable an Nth gate line. 3. The display according to claim 1, further comprising a second direction start trigger signal generator, coupled to a dummy shift register of the second set of dummy shift registers, for the The dummy shift register inputs a second direction start trigger signal. 4. The display according to claim 2 or 3, wherein the second direction start trigger signal generator is an upload start trigger signal generator. 5. The display according to claim 1, wherein the first direction start trigger signal generator is a downlink start trigger signal generator. 6. The display according to claim 1, wherein each set of dummy shift registers comprises at least one shift register with unidirectional transmission. 7. The display according to claim 1, wherein each set of dummy shift registers comprises at least one bidirectional transmission shift register. 8. The display according to claim 1, wherein the plurality of effective shift registers are a plurality of bidirectional transmission shift registers. 9. A display, characterized in that it comprises: A display panel with N gate lines; A first group of dummy shift registers has m dummy shift registers, wherein an i-th dummy shift register is coupled to an (i+1)-th dummy shift register, and m-1≥i≥1 ; a second set of dummy shift registers; A plurality of effective shift registers are coupled between the two sets of dummy shift registers, a first effective shift register is coupled to an m-th dummy shift register of the first set of dummy shift registers, a The Nth effective shift register is coupled to the second set of dummy shift registers; and A first direction start trigger signal generator, coupled to a j-th dummy shift register of the first set of dummy shift registers, for directly inputting a first-direction start trigger signal generator to the j-th dummy shift register start trigger signal; Where j≠1, to avoid delay in transmitting the first direction start trigger signal due to inputting the first direction start trigger signal into the first dummy shift register of the first group of dummy shift registers. 10. The display according to claim 9, further comprising a second direction start trigger signal generator coupled to the Nth effective shift register for shifting the Nth effective shift register The register inputs a second direction start trigger signal to enable an Nth gate line. 11. The display according to claim 9, further comprising a second direction start trigger signal generator coupled to a dummy shift register of the second group of dummy shift registers for The dummy shift register inputs a second direction start trigger signal. 12. The display according to claim 10 or 11, wherein the second direction start trigger signal generator is an upload start trigger signal generator. 13. The display according to claim 9, wherein the first direction start trigger signal generator is a downlink start trigger signal generator. 14. The display according to claim 9, wherein each set of dummy shift registers comprises at least one shift register with unidirectional transmission. 15. The display according to claim 9, wherein each set of dummy shift registers comprises at least one bidirectional transmission shift register. 16. The display according to claim 9, wherein the plurality of effective shift registers are a plurality of bidirectional transmission shift registers. the

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