CN101977051B - Frequency correction circuit and method for automatically correcting frequency - Google Patents

Abstract

The invention discloses a frequency correction circuit for automatically correcting frequency and a method thereof, wherein the method comprises the following steps: a serial interface engine for generating a serial digital data according to a differential signal pair received from a master of a universal serial bus in a high-speed and/or full-speed transmission mode; then a packet identifier recognition unit recognizes a packet identifier at the beginning of each frame and a first period between two consecutive packet identifiers according to the sequence of digital data; a count comparator is used for generating a correction signal according to the first period to correct an output frequency of an oscillator.

Description

Frequency correction circuit and method for automatically correcting frequency

technical field

The present invention relates to a frequency correction circuit and method for automatically correcting frequency, especially to a frequency correction circuit and method for automatically correcting frequency by using the packet identification code of the Universal Serial Bus in high-speed and/or full-speed transmission mode .

Background technique

Oscillators are important components in many electronic systems and can be used as frequency generators, timers or counters in communication systems, computer systems, control systems and microprocessors.

Generally speaking, due to cost pressure, system manufacturers widely use less accurate non-crystal oscillators (such as RC oscillators or delay time oscillators) to replace crystal oscillators with more accurate oscillation frequencies (such as quartz oscillators). device). However, the prior art for improving the oscillation frequency of the non-crystal oscillator can improve the accuracy of the oscillation frequency of the non-crystal oscillator, but still cannot meet the requirements of high-speed digital systems (such as USB2.0). Therefore, system manufacturers are still developing technologies that can greatly improve the accuracy of the oscillation frequency of non-crystal oscillators.

Contents of the invention

An embodiment of the present invention provides a frequency correction circuit for automatically correcting frequency. The frequency correction circuit includes a serial interface engine, a packet identification code identification unit, an oscillator and a counting comparator. The serial interface engine generates a sequence of digital data according to the differential signal pair received from the master terminal of a universal serial bus in a high-speed and/or full-speed transmission mode; the packet identification code identification unit generates a sequence of digital data according to the sequence number data, identifying a packet identification code at the beginning of each frame, and a first period between two consecutive packet identification codes; and the counting comparator is used to generate a correction signal to correct the An output frequency of the oscillator.

An embodiment of the invention provides a method for automatically correcting frequency. The method includes generating a sequence of digital data from differential signal pairs received from a master of a Universal Serial Bus in a high-speed and/or full-speed transmission mode; identifying the start of each frame based on the sequence of digital data and correcting an output frequency of an oscillator according to a first period between two consecutive packet identification codes.

A frequency correction circuit and method for automatically correcting the frequency provided by the present invention are automatically corrected according to the packet identification code of the start of frame (SOF) of a universal serial bus in a high-speed and/or full-speed transmission mode An oscillator output frequency. Therefore, without substantially changing the existing circuit design, the error range of the output frequency of the oscillator can still meet the requirements of USB 2.0 for frequency error.

Description of drawings

FIG. 1 is a schematic diagram illustrating a frequency correction circuit for automatically correcting frequency according to an embodiment of the present invention;

2A and FIG. 2B are schematic diagrams of frame intervals defined in full-speed and high-speed transmission modes in the communication protocol of Universal Serial Bus Version 2.0;

3A and 3B are schematic diagrams of how the packet identification code identification unit identifies the packet identification code in high-speed and/or full-speed transmission mode;

FIG. 4 is a flowchart of a method for automatically calibrating the oscillator frequency by using the packet identification code at the beginning of a frame of the USB in the high-speed and/or full-speed transmission mode according to another embodiment of the present invention.

Among them, reference signs:

100 frequency correction circuit

102 serial interface engine

104 packet identification code identification unit

106 oscillators

108 count comparators

110 master control terminal

1082 Reference Oscillator

1084 first counter

1086 frequency divider

1088 second counter

1090 Comparator

1092 Controller

C1 first frequency number

C2 second frequency number

E1 correction signal

f1 output frequency

T1 first cycle

T2 second cycle

40-56 steps

Detailed ways

Please refer to FIG. 1 . FIG. 1 is a schematic diagram illustrating a frequency calibration circuit 100 for automatically calibrating frequency according to an embodiment of the present invention. The frequency calibration circuit 100 includes a serial interface engine (serial interface engine) 102 , a packet identification (PID) identification unit 104 , an oscillator 106 and a counting comparator 108 . The serial interface engine 102 generates a sequence of digital data according to a differential signal pair received from a master control terminal (host) 110 of a universal serial bus in a high speed (high speed) and/or full speed (full speed) transmission mode The packet identification code identification unit 104 is coupled to the serial interface engine 102, and according to the serial digital data, identifies the packet identification code at the beginning of each frame (frame), and a first cycle T1 between two consecutive packet identification codes .

The counting comparator 108 is coupled to the packet identification code identification unit 104 and the oscillator 106, including a reference oscillator 1082, a first counter 1084, a frequency divider 1086, a second counter 1088, a comparator 1090 and a control device 1092. The reference oscillator 1082 is coupled to the first counter 1084 and the second counter 1088 to provide a reference oscillation frequency (100MHz-300MHz) for counting by the counter 1084 and the second counter 1088; the first counter 1084 is coupled to the packet identification The code identification unit 104 is used for counting a first frequency number C1 generated by the reference oscillation frequency of the reference oscillator 1082 during the first period T1; The output frequency f1 (12MHz) is divided by 3000 (high-speed transmission mode) or 24000 (full-speed transmission mode) to generate a second period T2; the second counter 1088 is coupled to the frequency divider 1086 to count in the second period T2 A second frequency number C2 generated by the reference oscillation frequency of the reference oscillator 1082 during the period; the comparator 1090 is coupled to the first counter 1084 and the second counter 1088, and is used to A difference between them generates a comparison result; the controller 1092 is coupled to the comparator 1090 for generating a correction signal E1 to correct the output frequency f1 of the oscillator 106 according to the comparison result. In addition, the oscillator 106 and the reference oscillator 1082 are delay time oscillators or RC oscillators.

Please refer to FIG. 2A and FIG. 2B . FIG. 2A and FIG. 2B are schematic diagrams of frame pitches defined in full-speed and high-speed transmission modes in the communication protocol of Universal Serial Bus Version 2.0 (USB 2.0). As shown in Figure 2A, the frame interval (frame interval) defined under the full-speed transmission mode is a time interval of one millisecond error of five hundred nanoseconds (1.000ms±500ns); as shown in Figure 2B, the frame interval defined under the high-speed transmission mode The time interval is 125 microseconds with an error of 62.5 nanoseconds (125us±62.5ns). The error range of the above frame pitch can meet the requirements of USB 2.0 for frequency error (±500ppm), so the frame pitch in high-speed and/or full-speed transmission mode can be used as the benchmark for frequency correction.

Please refer to FIG. 3A and FIG. 3B . FIG. 3A and FIG. 3B are schematic diagrams of how the PID identification unit 104 identifies the PID in the high-speed and/or full-speed transmission mode. As shown in FIG. 3A and FIG. 3B, the types of the packet identification codes of the full-speed and high-speed transmission modes are all 10100101, therefore, by the type of the packet identification code, the packet identification code identification unit 104 can generate from the serial interface engine 102 The packet identification code at the beginning of each frame is identified in the sequence of digital data.

Please refer to FIG. 1, FIG. 2A and FIG. 2B. After the packet identification code identifying unit 104 recognizes the packet identification code, it recognizes two consecutive packet identification codes according to the reset (reset) and locking phase (locking inphase) mode. The first period T1 between them (that is, the frame interval defined in the full-speed or high-speed transmission mode), and the first counter 1084 generates the first frequency number C1 according to the first period T1 and the reference oscillation frequency of the reference oscillator 1082 sent to the comparator 1090. In addition, as shown in FIG. 2A , in the high-speed transmission mode, the frequency divider 1086 will divide the output frequency f1 (12 MHz) of the oscillator 106 by 3000 to generate a second period T2, corresponding to two consecutive start-of-frames (SOF) The first period T1; similarly, as shown in FIG. 2B , in the full-speed transmission mode, the frequency divider 1086 divides the output frequency f1 (12 MHz) of the oscillator 106 by 24000 to generate the second period T2. Afterwards, the second counter 1088 generates a second frequency number C2 according to the second period T2 and the reference oscillation frequency of the reference oscillator 1082 and sends it to the comparator 1090 . The comparator 1090 generates a comparison result according to the difference between the first frequency value C1 and the second frequency value C2 when the difference is greater than a preset threshold value TH. The controller 1092 generates a correction signal E1 to correct the output frequency f1 of the oscillator 106 according to the comparison result.

Please refer to FIG. 4 . FIG. 4 is a flow chart illustrating a method for automatically calibrating the oscillator frequency by using the packet identification code at the beginning of a frame of the Universal Serial Bus in the high-speed and/or full-speed transmission mode according to another embodiment of the present invention. The method of FIG. 4 utilizes the frequency correction circuit 100 of FIG. 1 to illustrate, and the detailed steps are as follows:

Step 40: start;

Step 42: the serial interface engine 102 generates serial digital data according to the differential signal pair received from the master control terminal 110 of the universal serial bus in the high-speed and/or full-speed transmission mode;

Step 44: The packet identification code identification unit 104 identifies the packet identification code at the beginning of each frame according to the serial digital data;

Step 46: The packet identification code identification unit 104 identifies the first period T1 between two consecutive packet identification codes according to the method of resetting and locking the same phase;

Step 48: the first counter 1084 counts the first frequency C1 generated by the reference oscillator 1082 during the first period T1;

Step 50: Divide the output frequency f1 of the oscillator 106 by 3000 or 24000 to generate a second period T2;

Step 52: the second counter 1088 counts the second frequency C2 generated by the reference oscillator 1082 during the second period T2;

Step 54: The comparator 1090 compares the first frequency number C1 and the second frequency number C2, if the difference between the first frequency number C1 and the second frequency number C2 is greater than the preset threshold value TH, a comparison result is generated, and step 56; Otherwise, jump back to step 50;

Step 56 : The controller 1092 generates a correction signal E1 to correct the output frequency f1 of the oscillator 106 according to the comparison result; skip back to step 50 .

It can be seen from the method in FIG. 4 that the frequency divider 1086 , the counter 1088 , the comparator 1090 , the controller 1092 and the oscillator 106 form a cycle that can automatically correct the frequency. Therefore, when the output frequency of the oscillator 106 deviates and is greater than the preset threshold TH, the output frequency of the oscillator 106 can be corrected through the above cycle.

To sum up the above, the existing technology is to write the corrected parameters into the non-volatile memory during production, or to use laser adjustment to correct the frequency, but these methods still cannot meet the needs of high-speed digital systems. However, the frequency correction circuit and method for automatically correcting the frequency provided by the present invention use the packet identification code of the SOF of the Universal Serial Bus in the high-speed and/or full-speed transmission mode to automatically correct the output frequency of the oscillator. Therefore, without changing the existing circuit design, the error range of the output frequency of the oscillator can still meet the requirements of USB 2.0 for frequency error (±500ppm).

The above descriptions are only preferred embodiments of the present invention, and all equivalent changes and modifications made according to the protection scope of the patent of the present invention shall fall within the scope of the present invention.

Claims (13)

1. A method for automatically correcting frequency, characterized in that, comprising: Step A, generating a sequence of digital data according to a differential signal pair received from a master of a Universal Serial Bus in a high-speed and/or full-speed transmission mode; Step B, identifying a packet identification code at the beginning of each frame according to the sequence of digital data; and Step C, comparing a first cycle between two consecutive packet identification codes and a second cycle generated by dividing an output frequency of an oscillator to generate a comparison result, and generate a correction according to the comparison result signal to correct the output frequency of the oscillator. 2. The method as claimed in claim 1, wherein the first period is identified according to the manner of resetting and locking in-phase. 3. The method of claim 1, wherein step C further comprises: counting a first frequency number generated by a reference oscillator during the first period; dividing the output frequency of the oscillator by 3000 to generate the second period; counting a second frequency number generated by the reference oscillator during the second period; generating the comparison result based on a difference between the first frequency number and the second frequency number; and According to the comparison result, the correction signal is generated to correct the output frequency of the oscillator. 4. The method according to claim 3, wherein the comparison result is generated according to the difference between the first frequency number and the second frequency number, and when the difference is greater than a preset threshold value, Generate the comparison result. 5. The method according to claim 1, wherein the packet identification code is composed of eight bits of data 10100101. 6. A frequency correction circuit for automatically correcting frequency, characterized in that it comprises: A serial interface engine generates a sequence of digital data according to a differential signal pair received from a master of a universal serial bus in a high-speed and/or full-speed transmission mode; A packet identification code identification unit, according to the sequence of digital data, identifies a packet identification code at the beginning of each frame, and a first period between two consecutive packet identification codes; an oscillator; and A counting comparator comprising: a reference oscillator; a first counter for counting a first frequency number generated by the reference oscillator during the first period; a frequency divider for dividing the output frequency of the oscillator to generate a second period; a second counter for counting a second frequency number generated by the reference oscillator during the second period; a comparator for generating the comparison result based on a difference between the first frequency number and the second frequency number; and A controller is used for generating the correction signal to correct the output frequency of the oscillator according to the comparison result. 7 . The frequency calibration circuit according to claim 6 , wherein the identifying packet identification code unit identifies the first period according to the way of resetting and locking the same phase. 8. frequency correction circuit as claimed in claim 6, is characterized in that, The frequency divider is used for dividing the output frequency of the oscillator by 3000 or 24000 to generate the second period. 9. The frequency calibration circuit as claimed in claim 8, wherein the reference oscillator is a delay time oscillator. 10. The frequency calibration circuit as claimed in claim 8, wherein the reference oscillator is a RC oscillator. 11. The frequency calibration circuit as claimed in claim 6, wherein the oscillator is a delay time oscillator. 12. The frequency calibration circuit as claimed in claim 6, wherein the oscillator is a RC oscillator. 13. The frequency calibration circuit according to claim 6, wherein the packet identification code is composed of eight bits of data 10100101.

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