CN101977042A - PWM or PSM dual-mode modulation control circuit used for switch voltage-stabilized supply - Google Patents

Abstract

The invention relates to a PWM or PSM dual-mode modulation control circuit for switching and stabilizing a power supply, which belongs to the field of electronic technology. It includes a controllable current reference source Iref, a comparator and a switching control circuit Load_SM; where the controllable current reference source Iref generates two reference voltage signals vref0 and vref1 under the control of a pair of opposite-phase control signals D0 and D1; the comparator realizes Comparison output of main switch drain voltage SW and reference voltage; switching control circuit Load_SM realizes automatic switching of PWM or PSM modulation mode and updates control signals D0 and D1. The present invention can select PWM or PSM modulation mode according to the light and heavy conditions of the load, so as to ensure that the system has higher efficiency in the whole load range. The present invention does not need a current sampling circuit to sample the current on the power switch tube, but directly converts the current into a voltage and compares it with a reference voltage, thereby judging the load condition. Most of the invention is a logic circuit, its own power consumption is low, the chip area occupied is small, and the efficiency of the system can be significantly improved.

Description

A PWM or PSM dual-mode modulation control circuit for switching regulated power supply

technical field

The invention belongs to the field of electronic technology, and relates to a control circuit of a switching and stabilizing power supply, in particular to a control circuit with a PWM or PSM dual-mode modulation mode for a switching and stabilizing power supply.

Background technique

The modulation methods often used in switching regulated power supplies (that is, power converters) include pulse width modulation mode PWM (PulseWidth Modulation) and pulse spanning modulation mode PSM (Pulse Skip Modulation). The output of the converter is controlled by a negative feedback control loop. The voltage remains stable. The specific implementation of pulse width modulation mode PWM is: if the input voltage or load changes cause the output voltage to change, the sampling circuit samples the output voltage and compares it with the reference voltage, and then adjusts the duty of the converter switch according to the change ratio, making the output voltage stable. The specific implementation of the pulse spanning modulation mode PSM is: if the input voltage or load changes cause the output voltage to change, the sampling circuit samples the output voltage and compares it with the reference voltage, and then determines whether there is a pulse being crossed according to the change. over, making the output voltage stable. PSM is based on constant frequency and constant width CWCF (Constant Width Constant Frequency) modulated pulse. When the output voltage of the converter is greater than the reference voltage, a pulse will be crossed, otherwise it will always be on/off under the control of constant frequency and constant width pulse wave working state, thereby stabilizing the output voltage of the converter. PWM is based on constant-frequency variable-width modulation pulses. When the output voltage of the converter is greater than the reference voltage, the duty cycle of the converter switch decreases; when the output voltage of the converter is lower than the reference voltage, the duty cycle of the converter switch increases; This stabilizes the output voltage of the converter. PSM modulation mode has the advantages of faster response and higher efficiency under light load, while in PWM modulation mode, the system efficiency is higher under heavy load, but because each clock cycle must be turned on, resulting in The system is less efficient. In order to achieve higher efficiency in the entire load range, two operating modes, PSM and PWM, can be considered in the system. When the load is light, the control circuit allows it to work in the PSM operating mode with higher efficiency. When the load is heavy At the same time, the control circuit is used to make it work in the high-efficiency PWM working mode, so that the system has high efficiency in the entire load range.

Contents of the invention

The present invention provides a PWM or PSM dual-mode modulation control circuit for a switching regulated power supply. The control circuit can select the PWM or PSM modulation mode according to the load condition to ensure that the system has higher efficiency in the entire load range; The control circuit does not need a current sampling circuit to sample the current on the power switch tube, but directly converts the current into a voltage and compares it with the reference voltage, so as to judge the weight of the load; most of the control circuit is a logic circuit, and its power consumption is low , occupies a small chip area, can significantly improve the efficiency of the system.

Detailed technical scheme of the present invention is:

A PWM or PSM dual-mode modulation control circuit for switching regulated power supplies, as shown in Figures 1 to 3, includes a controllable current reference source Iref, a comparator comp and a switching control circuit Load_SM.

The controllable current reference source Iref is shown in FIG. 2 and consists of four NMOS transistors, three PMOS transistors and a bias current source _IB . Three PMOS transistors M01, M02 and M03 are connected in series, that is, the drain of M01 is connected to the source of M02, the drain of M02 is connected to the source of M03, and the source of M01 is connected to the input voltage Vin. The gates of NMOS tubes MB, M0 and M1 are interconnected, the sources of NMOS tubes MB, M0 and M1 are interconnected, the drain of NMOS tube MB is short-circuited with the grid and then connected to bias current source I _B ; the NMOS tube M0 The drain is connected to the source of the NMOS transistor M2, the drain of the NMOS transistor M1 is connected to the source of the NMOS transistor M3; the drains of the NMOS transistors M2 and M3 are interconnected and connected to the drain of the PMOS transistor M03.

The drain of the PMOS transistor M03 is connected to the positive input terminal of the comparator comp, and the drain voltage SW of the main switching tube in the external switching regulated power supply is connected to the negative input terminal of the comparator comp.

The switching control circuit Load_SM is shown in FIG. 3 and consists of two D flip-flops, two delays, two inverters, two sequence detectors, two AND gates, one OR gate and one selector. The output terminal of comparator comp is connected to the input terminal of delayer 1; the output terminal of delayer 1 is connected to the data input terminal of D flip-flop 1, and the output terminal of inverter 1 is connected to the clock terminal of D flip-flop 1; D flip-flop 1 The non-inverting output terminal of the D flip-flop is connected to the input terminal of the sequence detector 1, and the inverting output terminal of the D flip-flop 1 is connected to the input terminal of the sequence detector 2; the output terminal of the sequence detector 1 is connected to an input terminal of the AND gate 1, and the sequence detector The output terminal of 2 is connected to an input terminal of AND gate 2; the output signals of AND gate 1 and AND gate 2 are respectively used as two input signals of OR gate, and the output signal of OR gate is used as the clock signal of D flip-flop 2; D flip-flop The inverting output terminal of 2 is short-circuited with the data input terminal, and the non-inverting output terminal of D flip-flop 2 is respectively connected to the input terminal of delayer 2 and the control input terminal S of the selector; the control signal D0 output by delayer 2 is connected to the inverting terminal at the same time The input terminal of the inverter 2, the other input terminal of the AND gate 1 and the gate of the NMOS transistor M2 in the controllable current reference source Iref, the control signal D1 output by the inverter 2 is simultaneously connected to the other input terminal of the AND gate 2 and the gate of the controllable current reference source Iref. Control the gate of the NMOS transistor M3 in the current reference source Iref; the two selection input terminals of the selector input the PSM or PWM modulation signal respectively, when the control input terminal S is at high level, select the PWM modulation signal as the output signal; when the control input When the terminal S is at low level, the PSM modulation signal is selected as the output signal; the output signal of the selector is respectively used as the gate control signal of the main switch tube in the external switching regulated power supply and the three PMOS tubes M01 and M02 in the controllable current reference source Iref And the gate control signal of M03, at the same time, the output signal of the selector is used as the clock signal of D flip-flop 1 after being inverted by inverter 1.

Figure 1 shows the application of the present invention in a typical buck power converter. In a typical buck circuit mode, the source of the main switch MPP is connected to the input signal Vin, the gate is connected to the control signal vg, and the drain (SW) is connected to one end of the inductor L, the cathode of the diode D, and the negative end of the comparator comp respectively. . The other end of the inductor L is connected to the capacitor C and the load resistor R, the other end of the capacitor C and the load resistor R are grounded, the anode of the diode D is grounded, the positive end of the comparator comp is connected to the controllable current reference Iref, and the comparator output comp_out is connected to the switch The other three inputs of the control circuit Load_SM are vg, the PSM control signal and the PWM control signal respectively, and its output is the control signals D0, D1 and the gate control signal vg of the main switching transistor MPP.

The beneficial effects of the present invention are:

The PWM or PSM dual-mode modulation control circuit for switching regulated power supply provided by the present invention can select the control signal of PWM or PSM modulation mode according to the weight of the external load to control the main switching tube in the external switching regulated power supply , to ensure that the system has high efficiency over the entire load range. When the external load is light, the PSM modulation mode is used to control the main switch tube in the external switching regulated power supply, and when the external load is heavy, the PWM modulation mode is used to control the main switch tube in the external switching regulated power supply. When the load changes, the PWM or PSM modulation mode can be automatically switched. The circuit is equipped with a hysteresis function to ensure that the system is in a stable working state and will not oscillate back and forth in different modulation modes. In addition, the control circuit does not need a current sampling circuit to sample the current on the power switch tube, but directly converts the current into a voltage and compares it with the reference voltage to judge the load. Most of the control circuit is a logic circuit, and its own function Low power consumption, occupying a small chip area, can significantly improve the efficiency of the system.

Description of drawings

Fig. 1 is a functional block diagram of a PWM or PSM dual-mode modulation control circuit for a switching regulated power supply provided by the present invention.

Fig. 2 is a circuit diagram of a controllable current reference source and a comparator in the present invention.

FIG. 3 is a circuit diagram of the switching control circuit Load_SM in the present invention.

Detailed ways

The working principle of the PWM or PSM dual-mode modulation control circuit for the switching regulated power supply provided by the present invention will be described below in conjunction with the accompanying drawings, taking a power converter with a buck structure as an example of the switching regulated power supply.

The current on the main switch tube of the buck circuit in discontinuous mode can be simulated by a triangle wave. As shown in Figure 2, the three PMOS transistors M01, M02 and M03 in the deep linear region in series are equivalent to a resistor, and the same gate control signal vg as the main switch is used, and the current flowing through M01, M02 and M03 is assumed I _D ; use a pair of mutually inverse control signals D0 and D1 to control the conduction or cut-off of the NMOS transistors M2 and M3 in the controllable current reference source Iref: when D0 is high level and D1 is low level, M2 is turned on and M3 is turned off. At this time, the voltage of the controllable current reference source Iref input to the positive terminal of the comparator is vref0; when D0 is low and D1 is high, M2 is turned off and M3 is turned on. At this time, the controllable current reference The voltage of the source Iref input to the positive terminal of the comparator is vref1; by setting the width-to-length ratio of M0 and M2 and M1 and M3, vref0 is slightly smaller than vref1 to realize hysteresis. The comparator compares the drain terminal voltage SW of the main switch with the reference voltage vref0 generated by the control signal D0 or the reference voltage vref1 generated by the control signal D1. When SW>vref0, the comparator outputs a low level; when SW<vref1, Comparator output high level.

The clock of D flip-flop 1 is the inverse of the gate control signal vg of the main switch, and has the same start time and period as the comparator output signal comp_out, but after the comparator output signal comp_out is delayed by delayer 1, delayer 1 The output of D flip-flop 1 lags behind the clock of D flip-flop 1, which ensures that the input of D flip-flop 1 can be sampled.

As shown in Figure 3, the sequence detector includes two identical sequence detectors 1 and 2. The function of each sequence detector is to judge the input signal, which is used for switching from PWM to PSM mode and from PSM to PSM respectively. Detection of PWM mode switching. When the sequence detector detects a low-level input signal for N consecutive clock cycles, it outputs a high level (the value of N can be set between 4 and 8 according to the actual situation), otherwise the output remains low. The sequence detector reduces the influence of the offset voltage of the comparator, and through the detection of the input signal for N consecutive clock cycles, the slight disturbance of the current will not cause frequent switching of the modulation mode of the main switch tube.

Two sequence detectors are respectively used to detect the continuous high level and low level of the comparator output signal comp_out, wherein the sequence detector 1 is used to detect the continuous low level of the comparator output, and the input of the sequence detector 2 is a D flip-flop The inverting output of 1 is used to detect the continuous high level of the output of the comparator.

When switching from PSM to PWM, compare the drain terminal voltage SW of the main switch with vref1. If SW is less than vref1, the comparator outputs a high level. If the output is high for N consecutive clock cycles, it means that the current on the main switch is too large. At this time, it means that the PSM modulation mode is no longer suitable and needs to be switched to PWM control. model. When the PWM switches to the PSM, compare the main switch drain voltage SW with vref0. If SW is greater than vref0, the comparator outputs a low level. If the output is low for N consecutive clock cycles, it means that the load is too small, and the PWM control mode can no longer obtain higher efficiency than the PSM modulation mode. It needs to be switched to the PSM modulation mode. . It is worth noting that D0 and D1 are two internal control signals with opposite phases, which are used to control the generation of two voltage references vref0 and vref1, and vref0 is smaller than vref1 to achieve hysteresis.

The selector is used for final mode control, and the output signal of D flip-flop 2 is used as the input signal of the control input terminal S of the selector. When the input signal of the control input terminal S is high level, the PWM modulation signal is selected as the output and used as the main switch tube. The gate control signal vg; when the input signal of the control input terminal S is low, the PSM modulation signal is selected as the output and used as the gate control signal vg of the main switch. The output of the D flip-flop 2 generates the control signal D0 through the delayer 2 , and the control signal D0 generates the control signal D1 through the inverter 2 . When the system works in PWM modulation mode, the input signal of the control input terminal S is high level, that is, D0 is high (delayed), and D1 is low. For the sequence detector 1, when D0 is high, it can be known from the nature of the AND gate that D0 has no effect on the signal ANDed with it, and the signal ANDed with it seems to pass through directly; for the sequence detector 2, D1 is low, and it can be seen from the nature of the AND gate that no matter whether the output of the sequence detector 2 is high or low, the result is always low; and then by the nature of the OR gate, the low level is ORed with other signals, and no other Influences the signal it ORs with. Therefore, it can be concluded that when the system works in PWM modulation mode, sequence detector 2 is shielded, and the AND signal of sequence detector 1 and D0 is transmitted to the clock input terminal of D flip-flop 2 as it is through the OR gate. Similarly, when the system works in the PSM modulation mode, D0 is low, sequence detector 1 is shielded, and the AND signal of the output signal of sequence detector 2 and D1 passes through the OR gate, and is transmitted to the clock input terminal of D flip-flop 2 as it is. .

The working process of the PWM or PSM dual-mode modulation control circuit for switching regulated power supply provided by the present invention includes: (1) the switching process from PWM to PSM: at the beginning moment, the system works in the PWM state, D0 is high, and D1 is low . In the process of load reduction, the drain terminal voltage SW of the main switch tube gradually increases, and compared with vref0, a periodic square wave comp_out is generated, and the delayer 1 delays this square wave to eliminate possible existence in the circuit adventure phenomenon. The delayed waveform passes through D flip-flop 1 and is sampled on the rising edge of the clock, and the sampling result is d_out. d_out then enters the sequence detector. As can be seen from the previous description, when the PWM switches to the PSM mode, the output of the next sequence detector 2 is shielded. Therefore, only the output of the sequence detector 1 is concerned at this time. When the output of the sequence detector 1 detects that the output of the D flip-flop 1 is low level in N clock cycles continuously, it is considered that the load is too small, and the sequence detector 1 outputs a high level at this time. This high level is ANDed with D0, which is also high, and the result is still high, which is transmitted to the clock input terminal of D flip-flop 2. On the rising edge of this high level, the input of D flip-flop 2 is sampled (that is, the upper The inverting output of D flip-flop 2 at a moment), since the system is working in PWM mode at this time, S is still in a high state at this time and has not changed, that is, the inverting output of D flip-flop 2 is low at the previous moment, that is, the current The input of the D flip-flop 2 is low at the moment, so the output of the D flip-flop 2 is low at the current moment, the selector controls the input terminal S to be low, and the selector selects the PSM modulation signal output as the gate control signal vg of the main switching tube, and finally Realized the switching from PWM to PSM. (2) When switching from PSM to PWM, the system starts to work in PSM state, S, D0 is low, and D1 is high. As the peripheral load gradually increases, the drain terminal voltage SW of the main switch tube gradually decreases, and compared with vref1, it is the same as switching from PWM to PSM. After the output of the comparator is delayed, it is sampled by D flip-flop 1, and D trigger The inverted output signal of device 1 is sent to sequence detector 2 for detection. If it is low for N consecutive clock cycles, that is to say, if d_out is high for N consecutive clock cycles, it is considered that the load is too large, and a high current is generated. flat. It can be seen from the previous description that when D0 is low, the upper path is shielded, and the output signal of sequence detector 2 is transmitted to the clock input terminal of D flip-flop 2. On the rising edge of this high level, the input of D flip-flop 2 is sampled. (that is, the inverted output of D flip-flop 2 at the last moment), since S is low, that is, the inverted output of D flip-flop 2 at the last moment is high, so the output of D flip-flop at the current moment is high, and the selector selects The PWM modulation signal is output and used as the gate control signal vg of the main switching tube, and finally realizes the switching from PSM to PWM.

Claims (3)

1. A PWM or PSM dual-mode modulation control circuit for a switching regulated power supply, comprising a controllable current reference source Iref, a comparator comp and a switching control circuit Load_SM; The controllable current reference source Iref is composed of four NMOS transistors, three PMOS transistors and a bias current source _IB ; three PMOS transistors M01, M02 and M03 are connected in series, that is, the drain of M01 is connected to the source of M02, and M02 The drain of M03 is connected to the source of M03, the source of M01 is connected to the input voltage Vin; the gates of NMOS transistors MB, M0 and M1 are interconnected, the sources of NMOS transistors MB, M0 and M1 are interconnected, and the drain of NMOS transistor MB Connect the bias current source I _B after shorting the grid; the drain of the NMOS transistor M0 is connected to the source of the NMOS transistor M2, the drain of the NMOS transistor M1 is connected to the source of the NMOS transistor M3; the drains of the NMOS transistors M2 and M3 Interconnected and connected to the drain of the PMOS transistor M03; The drain of the PMOS transistor M03 is connected to the positive input terminal of the comparator comp, and the drain voltage SW of the main switching tube in the external switching regulated power supply is connected to the negative input terminal of the comparator comp; The switching control circuit Load_SM is composed of two D flip-flops, two delayers, two inverters, two sequence detectors, two AND gates, an OR gate and a selector; the output terminal of the comparator comp Connect to the input terminal of delayer 1; the output terminal of delayer 1 is connected to the data input terminal of D flip-flop 1, the output terminal of inverter 1 is connected to the clock terminal of D flip-flop 1; the non-inverting output terminal of D flip-flop 1 is connected to the sequence The input terminal of the detector 1, the inverting output terminal of the D flip-flop 1 is connected to the input terminal of the sequence detector 2; the output terminal of the sequence detector 1 is connected to an input terminal of the AND gate 1, and the output terminal of the sequence detector 2 is connected to the AND gate. One input terminal of gate 2; the output signals of AND gate 1 and AND gate 2 are respectively used as two input signals of OR gate, and the output signal of OR gate is used as the clock signal of D flip-flop 2; the inverting output terminal of D flip-flop 2 It is short-circuited with the data input terminal, and the non-inverting output terminal of the D flip-flop 2 is respectively connected to the input terminal of the delayer 2 and the control input terminal S of the selector; the control signal D0 output by the delayer 2 is simultaneously connected to the input terminal of the inverter 2, The other input terminal of AND gate 1 is connected to the gate of NMOS transistor M2 in the controllable current reference source Iref, and the control signal D1 output by inverter 2 is connected to the other input terminal of AND gate 2 and the controllable current reference source Iref at the same time. The gate of the NMOS transistor M3; the two selection input terminals of the selector input the PSM or PWM modulation signal respectively. When the control input terminal S is at a high level, the PWM modulation signal is selected as the output signal; when the control input terminal S is at a low level , select the PSM modulation signal as the output signal; the output signal of the selector is respectively used as the gate control signal of the main switch tube in the external switching regulated power supply and the gate control signal of the three PMOS transistors M01, M02 and M03 in the controllable current reference source Iref , At the same time, the output signal of the selector is used as the clock signal of the D flip-flop 1 after being inverted by the inverter 1. 2. the PWM or PSM dual-mode modulation control circuit that is used for switching regulated power supply according to claim 1, is characterized in that, two sequence detectors in the described switching control circuit Load_SM are identical sequence detectors, when When the sequence detector detects a low-level input signal for N consecutive clock cycles, it outputs a high level, otherwise the output remains low. 3 . The PWM or PSM dual-mode modulation control circuit for switching regulated power supplies according to claim 2 , wherein the value range of N is between 4 and 8. 4 .

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