CN101976542A - Pixel driving circuit - Google Patents

Abstract

The invention provides a pixel driving circuit, comprising: the display device comprises a first pixel, a second pixel and a data driving circuit, wherein each pixel comprises a main area and a sub-area, and the main area and the sub-area store corresponding gray scale voltages when displaying a picture. In the data driving circuit, a first selection circuit inputs a first digital data corresponding to the first pixel and a second digital data corresponding to the second pixel to the corresponding digital-to-analog converter to generate a first gray scale voltage, a second gray scale voltage, a third gray scale voltage and a fourth gray scale voltage, and a second selection circuit distributes the gray scale voltages to a main region and a sub-region of the first pixel and the second pixel. This reduces the number of digital-to-analog converters required for the data driving circuit. The invention can reduce the number of digital-to-analog converters required by the data driving circuit, save the cost of the pixel driving circuit and reduce the power consumption.

Description

Pixel drive circuit

technical field

The present invention relates to a pixel driving circuit, and more particularly, the present invention relates to a pixel driving circuit capable of reducing the number of digital-to-analog converters required for its data driving circuit.

Background technique

Please refer to Figure 1. FIG. 1 is a schematic diagram illustrating a pixel driving circuit 100 capable of reducing color washout in the related art. The pixel driving circuit 100 includes a plurality of pixels, data lines DL ₁ ˜DL _M , scanning lines SL ₁ ˜SL _N , a data driving circuit 110 and a scanning driving circuit 120 . The structures of the plurality of pixels are illustrated by taking the pixels PIX ₁ and PIX ₂ as examples. The pixel PIX ₁ includes transistors Q ₁ and Q ₂ , a main region MR ₁ and a sub-region SR ₁ . The transistor _Q1 includes a first electrode (1), a second electrode (2) and a gate (G). A first electrode of the transistor Q ₁ is coupled to the data line DL _X , a second electrode of the transistor Q ₁ is coupled to the main region MR ₁ , and a gate of the transistor Q ₁ is coupled to the scan line SL _Y . The transistor _Q2 includes a first electrode (1), a second electrode (2) and a gate (G). A first electrode of the transistor Q ₂ is coupled to the data line DL _(X+1) , a second electrode of the transistor Q ₂ is coupled to the sub-region SR ₁ , and a gate of the transistor Q ₂ is coupled to the scan line SL _Y . The pixel PIX ₂ includes transistors Q ₃ and Q ₄ , a main region MR ₂ and a sub-region SR ₂ . The transistor _Q3 includes a first electrode (1), a second electrode (2) and a gate (G). A first electrode of the transistor Q ₃ is coupled to the data line DL _{(X+2 )} , a second electrode of the transistor Q ₃ is coupled to the sub-region SR ₂ , and a gate of the transistor Q ₃ is coupled to the scan line SL _Y . The transistor _Q4 includes a first electrode (1), a second electrode (2) and a gate (G). A first electrode of the transistor Q ₄ is coupled to the data line DL _{(X+3 )} , a second electrode of the transistor Q ₄ is coupled to the main region MR ₂ , and a gate of the transistor Q ₄ is coupled to the scan line SL _Y . When the scan driving circuit 120 drives the scan line SL _Y , the transistors Q ₁ -Q ₄ are turned on, so that the main region MR ₁ is coupled to the data line DL _X through the transistor Q 1 , and the sub-region SR ₁ is coupled to the data line DL _X through the transistor Q ₂ . connected to the data line DL _(X+1 ), the sub-region SR ₂ is coupled to _the data line DL _(X+2) through the transistor _Q3 , and the main region MR ₂ is coupled to the data line DL _{(X +3)} . Assuming that the pixel PIX ₁ intends to display an image corresponding to the digital data DA ₁ , and the pixel PIX ₂ intends to display an image corresponding to the digital data DA ₂ , then in the pixel PIX ₁ at this time, the main region MR ₁ and the sub-region SR ₁ are transparent respectively. The gray scale voltage corresponding to the digital data DA ₁ is received and stored from the data driving circuit 110 through the data lines D _X and D _(X+1) , and in the pixel PIX ₂ , the main region MR ₂ and the sub-region SR ₂ pass through the The data lines D _(X+3) and D _(X+2) receive and store gray scale voltages corresponding to the digital data DA ₂ from the data driving circuit 110 . In addition, the potential of the grayscale voltage stored in the main region _MR1 corresponds to the potential of the grayscale voltage stored in the subregion _SR1 , and the potential of the grayscale voltage stored in the main region _MR2 corresponds to the potential of the grayscale voltage stored in the subregion _SR2 . The potentials of the voltages also correspond to each other, so the color shift phenomenon when viewing the pixel driving circuit 100 from different viewing angles can be reduced.

However, in the pixel driving circuit 100, the main region _MR1 and the subregion _SR1 store different grayscale voltages, the main region _MR2 and the subregion _SR2 also store different grayscale voltages, and each region ( _MR1 , MR ₂ , SR ₁ , SR ₂ ) can be positive or negative, so for each data line DL _X ˜DL _(X+3) , the data driving circuit 110 needs a corresponding digital-to-analog converter A corresponding negative polarity digital-to-analog converter is used to provide positive grayscale voltages or negative grayscale voltages to the main regions MR ₁ , MR ₂ and the sub-regions SR ₁ , SR ₂ . In other words, when the pixel driving circuit 100 has M data lines, the data driving circuit 110 needs to have 2M digital-to-analog converters. Since the digital-to-analog converter occupies a large circuit area, the cost of the data driving circuit 110 will increase significantly, and the power consumption of the pixel driving circuit 100 will also be increased, which brings great inconvenience to users.

Contents of the invention

In order to overcome the above defects in the prior art, the present invention provides a pixel driving circuit. The pixel driving circuit includes a first pixel, a second pixel, and a data driving circuit. The first pixel includes a first main area and a first sub-area. The first main area is coupled to a first data line and a scan line. The first sub-region is coupled to a second data line and the scan line. The first main area and the first sub-area respectively store gray scale voltages corresponding to a first digital data. The second pixel includes a second main area and a second sub-area. The second sub-region is coupled to a third data line and the scan line. The second main area is coupled to a fourth data line and the scan line. The second main area and the second sub-area respectively store gray scale voltages corresponding to a second digital data. The data driving circuit includes a first digital-to-analog converter, a second digital-to-analog converter, a third digital-to-analog converter, a fourth digital-to-analog converter, a first selection circuit, and a second selection circuit. The first digital-to-analog converter is used for converting the first digital data or the second digital data into a first gray scale voltage according to a positive polarity main region Gamma voltage. The second digital-to-analog converter is used to convert the first digital data or the second digital data into a second gray scale voltage according to a positive polarity sub-region Gamma voltage. The third digital-to-analog converter is used to convert the first digital data or the second digital data into a third grayscale voltage according to a negative sub-region Gamma voltage. The fourth digital-to-analog converter is used for converting the first digital data or the second digital data into a fourth gray scale voltage according to a negative main area Gamma voltage. The first selection circuit is used to select the first digital data according to a gamma voltage selection signal and a polarity signal, and input them to the first digital-to-analog converter, the second digital-to-analog converter, and the third digital-to-analog converter. converter and two DACs of the fourth DAC, and input the second digital data to the other two DACs. The second selection circuit is used for transmitting the first gray-scale voltage, the second gray-scale voltage, the third gray-scale voltage and the fourth gray-scale voltage through the gamma voltage selection signal and the polarity signal. The first data line, the second data line, the third data line, and the fourth data line are allocated to the first main area, the first sub area, the second main area and the second sub area.

The invention can reduce the number of digital-to-analog converters required by the data driving circuit, thereby saving the cost of the pixel driving circuit and reducing power consumption.

Description of drawings

FIG. 1 is a schematic diagram illustrating a pixel driving circuit in the related art.

FIG. 2 is a schematic diagram illustrating an embodiment of a pixel driving circuit of the present invention.

FIG. 3 is a schematic diagram illustrating a partial structure of the data driving circuit in FIG. 2 .

4 and 5 are schematic diagrams illustrating how to use the data driving circuit in FIG. 3 to distribute correct grayscale voltages to pixels in the pixel driving circuit in FIG. 2 .

FIG. 6 is a schematic diagram illustrating another embodiment of the pixel driving circuit of the present invention.

7 and 8 are schematic diagrams illustrating how to use the data driving circuit in FIG. 3 to distribute correct grayscale voltages to pixels in the pixel driving circuit in FIG. 6 .

FIG. 9 is a schematic diagram illustrating another embodiment of the pixel driving circuit of the present invention.

FIG. 10 is a schematic diagram illustrating a partial structure of the data driving circuit in FIG. 9 .

Wherein, the reference signs are explained as follows:

1, 2 Electrodes

100, 200, 600, 900 Pixel drive circuit

120, 220 Gate drive circuit

210, 110 Data drive circuit

211, 212 Select circuit

2111 Mutual exclusion or gate

2121, 2122 Polarity selection circuit

BUF ₁ ~ BUF ₄ buffers

C Control Terminal

DA ₁ , DA ₂ digital data

DAC ₁ ~ DAC ₄ digital to analog converter

DL ₁ ~ DL _M data line

DH ₁ ～DH ₄ latch

G Gate

I ₁ , 1 ₂ input terminals

LS ₁ ~ LS ₄ level shifter

MUX ₁ ~ MUX ₈ multiplexer

MR ₁ , MR ₂ main area

O, O ₁ , O ₂ output terminals

PIX ₁ , PIX ₂ pixels

Q ₁ ~ Q ₄ transistors

S _C control signal

S _{G_SEL} Gamma voltage selection signal

S _POL polarity signal

SL ₁ ～SL _N scanning line

SR ₁ , SR ₂ sub-regions

V _G1 ~ V _G4 grayscale voltage

Detailed ways

Please refer to Figure 2 and Figure 3. FIG. 2 is a schematic diagram illustrating an embodiment 200 of the pixel driving circuit of the present invention. FIG. 3 is a schematic diagram illustrating a partial structure of the data driving circuit 210 in FIG. 2 . The pixel driving circuit 200 includes a plurality of pixels, data lines DL ₁ ˜DL _M , scanning lines SL ₁ ˜SL _N , a data driving circuit 210 and a scanning driving circuit 220 . The structures of the plurality of pixels are illustrated by taking the pixels PIX ₁ and PIX ₂ as examples. The pixel PIX ₁ includes transistors Q ₁ and Q ₂ , a main region MR ₁ and a sub-region SR ₁ . The transistor _Q1 includes a first electrode (1), a second electrode (2) and a gate (G). A first electrode of the transistor Q ₁ is coupled to the data line DL _X , a second electrode of the transistor Q ₁ is coupled to the main region MR ₁ , and a gate of the transistor Q ₁ is coupled to the scan line SL _Y . The transistor _Q2 includes a first electrode (1), a second electrode (2) and a gate (G). A first electrode of the transistor Q ₂ is coupled to the data line DL _(X+1) , a second electrode of the transistor Q ₂ is coupled to the sub-region SR ₁ , and a gate of the transistor Q ₂ is coupled to the scan line SL _Y . The pixel PIX ₂ includes transistors Q ₃ and Q ₄ , a main region MR ₂ and a sub-region SR ₂ . The transistor _Q3 includes a first electrode (1), a second electrode (2) and a gate (G). A first electrode of the transistor Q ₃ is coupled to the data line DL _{(X+2 )} , a second electrode of the transistor Q ₃ is coupled to the sub-region SR ₂ , and a gate of the transistor Q ₃ is coupled to the scan line SL _Y . The transistor _Q4 includes a first electrode (1), a second electrode (2) and a gate (G). A first electrode of the transistor Q ₄ is coupled to the data line DL _{(X+3 )} , a second electrode of the transistor Q ₄ is coupled to the main region MR ₂ , and a gate of the transistor Q ₄ is coupled to the scan line SL _Y . When the scan driving circuit 220 drives the scan line SL _Y , the transistors Q ₁ -Q ₄ are turned on, so that the main region MR ₁ is coupled to the data line DL _X through the transistor Q 1 , and the sub-region SR ₁ is coupled to the data line DL _X through the transistor Q ₂ . connected to the data line DL _(X+1) , the sub-region SR ₂ is coupled to _the data line DL _(X+2) through the transistor _Q3 , and the main region MR ₂ is coupled to the data line DL _{(X +3)} . Assuming that the pixel PIX ₁ intends to display an image corresponding to the digital data DA ₁ , and the pixel PIX ₂ intends to display an image corresponding to the digital data DA ₂ , then in the pixel PIX ₁ at this time, the main region MR ₁ and the sub-region SR ₁ are transparent respectively. The gray scale voltage corresponding to the digital data DA ₁ is received and stored from the data driving circuit 210 through the data lines D _X and D _(X+1) , and in the pixel PIX ₂ , the main region MR ₂ and the sub-region SR ₂ pass through the The data lines D _(X+3) and D _(X+2) receive and store grayscale voltages corresponding to the digital data DA ₂ from the data driving circuit 210 , so as to reduce color shift when viewing the pixel driving circuit 200 from different viewing angles.

FIG. 3 shows the structure of the data driving circuit 210 for driving the data lines DL _X ˜DL _(X+3) . As for the structure of the data driving circuit 210 for driving other data lines, the same can be deduced. The data driving circuit 210 includes digital-to-analog converters DAC ₁ -DAC ₄ , selection circuits 211 and 212 , data latches DH ₁ -DH ₄ , and level shifters LS ₁ -LS ₄ . The selection circuit 211 selects the digital data DA ₁ according to the gamma voltage selection signal S _{G_SEL} and the polarity signal S _POL , and inputs the digital data DA 1 to two of the digital-analog converters DAC ₁ -DAC ₄ , and converts the digital data DA ₂ Input to two other DACs. The data latches DH ₁ -DH ₄ are used to latch the digital data output by the selection circuit 211 . The level shifters LS ₁ -LS ₄ are used to increase the potential of the digital data output by the data latches DH ₁ -DH ₄ . The digital-to-analog converter DAC ₁ converts the digital data (DA ₁ or DA ₂ ) output by the level shifter LS ₁ into a gray scale voltage V _G1 according to the positive polarity main area gamma voltage V _PA . The digital-to-analog converter DAC ₂ is level-coupled to the output terminal O of the multiplexer MUX ₄ according to the positive polarity sub-region Gamma voltage V _PB . In this embodiment, when the control signal S _C represents logic "0", the input terminals _I1 of the multiplexers MUX ₁ -MUX ₄ are respectively coupled to the output terminals O of the multiplexers MUX ₁ -MUX ₄ ; when the control signal When S _C represents logic “1”, the input terminals I ₂ of the multiplexers MUX ₁ -MUX ₄ are respectively coupled to the output terminals O of the multiplexers MUX ₁ -MUX ₄ .

The data latches DH ₁ to DH ₄ are respectively coupled between the selection circuit 211 and the level shifters LS ₁ to LS ₄ , and the data latches DH ₁ to DH ₄ are respectively used to latch the input of the selection circuit 211 to the digital analog Digital data of converters DAC ₁ to DAC ₄ . The level shifters LS ₁ -LS ₄ are respectively coupled between the selection circuit 211 and the digital-to-analog converters DAC ₁ -DAC ₄ through the data latches DH ₁ -DH ₄ , and the level shifters LS ₁ -LS ₄ are respectively It is used to increase the potential of the digital data input from the selection circuit 211 to the digital-to-analog converters DAC ₁ -DAC ₄ .

The selection circuit 212 includes multiplexers MUX ₅ -MUX ₈ , buffers BUF ₁ -BUF ₄ , and polarity selection circuits 2121 and 2122 . The multiplexer MUX ₅ includes an input terminal I ₁ for receiving the gray scale voltage V _G2 , an input terminal I ₂ for receiving the gray scale voltage V _G1 , a control terminal C for receiving the control signal S _C , and an output terminal O. The multiplexer MUX ₅ couples the input terminal _I1 or _I2 of the multiplexer MUX ₅ to the output terminal O of the multiplexer MUX ₅ according to the control signal _SC . The multiplexer MUX ₆ includes an input terminal I ₁ for receiving the gray scale voltage V _G4 , an input terminal I ₂ for receiving the gray scale voltage V _G3 , a control terminal C for receiving the control signal S _C , and an output terminal O. The multiplexer MUX ₆ couples the input terminal _I1 or _I2 of the multiplexer MUX ₆ to the output terminal O of the multiplexer MUX ₆ according to the control signal S _C . The multiplexer MUX ₇ includes an input terminal I ₁ for receiving the gray scale voltage V _G1 , an input terminal I ₂ for receiving the gray scale voltage V _G2 , a control terminal C for receiving the control signal S _C , and an output terminal O. The multiplexer MUX ₇ couples the input terminal _I1 or _I2 of the multiplexer MUX ₇ to the output terminal O of the multiplexer MUX ₇ according to the control signal S _C . The multiplexer MUX ₈ includes an input terminal I ₁ for receiving the gray scale voltage V _G3 , an input terminal I ₂ for receiving the gray scale voltage V _G4 , a control terminal C for receiving the control signal S _C , and an output terminal O. The multiplexer MUX ₈ couples the input terminal _I1 or _I2 of the multiplexer MUX ₈ to the output terminal O of the multiplexer MUX ₈ according to the control signal S _C . When the control signal S _C represents logic "0", the input terminals _I1 of the multiplexers MUX ₅ - MUX ₈ are respectively coupled to the output terminals O of the multiplexers MUX ₅ - MUX ₈ ; when the control signal S _C represents logic "1 ”, the input terminals I ₂ of the multiplexers MUX ₅ -MUX ₈ are respectively coupled to the output terminals O of the multiplexers MUX ₅ -MUX ₈ .

The polarity selection circuit 2121 includes an input terminal _I1 coupled to the output terminal O of the multiplexer MUX ₅ , an input terminal _I2 coupled to the output terminal O of the multiplexer MUX ₆ , and an output terminal _O1 coupled to the data line _DLx , The output terminal O ₂ is coupled to the data line DL _(X+1) , and the control terminal C is used to receive the polarity signal S _POL , and the digital data (DA ₁ or DA ₂ ) output by the polarity converter LS ₂ is converted into gray step voltage V _G2 . The digital-to-analog converter DAC ₃ converts the digital data (DA ₁ or DA ₂ ) output by the level shifter LS ₃ into a gray scale voltage V _G3 according to the negative polarity sub-region gamma voltage V _NB . The digital-to-analog converter DAC ₄ converts the digital data (DA ₁ or DA ₂ ) output by the level shifter LS ₄ into a gray scale voltage V _G4 according to the negative polarity main area gamma voltage V _NA . The selection circuit 212 distributes the grayscale voltages V _G1 -V _G4 to the main regions MR ₁ and MR 2 and the sub-regions MR 1 and MR ₂ through the data lines DL _X ˜DL _(X+3) according to the gamma voltage selection signal S _{G_SEL} and the polarity signal S _POL . Region SR ₁ and SR ₂ . In the data driving circuit 210, the digital data DA ₁ corresponding to the pixel PIX ₁ and the digital data DA ₂ corresponding to the pixel PIX ₂ are input to corresponding digital-to-analog converters through the selection circuit 211 to generate the gray scale voltage V _G1 ~V _G4 , and the gray-scale voltage V _G1 ~V _G4 is distributed to the main regions MR ₁ and MR 2 and the sub-regions SR ₁ and _{SR 2 in} the pixels PIX ₁ and PIX ₂ through the selection circuit 212, so that the data driving can be reduced The number of digital-to-analog converters required for circuit 210. The working principle will be further explained below.

The selection circuit 211 includes an exclusive OR gate (XOR gate) 2111 and multiplexers MUX ₁ -MUX ₄ . The exclusive OR gate 2111 performs logic operation according to the gamma voltage selection signal S _{G_SEL} and the polarity signal S _POL to generate the control signal S _C . When the gamma voltage selection signal S _{G_SEL} and the polarity signal S _POL both represent logic “0” or both represent logic “1”, the control signal S _C represents logic “0”; when the gamma voltage selection signal S _{G_SEL} represents logic “ 0" and the polarity signal S _POL represents logic "1", the control signal S _C represents logic "1"; when the gamma voltage selection signal S _{G_SEL} represents logic "1" and the polarity signal S _POL represents logic "0" , the control signal S _C represents logic "1". The multiplexer MUX ₁ includes an input terminal I ₁ for receiving digital data DA ₂ , an input terminal I ₂ for receiving digital data DA ₁ , and a control terminal C for receiving a control signal S _C . The multiplexer MUX ₁ couples the input terminal I ₁ or I ₂ of the multiplexer MUX ₁ to the output terminal O of the multiplexer MUX ₁ according to the control signal S _C . The multiplexer MUX ₂ includes an input terminal I ₁ for receiving digital data DA ₁ , an input terminal I ₂ for receiving digital data DA ₂ , and a control terminal C for receiving a control signal S _C . The multiplexer MUX ₂ couples the input terminal _I1 or _I2 of the multiplexer MUX ₂ to the output terminal O of the multiplexer MUX ₂ according to the control signal S _C . The multiplexer MUX ₃ includes an input terminal I ₁ for receiving digital data DA ₂ , an input terminal I ₂ for receiving digital data DA ₁ , and a control terminal C for receiving a control signal S _C . The multiplexer MUX ₃ couples the input terminal _I1 or _I2 of the multiplexer MUX ₃ to the output terminal O of the multiplexer MUX ₃ according to the control signal S _C . The multiplexer MUX ₄ includes an input terminal I ₁ for receiving digital data DA ₁ , an input terminal I ₂ for receiving digital data DA ₂ , and a control terminal C for receiving a control signal S _C . The multiplexer MUX ₄ selects the input terminal _I1 or _I2 of the multiplexer MUX ₄ according to the control signal S _C. The selection circuit 2121 selects one of the input terminals _I1 and _I2 of the polarity selection circuit 2121 according to the polarity signal S _POL One input terminal is coupled to the output terminal O ₁ of the polarity selection circuit 2121 , and the other input terminal is coupled to the output terminal O ₂ of the polarity selection circuit 2121 . The polarity selection circuit 2122 includes an input terminal _I1 coupled to the output terminal O of the multiplexer MUX ₇ , an input terminal _I2 coupled to the output terminal O of the multiplexer MUX ₈ , and an output terminal _O1 coupled to the data line DL _{(X +2)} , the output terminal O ₂ is coupled to the data line DL _(X+3) , and the control terminal C is used to receive the polarity signal S _POL , the polarity selection circuit 2122 switches the polarity selection circuit 2122 according to the polarity signal S _POL One of the input terminals I ₁ and I ₂ is coupled to the output terminal O ₁ of the polarity selection circuit 2122 , and the other input terminal is coupled to the output terminal O ₂ of the polarity selection circuit 2122 . When the polarity signal S _POL represents logic “0”, the input terminals I ₁ of the polarity selection circuits 2121 and 2122 are respectively coupled to the output terminal O ₂ , and the input terminals I ₂ of the polarity selection circuits 2121 and 2122 are respectively coupled to connected to its output terminal O ₁ ; when the polarity signal S _POL represents a logic "1", the input terminals I ₁ of the polarity selection circuits 2121 and 2122 are respectively coupled to their output terminals O ₁ , and the polarity selection circuits 2121 and 2122 The input terminals I ₂ of the 2122 are respectively coupled to the output terminals O ₂ .

The buffer BUF ₁ is coupled between the output terminal O of the multiplexer MUX ₅ and the input terminal _I1 of the polarity selection circuit 2121, and the buffer BUF ₁ is used to buffer the gray output from the output terminal O of the multiplexer MUX ₅ step voltage. The buffer BUF ₂ is coupled between the output terminal O of the multiplexer MUX ₆ and the input terminal I ₂ of the polarity selection circuit 2121, and the buffer BUF ₂ is used to buffer the gray output from the output terminal O of the multiplexer MUX ₆ step voltage. The buffer BUF ₃ is coupled between the output terminal O of the multiplexer MUX ₇ and the input terminal _I1 of the polarity selection circuit 2122, and the buffer BUF ₃ is used to buffer the gray output from the output terminal O of the multiplexer MUX ₇ step voltage. The buffer BUF ₄ is coupled between the output terminal O of the multiplexer MUX ₈ and the input terminal I ₂ of the polarity selection circuit 2122, and the buffer BUF ₄ is used to buffer the gray output from the output terminal O of the multiplexer MUX ₈ step voltage.

Please refer to Figure 4. FIG. 4 illustrates the data driving circuit 210 when the inversion polarities of the main region MR ₁ , sub-region SR ₁ , sub-region SR ₂ , and main region MR ₂ in the pixel driving circuit 200 are positive, negative, positive, and negative, respectively. Schematic diagram of the operation. At this time, the gamma voltage selection signal S _{G_SEL} represents logic "0", and the polarity signal S _POL represents logic "1", so the exclusive OR gate 2111 outputs the control signal S _C representing logic "1". When the control signal S _C represents logic “1”, the input terminals I ₂ of the multiplexers MUX ₁ -MUX ₄ are respectively coupled to the output terminals O of the multiplexers MUX ₁ -MUX ₄ . In this way, the multiplexer MUX ₁ outputs the digital data DA ₁ to the digital-analog converter DAC ₁ through the latch DH ₁ and the level shifter LS ₁ , and the multiplexer MUX ₂ passes through the latch DH ₂ and the level shifter LS ₂ outputs digital data DA ₂ to digital-to-analog converter DAC _{2 ,} multiplexer MUX ₃ outputs digital data DA ₁ to digital-to-analog converter DAC 3 through latch DH ₃ and level shifter LS ₃ , and more The router MUX ₄ outputs the digital data DA ₂ to the digital-to _- analog converter DAC 4 through the latch DH ₄ and the level shifter LS ₄ . The digital-to-analog converter DAC ₁ converts the digital data DA ₁ into a gray scale voltage V _G1 according to the positive polarity main area gamma voltage V _PA . The digital-to-analog converter DAC ₂ converts the digital data DA ₂ into a grayscale voltage V _G2 according to the positive polarity sub-region Gamma voltage V _PB . The digital-to-analog converter DAC ₃ converts the digital data DA ₁ into a grayscale voltage V _G3 according to the negative polarity sub-region Gamma voltage V _NB . The digital-to-analog converter DAC ₄ converts the digital data DA ₂ into a gray scale voltage V _G4 according to the negative polarity main area gamma voltage V _NA . At this time, the multiplexers MUX ₅ -MUX ₈ respectively couple the input terminal I ₂ of MUX ₅ -MUX ₈ to the output terminal O of MUX ₅ -MUX ₈ according to the control signal _Sc indicating logic "1". In this way, the multiplexer MUX ₅ outputs the gray scale voltage V _G1 to the input terminal I ₁ of the polarity selection circuit 2121 through the buffer BUF 1 , _and the multiplexer MUX ₆ outputs the gray scale voltage V _G3 to the polarity selection through the buffer BUF ₂ The input terminal I ₂ of the circuit 2121, the multiplexer MUX ₇ outputs the grayscale voltage V _G2 to the input terminal I ₁ of the polarity selection circuit 2122 through the buffer BUF ₃ , and the multiplexer MUX ₈ outputs the gray scale voltage V G2 through the buffer BUF ₄ The step voltage V _G4 is sent to the input terminal I ₂ of the polarity selection circuit 2122 . Since the polarity signal S _POL represents logic “1”, the input terminals I ₁ of the polarity selection circuits 2121 and 2122 are respectively coupled to their output terminals O ₁ , and the input terminals I ₂ of the polarity selection circuits 2121 and 2122 are respectively coupled to Connected to its output O ₂ . In this way, the polarity selection circuit 2121 outputs the gray scale voltage V _G1 obtained by converting the digital data DA ₁ according to the positive polarity main area gamma voltage V _PA to the main area MR ₁ through the data line DL _X , and the polarity selection circuit 2121 outputs the gray scale voltage V _G3 obtained by converting the digital data DA ₁ according to the negative polarity sub-region Gamma voltage V _NB to the sub-region SR ₁ through the data line DL _(X+1) . The polarity selection circuit 2122 outputs the gray-scale voltage V _G2 obtained by converting the digital data DA ₂ according to the positive polarity sub-region Gamma voltage V _PB to the sub-region SR ₂ through the data line DL _(X+2) , and polarity selection The circuit 2122 outputs the gray scale voltage V _G4 obtained by converting the digital data DA ₂ according to the negative main area gamma voltage V _NA to the main area MR ₂ through the data line DL _{(X+3 )} . Therefore, in the pixel driving circuit 200, when the inverted polarities of the main region MR ₁ , the sub-region SR ₁ , the sub-region SR ₂ , and the main region MR ₂ are positive, negative, positive, and negative, respectively, by representing logic “0 The gamma voltage selection signal S _{G_SEL} of " and the polarity signal S _POL representing logic "1" can control the selection circuit 211 to input the digital data DA ₁ and DA ₂ to the corresponding digital-to-analog converters to generate gray-scale voltages V _G1 -V _G4 , and _{control the selection circuit 212 to correctly distribute the gray-scale voltages V G1 -V G4 to the main} regions MR ₁ and MR ₂ and the sub-regions SR ₁ and SR ₂ .

Please refer to Figure 5. FIG. 5 illustrates the data driving circuit 210 when the inversion polarities of the main region MR ₁ , sub-region SR ₁ , sub-region SR ₂ , and main region MR ₂ in the pixel driving circuit 200 are negative, positive, negative, and positive, respectively. Schematic diagram of the operation. At this time, the gamma voltage selection signal S _{G_SEL} represents logic "0", and the polarity signal S _POL represents logic "0", so the exclusive OR gate 2111 outputs the control signal S _C representing logic "0". When the control signal S _C represents logic “0”, the input terminals I ₁ of the multiplexers MUX ₁ -MUX ₄ are respectively coupled to the output terminals O of the multiplexers MUX ₁ -MUX ₄ . In this way, the multiplexer MUX ₁ outputs the digital data DA ₂ to the digital-analog converter DAC ₁ through the latch DH ₁ and the level shifter LS ₁ , and the multiplexer MUX ₂ passes through the latch DH ₂ and the level shifter LS ₂ outputs digital data DA ₁ to digital-to-analog converter DAC _{2 ,} multiplexer MUX ₃ outputs digital data DA 2 to digital-to-analog converter DAC ₃ through latch DH ₃ and level shifter LS ₃ , and more The multiplexer MUX ₄ outputs the digital data DA ₁ to the digital-to _- analog converter DAC 4 through the latch DH ₄ and the level shifter LS ₄ . The digital-to-analog converter DAC ₁ converts the digital data DA ₂ into a gray scale voltage V _G1 according to the positive polarity main area gamma voltage V _PA . The digital-to-analog converter DAC ₂ converts the digital data DA ₁ into a grayscale voltage V _G2 according to the positive polarity sub-region Gamma voltage V _PB . The digital-to-analog converter DAC ₃ converts the digital data D _A2 into a gray scale voltage V _G3 according to the negative polarity sub-region Gamma voltage V _NB . The digital-to-analog converter DAC ₄ converts the digital data DA ₁ into a gray scale voltage V _G4 according to the negative polarity main area gamma voltage V _NA . At this time, the multiplexers MUX ₅ -MUX ₈ respectively couple the input terminal I ₁ of MUX ₅ -MUX ₈ to the output terminal O of MUX ₅ -MUX ₈ according to the control signal _Sc representing logic "0". In this way, the multiplexer MUX ₅ outputs the gray scale voltage V _G2 to the input terminal I ₁ of the polarity selection circuit 2121 through the buffer BUF ₁ , and the multiplexer MUX ₆ outputs the gray scale voltage V _G4 to the polarity selection through the buffer BUF ₂ The input terminal I ₂ of the circuit 2121, the multiplexer MUX ₇ outputs the grayscale voltage V _G1 to the input terminal I ₁ of the polarity selection circuit 2122 through the buffer BUF 3 , and the multiplexer MUX ₈ outputs the grayscale voltage _through the buffer BUF ₄ The step voltage V _G3 is sent to the input terminal I ₂ of the polarity selection circuit 2122 . Since the polarity signal S _POL represents logic “0”, the input terminals I ₁ of the polarity selection circuits 2121 and 2122 are respectively coupled to their output terminals O ₂ , and the input terminals I ₂ of the polarity selection circuits 2121 and 2122 are respectively coupled to connected to its output O ₁ . In this way, the polarity selection circuit 2121 outputs the gray scale voltage V _G4 obtained by converting the digital data DA ₁ according to the negative polarity main area gamma voltage V _NA to the main area MR ₁ through the data line DL _X , and the polarity selection circuit The 2121 outputs the gray scale voltage V _G2 obtained by converting the digital data DA ₁ according to the positive polarity sub-region Gamma voltage V _PB to the sub-region SR ₁ through the data line DL _(X+1) . The polarity selection circuit 2122 outputs the gray scale voltage V _G3 obtained by converting the digital data DA ₂ according to the negative polarity sub-region Gamma voltage V _NB to the sub-region SR ₂ through the data line DL _(X+2) , and the polarity is selected The circuit 2122 outputs the gray scale voltage V _G1 obtained by converting the digital data DA ₂ according to the positive main area gamma voltage V _PA to the main area MR ₂ through the data line DL _{(X+3 )} . Therefore, in the pixel driving circuit 200, when the inverted polarities of the main region MR ₁ , the sub-region SR ₁ , the sub-region SR ₂ and the main region MR ₂ are respectively negative, positive, negative and positive, by representing logic “0 The gamma voltage selection signal S _{G_SEL} of " and the polarity signal S _POL representing logic "0" can control the selection circuit 211 to input the digital data DA ₁ and DA ₂ to the corresponding digital-to-analog converters to generate gray-scale voltages _{V G1} -V _G4 , and control the selection circuit 212 to correctly distribute the gray-scale voltages V _{G1 -V G4} to the main regions MR ₁ and MR ₂ and the sub-regions SR ₁ and SR ₂ .

It can be seen from the above description that in the pixel driving circuit 200 of the present invention, for the data lines DL _X ˜DL _(X+3) , the data driving circuit 210 only needs four digital-to-analog converters (DAC ₁ ˜DAC ₄ ), namely The correct gray scale voltage can be provided to the main regions MR ₁ , MR ₂ and the sub-regions SR ₁ , SR ₂ . In other words, when the pixel driving circuit 200 has M data lines, the data driving circuit 210 only needs to have M digital-to-analog converters. Therefore, compared with the pixel driving circuit 100 of the related art, the pixel driving circuit 200 of the present invention can reduce the number of required digital-to-analog converters to save cost and reduce power consumption.

Please refer to Figure 6. FIG. 6 is a schematic diagram illustrating another embodiment 600 of the pixel driving circuit of the present invention. The difference between the pixel driving circuit 600 and 200 is that the second terminal of the transistor Q ₁ is coupled to the sub-region SR ₁ , the second terminal of the transistor Q ₂ is coupled to the main region MR ₁ , and the second terminal of the transistor Q ₃ is coupled to the sub-region SR 1 . Connected to the main region MR ₂ , the second terminal of the transistor Q ₄ is coupled to the sub-region SR ₂ . At this time, the data driving circuit 210 can still be correctly allocated to the main regions MR ₁ and MR ₂ and the sub-regions SR ₁ and SR ₂ , and its working principle will be further described below.

Please refer to Figure 7. FIG. 7 illustrates the data driving circuit 210 when the inversion polarities of the sub-region SR ₁ , the main region MR ₁ , the main region MR ₂ and the sub-region SR ₂ in the pixel driving circuit 600 are respectively positive, negative, positive and negative. Schematic diagram of the operation. At this time, the gamma voltage selection signal S _{G_SEL} represents logic "1", and the polarity signal S _POL represents logic "1", so the exclusive OR gate 2111 outputs the control signal S _C representing logic "0". When the control signal S _C represents logic “0”, the input terminals I ₁ of the multiplexers MUX ₁ -MUX ₄ are respectively coupled to the output terminals O of the multiplexers MUX ₁ -MUX ₄ . In this way, the multiplexer MUX ₁ outputs the digital data DA ₂ to the digital-analog converter DAC ₁ through the latch DH ₁ and the level shifter LS ₁ , and the multiplexer MUX ₂ passes through the latch DH ₂ and the level shifter LS ₂ outputs digital data DA ₁ to digital-to-analog converter DAC _{2 ,} multiplexer MUX ₃ outputs digital data DA 2 to digital-to-analog converter DAC ₃ through latch DH ₃ and level shifter LS ₃ , and more The multiplexer MUX ₄ outputs the digital data DA ₁ to the digital-to _- analog converter DAC 4 through the latch DH ₄ and the level shifter LS ₄ . The digital-to-analog converter DAC ₁ converts the digital data DA ₂ into a gray scale voltage V _G1 according to the positive polarity main area gamma voltage V _PA . The digital-to-analog converter DAC ₂ converts the digital data DA ₁ into a grayscale voltage V _G2 according to the positive polarity sub-region Gamma voltage V _PB . The digital-to-analog converter DAC ₃ converts the digital data DA ₂ into a grayscale voltage V _G3 according to the negative polarity sub-region Gamma voltage V _NB . The digital-to-analog converter DAC ₄ converts the digital data DA ₁ into a gray scale voltage V _G4 according to the negative polarity main area gamma voltage V _NA . At this time, the multiplexers MUX ₅ -MUX ₈ respectively couple the input terminal I ₁ of MUX ₅ -MUX ₈ to the output terminal O of MUX ₅ -MUX ₈ according to the control signal _Sc representing logic "0". In this way, the multiplexer MUX ₅ outputs the gray scale voltage V _G2 to the input terminal I ₁ of the polarity selection circuit 2121 through the buffer BUF ₁ , and the multiplexer MUX ₆ outputs the gray scale voltage V _G4 to the polarity selection through the buffer BUF ₂ The input terminal I ₂ of the circuit 2121, the multiplexer MUX ₇ outputs the grayscale voltage V _G1 to the input terminal I ₁ of the polarity selection circuit 2122 through the buffer BUF 3 , and the multiplexer MUX ₈ outputs the grayscale voltage _through the buffer BUF ₄ The step voltage V _G3 is sent to the input terminal I ₂ of the polarity selection circuit 2122 . Since the polarity signal S _POL represents logic “1”, the input terminals I ₁ of the polarity selection circuits 2121 and 2122 are respectively coupled to their output terminals O ₁ , and the input terminals I ₂ of the polarity selection circuits 2121 and 2122 are respectively coupled to Connected to its output O ₂ . In this way, the polarity selection circuit 2121 outputs the gray scale voltage V _G2 obtained by converting the digital data DA ₂ according to the positive polarity sub-region Gamma voltage V _PB to the sub-region SR ₁ through the data line DL _X , and the polarity selection circuit 2121 Through the data line DL _(X+1) , the gray scale voltage V _G4 obtained by converting the digital data DA ₁ according to the negative main area gamma voltage V _NA is output to the main area MR ₁ . The polarity selection circuit 2122 outputs the gray scale voltage V _G1 obtained by converting the digital data DA ₂ according to the positive polarity main area Gamma voltage V _PA to the main area MR ₂ through the data line DL _(X+2) , and the polarity is The selection circuit 2122 outputs the gray scale voltage V _G3 obtained by converting the digital data DA ₂ according to the negative polarity sub-region Gamma voltage V _NB to the sub-region SR ₂ through the data line DL _{(X+3 )} . Therefore, in the pixel driving circuit 600, when the inverted polarities of the sub-region SR ₁ , the main region MR ₁ , the main region MR ₂ , and the sub-region SR ₂ are respectively positive, negative, positive, and negative, by representing the logic " The gamma voltage selection signal S _{G_SEL} of 1” and the polarity signal S _POL representing logic “1” can control the selection circuit 211 to input the digital data DA ₁ and DA ₂ to the corresponding digital-to-analog converters to generate gray scales voltages V _G1 -V _G4 , and control the selection circuit 212 to correctly distribute the gray-scale voltages V _G1 -V _{G4 to} the main regions MR ₁ and _{MR 2 and} the sub-regions SR ₁ and SR ₂ .

Please refer to Figure 8. FIG. 8 illustrates the data driving circuit 210 when the inversion polarities of the sub-region SR ₁ , the main region MR ₁ , the main region MR ₂ and the sub-region SR ₂ in the pixel driving circuit 600 are respectively negative, positive, negative and positive. Schematic diagram of the operation. At this time, the gamma voltage selection signal S _{G_SEL} represents logic "1", and the polarity signal S _POL represents logic "0", so the exclusive OR gate 2111 outputs the control signal S _C representing logic "1". When the control signal S _C represents logic “1”, the input terminals I ₂ of the multiplexers MUX ₁ -MUX ₄ are respectively coupled to the output terminals O of the multiplexers MUX ₁ -MUX ₄ . In this way, the multiplexer MUX ₁ outputs the digital data DA ₁ to the digital-analog converter DAC ₁ through the latch DH ₁ and the level shifter LS ₁ , and the multiplexer MUX ₂ passes through the latch DH ₂ and the level shifter LS ₂ outputs digital data DA ₂ to digital-to-analog converter DAC _{2 ,} multiplexer MUX ₃ outputs digital data DA ₁ to digital-to-analog converter DAC 3 through latch DH ₃ and level shifter LS ₃ , and more The router MUX ₄ outputs the digital data DA ₂ to the digital-to _- analog converter DAC 4 through the latch DH ₄ and the level shifter LS ₄ . The digital-to-analog converter DAC ₁ converts the digital data DA ₁ into a gray scale voltage V _G1 according to the positive polarity main area gamma voltage V _PA . The digital-to-analog converter DAC ₂ converts the digital data DA ₂ into a grayscale voltage V _G2 according to the positive polarity sub-region Gamma voltage V _PB . The digital-to-analog converter DAC ₃ converts the digital data DA ₁ into a grayscale voltage V _G3 according to the negative polarity sub-region Gamma voltage V _NB . The digital-to-analog converter DAC ₄ converts the digital data DA ₂ into a gray scale voltage V _G4 according to the negative polarity main area gamma voltage V _NA . At this time, the multiplexers MUX ₅ -MUX ₈ respectively couple the input terminal I ₂ of MUX ₅ -MUX ₈ to the output terminal O of MUX ₅ -MUX ₈ according to the control signal _Sc indicating logic "1". In this way, the multiplexer MUX ₅ outputs the gray scale voltage V _G1 to the input terminal I ₁ of the polarity selection circuit 2121 through the buffer BUF 1 , _and the multiplexer MUX ₆ outputs the gray scale voltage V _G3 to the polarity selection through the buffer BUF ₂ The input terminal I ₂ of the circuit 2121, the multiplexer MUX ₇ outputs the grayscale voltage V _G2 to the input terminal I ₁ of the polarity selection circuit 2122 through the buffer BUF ₃ , and the multiplexer MUX ₈ outputs the gray scale voltage V G2 through the buffer BUF ₄ The step voltage V _G4 is sent to the input terminal I ₂ of the polarity selection circuit 2122 . Since the polarity signal S _POL represents logic “0”, the input terminals I ₁ of the polarity selection circuits 2121 and 2122 are respectively coupled to their output terminals O ₂ , and the input terminals I ₂ of the polarity selection circuits 2121 and 2122 are respectively coupled to connected to its output O ₁ . In this way, the polarity selection circuit 2121 outputs the gray scale voltage V _G3 obtained by converting the digital data DA ₁ according to the negative polarity sub-region Gamma voltage V _NB to the sub-region SR ₁ through the data line DL _X , and the polarity selection circuit 2121 Through the data line DL _(X+1) , the gray scale voltage V _G1 obtained by converting the digital data DA ₁ according to the positive main area gamma voltage V _PA is output to the main area MR ₁ . The polarity selection circuit 2122 outputs the gray scale voltage V _G4 obtained by converting the digital data DA ₂ according to the negative polarity main area gamma voltage V _NA to the main area MR ₂ through the data line DL _(X+2) , and the polarity is The selection circuit 2122 outputs the gray scale voltage V _G2 obtained by converting the digital data DA ₂ according to the positive polarity sub-region Gamma voltage V _PB to the sub-region SR ₂ through the data line DL _{(X+3 )} . Therefore, when the inverted polarities of the sub-region SR ₁ , the main region MR ₁ , the main region MR ₂ , and the sub-region SR ₂ in the pixel driving circuit 600 are negative, positive, negative, and positive, respectively, by representing logic "1 The gamma voltage selection signal S _{G_SEL} of " and the polarity signal S _POL representing logic "0" can control the selection circuit 211 to input the digital data DA ₁ and DA ₂ to the corresponding digital-to-analog converters to generate gray-scale voltages V _G1 -V _G4 , and _{control the selection circuit 212 to correctly distribute the gray-scale voltages V G1 -V G4 to the main} regions MR ₁ and MR ₂ and the sub-regions SR ₁ and SR ₂ .

Similarly, it can be known from the above description that in the pixel driving circuit 600 of the present invention, for the data lines DL _X ˜DL _(X+3) , the data driving circuit 210 only needs four digital-to-analog converters (DAC ₁ ˜DAC ₄ ), the correct gray scale voltage can be provided to the main regions MR ₁ , MR ₂ and the sub-regions SR ₁ , SR ₂ . In other words, when the pixel driving circuit 600 has M data lines, the data driving circuit 210 only needs to have M digital-to-analog converters. Therefore, compared with the pixel driving circuit 100 of the related art, the pixel driving circuit 600 of the present invention can reduce the number of required digital-to-analog converters, thereby saving costs and reducing power consumption.

In addition, the coupling relationship between the pixels and the data lines is not limited to the manner shown in FIG. 2 or FIG. 6 . For example, please refer to FIG. 9 and FIG. 10 . FIG. 9 is a schematic diagram of another embodiment 900 of the pixel driving circuit of the present invention. FIG. 10 is a schematic diagram of a partial structure of the data driving circuit 910 of the pixel driving circuit 900 . Compared with the pixel driving circuit 200, in the pixel driving circuit 900, _the main region MR ₁ is coupled to the data line DL _x through the transistor Q ₁ , and the sub-region SR ₁ is coupled to the data line DL _{(X+ 1)} , the main region MR ₂ is coupled to the data line DL _(X+2) through the transistor Q ₃ , and the sub-region SR ₂ is coupled to the data line DL _(X+3) through the transistor Q ₄ . As shown in FIG. 10 , the difference between the data driving circuit 910 and 210 is that the output terminal O ₁ of the polarity selection circuit 2122 is coupled to the data line DL _(X+3) , and the output terminal O ₂ of the polarity selection circuit 2122 is coupled to the data line DL _(X+2) , so that no matter in the pixel driving circuit 200 or 900, the output terminal O ₁ of the polarity selection circuit 2122 is coupled to the sub-region SR ₂ , and the polarity The output terminals O ₂ of the selection circuit 2122 are both coupled to the main region MR ₂ . Therefore, by means of the method illustrated in FIG. 4 and FIG. 5 , the data driving circuit 910 can distribute correct gray scale voltages V _G1 -V _G4 to the main regions MR ₁ and MR ₂ and the sub-regions SR ₁ and SR ₂ . In other words, in the pixel driving circuit, even if the coupling relationship between the pixel and the data line changes, as long as the structure of the data driving circuit is adjusted accordingly, the data driving circuit can distribute the correct grayscale voltage to each pixel. Main area and sub area.

In summary, the pixel driving circuit provided by the present invention includes a first pixel, a second pixel, and a data driving circuit, each pixel includes a main area and a sub-area, the main area and the sub-area are separated by Gray scale voltages corresponding to each other are stored when a picture is displayed. In the data driving circuit, a first digital data corresponding to the first pixel and a second digital data corresponding to the second pixel are input to the corresponding digital-to-analog converter via a first selection circuit, so as to generating a first gray-scale voltage, a second gray-scale voltage, a third gray-scale voltage and a fourth gray-scale voltage, and providing these gray-scale voltages to the first pixel and the first pixel through a second selection circuit The main area and sub-area in the second pixel. In this way, the number of digital-to-analog converters required by the data driving circuit can be reduced, so as to save the cost of the pixel driving circuit and reduce power consumption.

The above descriptions are only preferred embodiments of the present invention, and all equivalent changes and modifications made according to the claims of the present invention shall fall within the scope of the present invention.

Claims (15)

1. A pixel driving circuit, comprising: A first pixel includes a first main area and a first sub-area, the first main area is coupled to a first data line and a scanning line, and the first sub-area is coupled to a second data line and a scanning line The scan line, the first main area and the first sub-area respectively store gray-scale voltages corresponding to a first digital data; A second pixel includes a second main area and a second sub-area, the second sub-area is coupled to a third data line and the scan line, the second main area is coupled to a fourth data line and the scanning line The scan line, the second main area and the second sub area respectively store gray scale voltages corresponding to a second digital data; and A data driving circuit, including: a first digital-to-analog converter, used to convert the first digital data or the second digital data into a first gray scale voltage according to a positive polarity main region gamma voltage; a second digital-to-analog converter, used to convert the first digital data or the second digital data into a second gray scale voltage according to a positive polarity sub-region gamma voltage; a third digital-to-analog converter, used to convert the first digital data or the second digital data into a third gray scale voltage according to a negative polarity sub-region gamma voltage; A fourth digital-to-analog converter, used to convert the first digital data or the second digital data into a fourth gray scale voltage according to a negative polarity main region gamma voltage; A first selection circuit, used to select the first digital data according to a gamma voltage selection signal and a polarity signal, and input it to the first digital-to-analog converter, the second digital-to-analog converter, and the third digital data an analog converter and two digital-to-analog converters of the fourth digital-to-analog converter, and input the second digital data to the other two digital-to-analog converters; and a second selection circuit, used for transmitting the first gray-scale voltage, the second gray-scale voltage, the third gray-scale voltage and the fourth gray-scale voltage according to the gamma voltage selection signal and the polarity signal The first data line, the second data line, the third data line, and the fourth data line are allocated to the first main area, the first sub area, the second main area and the second sub area. 2. The pixel driving circuit according to claim 1, wherein the data driving circuit further comprises: a first level shifter, coupled between the first selection circuit and the first digital-to-analog converter; a second level shifter, coupled between the first selection circuit and the second digital-to-analog converter; a third level shifter, coupled between the first selection circuit and the third digital-to-analog converter; and A fourth level shifter is coupled between the first selection circuit and the fourth digital-to-analog converter. 3. The pixel driving circuit as claimed in claim 2, wherein the data driving circuit further comprises: a first data latch, coupled between the first selection circuit and the first level shifter; a second data latch coupled between the first selection circuit and the second level shifter; a third data latch coupled between the first selection circuit and the third level shifter; and A fourth data latch is coupled between the first selection circuit and the fourth level shifter. 4. The pixel driving circuit as claimed in claim 2, wherein when the gamma voltage selection signal and the polarity signal both represent a first predetermined logic or both represent a second predetermined logic, the first selection circuit outputs the second digital data to the first DAC and the third DAC, and the first selection circuit outputs the first digital data to the second DAC and the fourth DAC; When the gamma voltage selection signal represents the first predetermined logic and the polarity signal represents the second predetermined logic, the first selection circuit outputs the first digital data to the first DAC and the third digital an analog converter, and the first selection circuit outputs the second digital data to the second digital-to-analog converter and the fourth digital-to-analog converter; when the gamma voltage selection signal represents the second predetermined logic and the polarity When the signal represents the first predetermined logic, the first selection circuit outputs the first digital data to the first DAC and the third DAC, and the first selection circuit outputs the second digital data to The second DAC and the fourth DAC. 5. The pixel driving circuit as claimed in claim 4, wherein the first selection circuit comprises: a mutually exclusive OR gate, used to select a signal and the polarity signal according to the gamma voltage to generate a control signal; A first multiplexer, comprising a first input terminal for receiving the second digital data, a second input terminal for receiving the first digital data, a control terminal for receiving the control signal, and an output terminal , the first multiplexer is used to couple the first input terminal or the second input terminal of the first multiplexer to the output terminal of the first multiplexer according to the control signal; A second multiplexer, comprising a first input terminal for receiving the first digital data, a second input terminal for receiving the second digital data, a control terminal for receiving the control signal, and an output terminal , the second multiplexer is used to couple the first input terminal or the second input terminal of the second multiplexer to the output terminal of the second multiplexer according to the control signal; A third multiplexer, comprising a first input terminal for receiving the second digital data, a second input terminal for receiving the first digital data, a control terminal for receiving the control signal, and an output terminal , the third multiplexer is used to couple the first input terminal or the second input terminal of the third multiplexer to the output terminal of the third multiplexer according to the control signal; and A fourth multiplexer, comprising a first input terminal for receiving the first digital data, a second input terminal for receiving the second digital data, a control terminal for receiving the control signal, and an output terminal , the fourth multiplexer is used to couple the first input terminal or the second input terminal of the fourth multiplexer to the output terminal of the fourth multiplexer according to the control signal. 6. The pixel driving circuit as claimed in claim 5, wherein when the gamma voltage selection signal and the polarity signal both represent the first predetermined logic or both represent the second predetermined logic, the control signal represents the first Predetermined logic; when the gamma voltage selection signal represents the first predetermined logic and the polarity signal represents the second predetermined logic, the control signal represents the second predetermined logic; when the gamma voltage selection signal represents the second predetermined logic When the predetermined logic and the polarity signal represent the first predetermined logic, the control signal represents the second predetermined logic. 7. The pixel driving circuit as claimed in claim 6, wherein when the control signal represents the first predetermined logic, the first input terminal of the first multiplexer is coupled to the output of the first multiplexer end, the first input end of the second multiplexer is coupled to the output end of the second multiplexer, the first input end of the third multiplexer is coupled to the third multiplexer the output terminal, and the first input terminal of the fourth multiplexer is coupled to the output terminal of the fourth multiplexer; when the control signal represents the second predetermined logic, the first multiplexer The second input terminal is coupled to the output terminal of the first multiplexer, the second input terminal of the second multiplexer is coupled to the output terminal of the second multiplexer, and the third multiplexer The second input terminal of the third multiplexer is coupled to the output terminal of the third multiplexer, and the second input terminal of the fourth multiplexer is coupled to the output terminal of the fourth multiplexer. 8. The pixel driving circuit as claimed in claim 6, wherein the second selection circuit comprises: A fifth multiplexer, comprising a first input terminal for receiving the second gray-scale voltage, a second input terminal for receiving the first gray-scale voltage, a control terminal for receiving the control signal, and a an output terminal, the fifth multiplexer is used to couple the first input terminal or the second input terminal of the fifth multiplexer to the output terminal of the fifth multiplexer according to the control signal; A sixth multiplexer, comprising a first input terminal for receiving the fourth grayscale voltage, a second input terminal for receiving the third grayscale voltage, a control terminal for receiving the control signal, and a an output terminal, the sixth multiplexer is used to couple the first input terminal or the second input terminal of the sixth multiplexer to the output terminal of the sixth multiplexer according to the control signal; A seventh multiplexer, comprising a first input terminal for receiving the first grayscale voltage, a second input terminal for receiving the second grayscale voltage, a control terminal for receiving the control signal, and a an output terminal, the seventh multiplexer is used to couple the first input terminal or the second input terminal of the seventh multiplexer to the output terminal of the seventh multiplexer according to the control signal; An eighth multiplexer, comprising a first input terminal for receiving the third gray-scale voltage, a second input terminal for receiving the fourth gray-scale voltage, a control terminal for receiving the control signal, and a an output terminal, the eighth multiplexer is used to couple the first input terminal or the second input terminal of the eighth multiplexer to the output terminal of the eighth multiplexer according to the control signal; A first polarity selection circuit, comprising a first input terminal coupled to the output terminal of the fifth multiplexer, a second input terminal coupled to the output terminal of the sixth multiplexer, a first The output terminal, a second output terminal, and a control terminal are used to receive the polarity signal, and the first polarity selection circuit is used to use the first input terminal and the first polarity selection circuit of the first polarity selection circuit according to the polarity signal one of the second input terminals is coupled to the first output terminal of the first polarity selection circuit, and the other input terminal is coupled to the second output terminal of the first polarity selection circuit; as well as A second polarity selection circuit, comprising a first input terminal coupled to the output terminal of the seventh multiplexer, a second input terminal coupled to the output terminal of the eighth multiplexer, a first The output terminal, a second output terminal, and a control terminal are used to receive the polarity signal, and the second polarity selection circuit is used to use the first input terminal and the first input terminal of the second polarity selection circuit according to the polarity signal One of the second input terminals is coupled to the first output terminal of the second polarity selection circuit, and the other input terminal is coupled to the second output terminal of the second polarity selection circuit. 9. The pixel driving circuit as claimed in claim 8, wherein when the control signal represents the first predetermined logic, the first input terminal of the fifth multiplexer is coupled to the output of the fifth multiplexer end, the first input end of the sixth multiplexer is coupled to the output end of the sixth multiplexer, the first input end of the seventh multiplexer is coupled to the seventh multiplexer The output terminal, the first input terminal of the eighth multiplexer is coupled to the output terminal of the eighth multiplexer; when the control signal indicates the second predetermined logic, the fifth multiplexer The second input terminal is coupled to the output terminal of the fifth multiplexer, the second input terminal of the sixth multiplexer is coupled to the output terminal of the sixth multiplexer, and the seventh multiplexer The second input terminal of the eighth multiplexer is coupled to the output terminal of the seventh multiplexer, and the second input terminal of the eighth multiplexer is coupled to the output terminal of the eighth multiplexer. 10. The pixel driving circuit as claimed in claim 8, wherein when the polarity signal represents the first predetermined logic, the first input terminal of the first polarity selection circuit is coupled to the first polarity selection circuit The second output end of the first polarity selection circuit and the second input end of the first polarity selection circuit are coupled to the first output end of the first polarity selection circuit and the first input end of the second polarity selection circuit coupled to the second output terminal of the second polarity selection circuit, and the second input terminal of the second polarity selection circuit is coupled to the first output terminal of the second polarity selection circuit; when the When the polarity signal represents the second predetermined logic, the first input end of the first polarity selection circuit is coupled to the first output end of the first polarity selection circuit, the first polarity selection circuit The second input end is coupled to the second output end of the first polarity selection circuit, the first input end of the second polarity selection circuit is coupled to the first output end of the second polarity selection circuit , and the second input end of the second polarity selection circuit is coupled to the second output end of the second polarity selection circuit. 11. The pixel driving circuit as claimed in claim 8, wherein the second selection circuit further comprises: A first buffer, coupled between the output terminal of the fifth multiplexer and the first input terminal of the first polarity selection circuit, the first buffer is used to buffer the fifth multiplexer the grayscale voltage output by the output terminal; a second buffer, coupled between the output terminal of the sixth multiplexer and the second input terminal of the first polarity selection circuit, the second buffer is used for buffering the output of the sixth multiplexer the grayscale voltage output by the output terminal; a third buffer, coupled between the output terminal of the seventh multiplexer and the first input terminal of the second polarity selection circuit, the third buffer is used for buffering the output of the seventh multiplexer the grayscale voltage output by the output terminal; and a fourth buffer, coupled between the output terminal of the eighth multiplexer and the second input terminal of the second polarity selection circuit, the fourth buffer is used to buffer the eighth multiplexer The grayscale voltage output by the output terminal. 12. The pixel driving circuit as claimed in claim 8, wherein the first output terminal of the first polarity selection circuit is coupled to the first data line, and the second output terminal of the first polarity selection circuit is coupled to connected to the second data line, the first output end of the second polarity selection circuit is coupled to the third data line, the second output end of the second polarity selection circuit is coupled to the fourth data line Wire. 13. The pixel driving circuit as claimed in claim 12, wherein when the gamma voltage selection signal represents the first predetermined logic and the polarity signal represents the second predetermined logic, the second selection circuit passes through the first predetermined logic. The data line provides the first gray-scale voltage to the first main area, the second data line provides the third gray-scale voltage to the first sub-area, and the third data line provides the second gray-scale voltage voltage to the second sub-region, and provide the fourth gray scale voltage to the second main region through the fourth data line; when the gamma voltage selection signal and the polarity signal both represent the first predetermined logic , the second selection circuit provides the fourth grayscale voltage to the first main region through the first data line, provides the second grayscale voltage to the first subregion through the second data line, and The third data line provides the third grayscale voltage to the second sub-region, and the fourth data line provides the first grayscale voltage to the second main region. 14. The pixel driving circuit as claimed in claim 8, wherein the first output terminal of the first polarity selection circuit is coupled to the second data line, and the second output terminal of the first polarity selection circuit is coupled to connected to the first data line, the first output end of the second polarity selection circuit is coupled to the fourth data line, the second output end of the second polarity selection circuit is coupled to the third data line Wire. 15. The pixel driving circuit as claimed in claim 14, wherein when the gamma voltage selection signal and the polarity signal both represent the second predetermined logic, the second selection circuit provides the first data line through the first data line. Four gray-scale voltages are provided to the first main area, the second gray-scale voltage is provided to the first sub-area through the second data line, and the third gray-scale voltage is provided to the second sub-area through the third data line. sub-region, and provide the first grayscale voltage to the second main region through the fourth data line; when the gamma voltage selection signal represents the second predetermined logic and the polarity signal represents the first predetermined logic, The second selection circuit provides the first gray-scale voltage to the first main region through the first data line, provides the third gray-scale voltage to the first sub-region through the second data line, and provides the first sub-region through the second data line. The third data line provides the second gray-scale voltage to the second sub-area, and the fourth data line provides the fourth gray-scale voltage to the second main area.

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