CN101969331B - Digital frequency selecting method for solving resource consumption - Google Patents
Digital frequency selecting method for solving resource consumption Download PDFInfo
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Abstract
The invention discloses a digital frequency selecting method for solving resource consumption. The method comprises the following steps of: connecting an FPGA digital frequency selection sub-module in a downlink formed by a downlink lower frequency converter, a downlink ADC, a downlink DAC and a downlink upper frequency converter and an uplink formed by an uplink lower frequency converter, an uplink ADC, an uplink DAC and an uplink upper frequency converter; performing digital multi-frequency selection processing on AD output of the downlink and the uplink; returning a processing result as DA input to the downlink and the uplink; performing down-sampling, filtering and up-sampling on digital signals in sequence in an internal processing process of the FPGA digital frequency selection sub-module. By adopting the digital frequency selection mode based on multi clock domains, the number of channels sharing the same group of filters is over the down-sampling rate R under determined down sampling rate R, so the occupied resource required by the digital frequency selection module can be effectively reduced, and the cost for a frequency selector can be reduced.
Description
Technical Field
The invention relates to a frequency selection method in the technical field of communication, in particular to a digital frequency selection method for solving resource consumption.
Background
The frequency selection method commonly used in the present communication system in China is basically analog frequency selection, and the analog frequency selection mainly has the following problems: firstly, the debugging work is difficult, the producibility is poor, and the engineering debugging is inconvenient; secondly, the isolation of the uplink and the downlink is difficult to be made and is easy to self-excite; thirdly, the GSM repeater for simulating frequency selection hardly meets the European standard; fourthly, time slot AGC (a technology for automatically adjusting gain of each time slot) cannot be realized, so that the coverage efficiency of the GSM repeater is greatly reduced.
At present, a published patent document with patent number ZL200920012632.4 introduces a GSM digital multi-frequency-selection repeater and a multi-channel frequency-selection digital signal processing method adopted by the GSM digital multi-frequency-selection repeater, which includes: an uplink, a downlink, a first duplexer module, a second duplexer module, and a control unit; the uplink comprises an uplink low-noise amplification module, an uplink first analog mixing module, an uplink analog-to-digital conversion module, an uplink digital channel frequency selection module, an uplink digital-to-analog conversion module, an uplink second analog mixing module and an uplink power amplification module; the downlink comprises a downlink low-noise amplification module, a downlink first analog mixing module, a downlink analog-to-digital conversion module, a downlink digital channel frequency selection module, a downlink digital-to-analog conversion module, a downlink second analog mixing module and a downlink power amplification module; the ports of the uplink analog-to-digital conversion module, the uplink digital channel frequency selection module, the uplink digital-to-analog conversion module, the downlink analog-to-digital conversion module, the downlink digital channel frequency selection module and the downlink digital-to-analog conversion module are connected with the port of the control unit. The donor antenna receives a downlink signal of a base station, the downlink signal is sent to a downlink low-noise amplification module through a first duplexer module for amplification, the downlink signal is converted into an intermediate frequency signal through a downlink first analog frequency mixing module, the intermediate frequency signal is converted through a downlink analog-to-digital conversion module and then enters a downlink digital channel frequency selection module to complete a frequency selection function, the frequency selection signal is converted through a downlink digital-to-analog conversion module, the frequency selection signal is up-converted into a radio frequency signal through a downlink second analog frequency mixing module, the radio frequency signal is sent to a cable and a distribution system through a second duplexer module after being amplified through a downlink power amplification module, and the retransmission antenna radiates. The retransmission antenna receives the mobile station uplink signal, the uplink signal is sent to the uplink low noise amplification module through the second duplexer module to be amplified, the uplink first analog mixing module down-converts the uplink signal to an analog intermediate frequency signal, the uplink signal is converted through the uplink analog-to-digital conversion module and then enters the uplink digital channel frequency selection module to complete the digital frequency selection function, the frequency selection signal is converted through the uplink digital-to-analog conversion module, the uplink second analog mixing module up-converts the frequency selection signal to a radio frequency signal, the radio frequency signal is amplified through the uplink power amplification module and then sent to the donor antenna through the first duplexer module, the donor antenna sends the radio frequency signal to the base station, and the channel selection and the filtering of the intermediate frequency are realized through software.
In the digital frequency-selective repeater, resource consumption and system delay are two major core indexes. Repeaters generally require that the delay must be less than 10 us. The digital frequency selection based on the multi-sampling rate filter bank technology is mainly determined by the bank delay of the FIR filter. Generally, the more the sampling rate is reduced, the less resources are required for digital frequency selection under the same out-of-band rejection index, but the larger the corresponding delay is. For the digital frequency selector of the repeater, the down-sampling rate R mainly affects the resource consumption from two aspects: firstly, the same out-of-band rejection is achieved by using less FIR taps; second, multiple channels share a set of filters. For the FIR filter determining the amount of taps, the group delay is determined by the sampling rate of the samples, or in other words, by the down-sampling rate R. In the prior art method, at a certain down-sampling rate R, the number of channels sharing a set of filters is at most half of the down-sampling rate R.
Disclosure of Invention
The invention aims to overcome the defects of the prior art and provide a digital frequency selection method for solving the resource consumption, which adopts a digital frequency selection mode based on multiple clock domains, so that the number of channels sharing a group of filters exceeds the down-sampling rate R under the determined down-sampling rate R, is only limited by the highest clock which can be reached by a system, and can meet the technical index requirements of a repeater at lower cost.
The technical scheme adopted by the invention for solving the technical problems is as follows: a digital frequency selection method for solving resource consumption is characterized in that an FPGA digital frequency selection submodule is connected in a downlink formed by a downlink down-converter, a downlink ADC, a downlink DAC and a downlink up-converter and an uplink formed by an uplink down-converter, an uplink ADC, an uplink DAC and an uplink up-converter, AD output of the downlink and the uplink is subjected to digital multi-frequency selection processing, and a processing result is used as DA input to be returned to the downlink and the uplink;
an uplink low-noise module of an uplink outputs a signal to enter an uplink down converter to be converted into an intermediate frequency signal, the intermediate frequency signal enters an uplink ADC to be subjected to band-pass under-sampling, the sampled data enters an FPGA digital frequency selection sub-module to be subjected to digital multi-frequency selection processing, the processed data is used as DA input and sent to an uplink DAC to generate an intermediate frequency signal, and the intermediate frequency signal is converted into a radio frequency signal by the uplink up converter to be output;
the down low noise module of the down link outputs signals to enter a down converter to be converted into intermediate frequency signals, the intermediate frequency signals enter a down ADC to be subjected to band-pass undersampling, the sampled data enter an FPGA digital frequency selection submodule to be subjected to digital multi-frequency selection processing, the processed data are used as DA input and sent to a down DAC to generate intermediate frequency signals, and the intermediate frequency signals are converted into radio frequency signals by a down up converter to be output;
in the internal processing process of the FPGA digital frequency selection submodule, the digital signals are subjected to down-sampling, filtering and up-sampling processing by adopting three clock domains according to the sequence: in the first clock domain, a mixer, a first integrator group and a down sampler are used for sequentially processing signals; in the second clock domain, signals are processed sequentially by a combiner, a first differentiator group, a FIR filter, a second differentiator group and a splitter; in the third clock domain, the signal is processed sequentially with an up-sampler, a second integrator group and a complex mixer.
In the internal processing process of the FPGA digital frequency selection submodule, for the preset channel number K, down-sampling rate R and multiple e, the output of 4K down-samplers is input into a combiner, and the combiner combines 4K signals into one signal;
wherein,
when 4K is equal to R, the combiner and the down sampler adopt the same working clock, wherein the combiner has R inputs;
when 4K is less than R, if the combiner and the down sampler adopt the same working clock, the combiner with R inputs is adopted, wherein R-4K inputs are zero-filled; if the clock of the combiner is e times of the down sampler, a combiner with eR (eR ═ 4K) inputs is adopted, wherein eR-4K inputs are zero-filled;
when 4K is larger than R, the clock of the combiner is e times of the down sampler, so that eR is equal to 4K; at this time, a combiner with eR inputs is employed, where eR-4K inputs are zero-padded.
The FPGA digital frequency selection sub-module is in the internal processing process, wherein: the mixer and the first integrator group work under the same clock; the combiner, the first differentiator group, the FIR filter, the second differentiator group and the splitter work under the same clock; the second integrator bank and the complex mixer operate at the same clock.
In the internal processing process of the FPGA digital frequency selection submodule, the selected combiner, the first differentiator group, the FIR filter, the second differentiator group and the splitter all have a shift register group named Dg, and the pipeline stage number of the shift register group is P and is equal to the input number of the combiner.
In the internal processing process of the FPGA digital frequency selection submodule, the working clock of the second clock domain for filtering is several times of the working clock of the first clock domain for down sampling and the working clock of the third clock domain for up sampling in the selected three clock domains.
The invention relates to a digital frequency selection method for solving resource consumption, wherein AD output data enters an FPGA digital frequency selection sub-module, the FPGA digital frequency selection sub-module carries out digital multi-frequency selection processing, and the processing process comprises the following steps:
for a digital frequency selector with K selection (the number of channels is K), 2K digital frequency mixers are adopted to move a channel to be selected to zero frequency; if the central frequency points of the uplink and downlink channels are consistent after AD undersampling, K digital mixers are adopted, each digital mixer respectively generates two paths of signals I and Q, and the uplink and downlink channels generate 4K paths of signals in total;
each mixer needs two paths of sin and cos signals as carrier frequencies, and the sin and cos signals are generated based on a direct digital frequency synthesis (DDS) technology;
the 4K paths of signals output by the digital mixer are respectively sent to first integrator groups of down-conversion, and each first integrator group of down-conversion consists of a plurality of cascaded integrators;
the output of each first integrator group respectively passes through a down sampler with the rate of reduction R, and the down sampler with the rate of reduction R finishes the operation of outputting one sample value of each R;
inputting signals output by the 4K down samplers into a combiner, and combining the 4K signals into one signal by the combiner; the merging process encounters the following three cases:
(1) when 4K is equal to R, the combiner and the down sampler adopt the same working clock, wherein the combiner has R inputs;
(2) when the ratio of 4K to R is less than R,
if the combiner and the down sampler adopt the same working clock, the combiner with R inputs is adopted, wherein R-4K inputs are zero-filled;
if the clock of the combiner is e times of the down sampler, adopting a combiner with eR (eR ═ 4K) inputs, wherein eR-4K inputs are zero-filled;
(3) when 4K is larger than R, the clock of the combiner is e times of the down sampler, so that eR is equal to 4K; at this time, a combiner with eR inputs is employed, where eR-4K inputs are zero-padded.
The combiner, the first differentiator group, the FIR filter, the second differentiator group and the splitter work under the same clock; the combiner, the first differentiator group, the FIR filter, the second differentiator group and the splitter are all provided with a shift register group named Dg, and the pipeline stage number of the shift register group is P and is equal to the input number of the combiner;
the output signal of the combiner is input into a first differentiator group, and the first differentiator group consists of a plurality of cascaded differentiators;
the output of the first set of differentiators is connected to the input of the FIR filter;
the output of the FIR filter is connected to the input of a second differentiator group, and the second differentiator group consists of a plurality of cascaded differentiators;
the output of the second differentiator group is connected with the input of the splitter;
the splitter decomposes the signal into P paths of outputs, and 4K effective outputs are obtained after screening;
4K effective output signals of the branching unit are respectively input to 4K up-samplers, and R-1 zeros are inserted between every two data by the 4K up-samplers with the rate of R;
the outputs of the 4K upsamplers are connected to the inputs of the second integrator group, respectively;
the outputs of the 4K second integrator groups are respectively connected to the 2K complex mixers, namely, each 2 second integrator groups are connected with one complex mixer;
the complex mixer generates positive and negative outputs, all the positive outputs in the uplink are added, all the negative outputs in the uplink are added, all the positive outputs in the downlink are added, and all the negative outputs in the downlink are added;
the 4 output signals generated by the 4 adders are supplied to the DA converter.
The invention has the advantages that because a digital frequency selection mode based on multiple clock domains is adopted, the number of channels sharing a group of filters exceeds the down-sampling rate R under the determined down-sampling rate R, and is only limited by the highest clock which can be reached by the system, thereby effectively solving the problems of poor productivity and low coverage rate in the prior art.
Compared with the prior art, the invention has the following advantages: firstly, the number of channels can be increased in multiples by sharing a group of filters, and resource consumption can be effectively reduced; secondly, the channel selection and filtering of the intermediate frequency are realized by a working clock, and the cost advantage is obvious; thirdly, the product operation stability and reliability are high, and the later maintenance is convenient.
The invention is further explained in detail with the accompanying drawings and the embodiments; a digital frequency selection method for solving resource consumption of the present invention is not limited to the embodiments.
Drawings
FIG. 1 is a schematic diagram of a digital frequency selector selected for use in implementing the method of the present invention;
FIG. 2 is a schematic diagram of an FPGA digital frequency-selecting sub-module selected for implementing the method of the present invention;
FIG. 3 is a schematic diagram of a mixer in an FPGA digital frequency-selective sub-module selected for implementing the method of the present invention;
FIG. 4 is a schematic diagram of a direct digital frequency synthesizer (DDS) in an FPGA digital frequency-selective sub-module selected for implementing the method of the present invention;
FIG. 5 is a schematic diagram of an integrator group in an FPGA digital frequency-selective sub-module selected for implementing the method of the present invention;
FIG. 6 is a schematic diagram of an integrator group in an FPGA digital frequency-selective sub-module selected for implementing the method of the present invention;
FIG. 7 is a diagram of a Dg register bank in an FPGA digital frequency-selective submodule selected for implementing the method of the present invention;
FIG. 8 is a schematic diagram of a set of differentiators within an FPGA digital frequency selective sub-module selected for implementing the method of the present invention;
FIG. 9 is a schematic diagram of a differentiator bank within an FPGA digital frequency selective sub-module selected for implementing the method of the present invention;
FIG. 10 is a schematic diagram of an FIR filter in an FPGA digital frequency-selective sub-module selected for implementing the method of the present invention;
FIG. 11 is a schematic diagram of a down sampler in an FPGA digital frequency-selective sub-module selected for implementing the method of the present invention;
FIG. 12 is a schematic diagram of an upsampler in an FPGA digital frequency selective sub-module selected for implementing the method of the present invention;
fig. 13 is a schematic diagram of a complex mixer in an FPGA digital frequency-selecting sub-module selected to implement the method of the present invention.
Detailed Description
In an embodiment, referring to the drawings, a digital frequency selecting method for solving resource consumption according to the present invention is implemented by using a digital frequency selector as shown in fig. 1, where the digital frequency selector includes a downlink down-converter 11, a downlink ADC12, a downlink DAC13, a downlink up-converter 14, a downlink local oscillator 15, an FPGA digital frequency selecting submodule 3, an uplink down-converter 21, an uplink ADC22, an uplink DAC23, an uplink up-converter 24, an uplink local oscillator 25, a power management submodule 10, a monitoring submodule 20, and a clock management submodule 30.
The input of the downlink down converter 11 is connected to the low noise module of the downlink, the output of the downlink down converter 11 is connected to the input of the downlink ADC12, the output of the downlink ADC12 is connected to the input of the FPGA digital frequency-selecting submodule 3, the output of the FPGA digital frequency-selecting submodule 3 is connected to the input of the downlink DAC13, the output of the downlink DAC13 is connected to the input of the downlink up converter 14, the output of the downlink up converter 14 is connected to the power amplifier module of the downlink, and the downlink local oscillator 15 is respectively connected to the downlink down converter 11 and the downlink up converter 14; the input of the up-converter 21 is connected to the low-noise module of the uplink, the output of the up-converter 21 is connected to the input of the up-converter 22, the output of the up-converter 22 is connected to the input of the FPGA digital frequency-selecting submodule 3, the output of the FPGA digital frequency-selecting submodule 3 is connected to the input of the up-DAC 23, the output of the up-DAC 23 is connected to the input of the up-converter 24, the output of the up-converter 24 is connected to the power amplifier module of the uplink, and the up local oscillator 25 is respectively connected to the up-converter 21 and the up-converter 24; the power management submodule 10 is connected in the uplink and the downlink to provide power for the normal operation of each module; the monitoring submodule 20 is connected in the uplink and the downlink to carry out initialization setting on each module and monitor the working state of the system; the clock management submodule 30 is respectively connected with the FPGA digital frequency selection submodule 3, the downlink ADC12, the downlink DAC13, the uplink ADC22 and the uplink DAC23, and the clock management submodule 30 outputs clock signals to the FPGA digital frequency selection submodule 3, the downlink ADC12, the downlink DAC13, the uplink ADC22 and the uplink DAC 23.
The digital frequency selection method for solving the resource consumption of the invention adopts an FPGA digital frequency selection submodule 3 as shown in FIG. 2 to realize digital multi-frequency selection processing, wherein the FPGA digital frequency selection submodule 3 comprises 2K (K channels) mixers 301, 4K first integrator groups 302, 4K down-samplers 303, a combiner 304, a first differentiator group 305, an FIR filter 306, a second differentiator group 307, a splitter 308, 4K up-samplers 309, 4K second integrator groups 310, 2K complex mixers 311 and four adders 312.
The AD outputs of the uplink and downlink links are connected to 2K mixers 301, respectively; the outputs of the 2K mixers 301 are respectively connected to the inputs of the 4K first integrator groups 302, i.e. the outputs of the 1 mixer 301 are divided into two first integrator groups 302; the outputs of the 4K first integrator groups 302 are respectively and correspondingly connected with the 4K down samplers 303, that is, the output of each first integrator group 302 is connected with one down sampler 303; the outputs of the 4K down-samplers 303 are connected to a combiner 304; the output of the combiner 304 is connected to the input of the first differentiator group 305; the output of the differentiator bank 305 is connected to the input of the FIR filter 306; the output of the FIR filter 306 is connected to the input of the second differentiator group 307; the output of the second differentiator group 307 is connected to the input of the splitter 308; the output of the splitter 308 is connected to the inputs of 4K up-samplers 309, respectively; the outputs of the 4K up-samplers 309 are connected to the inputs of the 4K second integrator groups 310, respectively, i.e., the output of each up-sampler 309 is connected to one second integrator group 310; the outputs of the 4K second integrator groups 310 are respectively connected to the inputs of the 2K complex mixers 311, that is, the outputs of every two second integrator groups 310 are connected to one complex mixer 311; the outputs of the 2K complex mixers 311 are connected to the inputs of four adders 312, respectively, one adder 312 adding all the positive outputs of the upper row, another adder 312 adding all the negative outputs of the upper row, yet another adder 312 adding all the positive outputs of the lower row, and yet another adder 312 adding all the negative outputs of the lower row.
The invention relates to a digital frequency selection method for solving resource consumption, which is characterized in that an FPGA digital frequency selection submodule 3 is connected in a downlink formed by a downlink down converter 11, a downlink ADC12, a downlink DAC13 and a downlink up converter 14 and an uplink formed by an uplink down converter 21, an uplink ADC22, an uplink DAC23 and an uplink up converter 24, the AD output of the downlink and the uplink is subjected to digital multi-frequency selection processing, and the processing result is used as DA input to be returned to the downlink and the uplink;
an uplink low-noise module output signal of an uplink enters an uplink down converter 11 to be converted into an intermediate frequency signal, the intermediate frequency signal enters an uplink ADC12 to be subjected to band-pass undersampling, sampled data enters an FPGA digital frequency selection submodule 3 to be subjected to digital multi-frequency selection processing, the processed data is used as DA input and sent to an uplink DAC13 to generate an intermediate frequency signal, and the intermediate frequency signal is converted into a radio frequency signal through an uplink up converter 14 and then is output;
the downlink low noise module output signal of the downlink enters the downlink down converter 21 to be converted into an intermediate frequency signal, the intermediate frequency signal enters the downlink ADC22 to be subjected to band-pass undersampling, the sampled data enters the FPGA digital frequency selection sub-module 3 to be subjected to digital multi-frequency selection processing, the processed data is used as DA input and sent to the downlink DAC23 to generate an intermediate frequency signal, and the intermediate frequency signal is converted into a radio frequency signal by the downlink up converter 24 and then output;
in the internal processing process of the FPGA digital frequency selection submodule 3, the digital signals are processed by adopting three clock domains to perform down sampling, filtering and up sampling according to the sequence: in the first clock domain, the signals are sequentially processed by a mixer 301, a first integrator group 302 and a down-sampler 303; in the second clock domain, the signal is processed sequentially with combiner 304, first differentiator bank 305, FIR filter 306, second differentiator bank 307 and splitter 308; in the third clock domain, the signal is processed sequentially with an up-sampler 309, a second integrator group 310 and a complex mixer 311.
In the internal processing process of the FPGA digital frequency-selecting submodule 3, for the preset number K of channels, down-sampling rate R and multiple e, the outputs of 4K down-samplers are input into the combiner 304, and the combiner 304 combines 4K signals into one signal;
wherein,
when 4K is equal to R, the combiner and the down sampler adopt the same working clock, wherein the combiner has R inputs;
when 4K is less than R, if the combiner and the down sampler adopt the same working clock, the combiner with R inputs is adopted, wherein R-4K inputs are zero-filled; if the clock of the combiner is e times of the down sampler, a combiner with eR (eR ═ 4K) inputs is adopted, wherein eR-4K inputs are zero-filled;
when 4K is larger than R, the clock of the combiner is e times of the down sampler, so that eR is equal to 4K; at this time, a combiner with eR inputs is employed, where eR-4K inputs are zero-padded.
In the internal processing process of the FPGA digital frequency selection submodule 3, wherein: the mixer 301 and the first integrator group 302 operate at the same clock; the combiner 304, the first differentiator group 305, the FIR filter 306, the second differentiator group 307 and the splitter 308 operate at the same clock; the second integrator bank 310 and the complex mixer 311 operate at the same clock.
In the internal processing process of the FPGA digital frequency-selecting submodule 3, the selected combiner 304, the first differentiator group 305, the FIR filter 306, the second differentiator group 307 and the splitter 308 all have a shift register group named Dg, and the pipeline stage number of the shift register group is P and is equal to the input number of the combiner.
Optionally, in the internal processing process of the FPGA digital frequency selection submodule 3, the operating clock of the second clock domain for filtering may be several times that of the operating clock of the first clock domain for down-sampling and the operating clock of the third clock domain for up-sampling, among the selected three clock domains.
The invention relates to a digital frequency selection method for solving resource consumption, data output by AD enters an FPGA digital frequency selection sub-module 3, the FPGA digital frequency selection sub-module 3 carries out digital multi-frequency selection processing, and the processing process comprises the following steps:
for a digital frequency selector with K selection (the number of channels is K), 2K digital mixers 301 are adopted to move the channels to be selected to zero frequency; if the central frequency points of the uplink and downlink channels are consistent after AD undersampling, K digital mixers 301 are adopted, each digital mixer 301 generates two paths of signals I and Q respectively, and the uplink and downlink channels generate 4K paths of signals in total;
each mixer 301 needs two channels of sin and cos signals as carrier frequencies, respectively, and the generation of the sin and cos signals is based on a direct digital frequency synthesis (DDS);
the 4K paths of signals output by the digital mixer 301 are respectively sent to first integrator groups 302 for down-conversion, and each first integrator group 302 for down-conversion is composed of a plurality of cascaded integrators;
the output of each first integrator group 302 passes through a down sampler 303 with a rate of reduction R, and the down sampler 303 with the rate of reduction R completes the operation of outputting one sample value of each R;
inputting the signals output by the 4K down-samplers 303 to a combiner 304, and combining the 4K signals into one signal by the combiner 304; the merging process encounters the following three cases:
(1) when 4K is equal to R, the combiner and the down sampler adopt the same working clock, wherein the combiner has R inputs;
(2) when the ratio of 4K to R is less than R,
if the combiner and the down sampler adopt the same working clock, the combiner with R inputs is adopted, wherein R-4K inputs are zero-filled;
if the clock of the combiner is e times of the down sampler, adopting a combiner with eR (eR ═ 4K) inputs, wherein eR-4K inputs are zero-filled;
(3) when 4K is larger than R, the clock of the combiner is e times of the down sampler, so that eR is equal to 4K; at this time, a combiner with eR inputs is employed, where eR-4K inputs are zero-padded.
Combiner 304, first differentiator bank 305, FIR filter 306, second differentiator bank 307, and splitter 308 operate at the same clock; the combiner 304, the first differentiator group 305, the FIR filter 306, the second differentiator group 307 and the splitter 308 all have a shift register group named Dg, the pipeline stage number of the shift register group is P, and is equal to the input number of the combiner;
the output signal of the combiner 304 is input to a first differentiator group 305, and the first differentiator group 305 is composed of a plurality of cascaded differentiators;
the output of the first differentiator bank 305 is connected to the input of the FIR filter 306;
the output of the FIR filter 306 is connected to the input of a second differentiator group 307, the second differentiator group 307 is composed of several cascaded differentiators;
the output of the second differentiator group 307 is connected to the input of the splitter 308;
the splitter 308 splits the signal into P outputs, and 4K effective outputs are obtained after screening;
the 4K valid output signals of the splitter 308 are respectively input to 4K up-samplers 309, and R-1 zeros are inserted between every two data by the 4K up-samplers 309 with the up-rate R;
the outputs of the 4K upsamplers 309 are connected to the inputs of a second integrator group 310, respectively;
the outputs of the 4K second integrator groups 310 are connected to 2K complex mixers 311, respectively, i.e. one complex mixer is connected to each 2 second integrator groups;
the complex mixer 311 generates positive and negative outputs, all the positive outputs of the uplink are added, all the negative outputs of the uplink are added, all the positive outputs of the downlink are added, and all the negative outputs of the downlink are added;
the 4 output signals generated by the 4 adders 312 are sent to the DA converter.
The digital frequency selection method provided by the invention is illustrated by taking a 16-selected GSM digital frequency selector as an example, and in order to meet the delay requirement, the sampling rate of an AD converter is 81.92Mbps, the down-sampling rate R is 32, and the number of taps of an FIR filter is 23; 4K > R since K is 16, 4K is 64; at this time, the working clocks of the combiner, the first differentiator group, the FIR filter, the second differentiator group and the splitter are 163.84, that is, the working clock of the clock domain 2 is 2 times of the working clock of the clock domain 1; because eR is 4K, 64 paths of signals generated by 16 selections only need to share one combiner, the first differentiator group, the FIR filter, the second differentiator group and the splitter, and thus another combiner, the first differentiator group, the FIR filter, the second differentiator group and the splitter which are needed in the prior art are saved; therefore, under the condition of keeping the determined time delay unchanged, the method can effectively reduce the resource consumption.
The above embodiments are only used to further illustrate a digital frequency selection method for solving the resource consumption of the present invention, but the present invention is not limited to the embodiments, and any simple modification, equivalent change and modification made to the above embodiments according to the technical spirit of the present invention fall within the protection scope of the technical solution of the present invention.
Claims (6)
1. A digital frequency selection method for solving resource consumption is characterized in that: connecting an FPGA digital frequency selection sub-module in a downlink formed by a downlink down-converter, a downlink ADC, a downlink DAC and a downlink up-converter and an uplink formed by an uplink down-converter, an uplink ADC, an uplink DAC and an uplink up-converter, performing digital multi-frequency selection processing on AD output of the downlink and the uplink, and returning a processing result to the downlink and the uplink as DA input;
an uplink low-noise module of an uplink outputs a signal to enter an uplink down converter to be converted into an intermediate frequency signal, the intermediate frequency signal enters an uplink ADC to be subjected to band-pass under-sampling, the sampled data enters an FPGA digital frequency selection sub-module to be subjected to digital multi-frequency selection processing, the processed data is used as DA input and sent to an uplink DAC to generate an intermediate frequency signal, and the intermediate frequency signal is converted into a radio frequency signal by the uplink up converter to be output;
the down low noise module of the down link outputs signals to enter a down converter to be converted into intermediate frequency signals, the intermediate frequency signals enter a down ADC to be subjected to band-pass undersampling, the sampled data enter an FPGA digital frequency selection submodule to be subjected to digital multi-frequency selection processing, the processed data are used as DA input and sent to a down DAC to generate intermediate frequency signals, and the intermediate frequency signals are converted into radio frequency signals by a down up converter to be output;
in the internal processing process of the FPGA digital frequency selection submodule, the digital signals are subjected to down-sampling, filtering and up-sampling processing by adopting three clock domains according to the sequence: in the first clock domain, a mixer, a first integrator group and a down sampler are used for sequentially processing signals; in the second clock domain, signals are processed sequentially by a combiner, a first differentiator group, a FIR filter, a second differentiator group and a splitter; in the third clock domain, the signal is processed sequentially with an up-sampler, a second integrator group and a complex mixer.
2. The digital frequency selection method of claim 1, wherein: in the internal processing process of the FPGA digital frequency selection submodule, for the preset channel number K, down-sampling rate R and multiple e, the output of 4K down-samplers is input into a combiner, and the combiner combines 4K signals into one signal;
wherein,
when 4K = R, the combiner and the down sampler adopt the same working clock, wherein the combiner has R inputs;
when 4K is less than R, if the combiner and the down sampler adopt the same working clock, the combiner with R inputs is adopted, wherein R-4K inputs are zero-filled; if the clock of the combiner is e times of the down sampler, adopting a combiner with eR inputs, wherein eR > =4K, and eR-4K inputs are filled with zero;
when 4K > R, let the clock of the combiner be e times of the down sampler, so that eR > = 4K; at this time, a combiner with eR inputs is employed, where eR-4K inputs are zero-padded.
3. The digital frequency selection method of claim 1, wherein: the FPGA digital frequency selection sub-module is in the internal processing process, wherein: the mixer and the first integrator group work under the same clock; the combiner, the first differentiator group, the FIR filter, the second differentiator group and the splitter work under the same clock; the second integrator bank and the complex mixer operate at the same clock.
4. A digital frequency selection method according to claim 1, 2 or 3, characterized in that: in the internal processing process of the FPGA digital frequency selection submodule, the selected combiner, the first differentiator group, the FIR filter, the second differentiator group and the splitter all have a shift register group named Dg, and the pipeline stage number of the shift register group is P and is equal to the input number of the combiner.
5. A digital frequency selection method according to claim 1 or 3, characterized in that: in the internal processing process of the FPGA digital frequency selection submodule, the working clock of the second clock domain for filtering is several times of the working clock of the first clock domain for down sampling and the working clock of the third clock domain for up sampling in the selected three clock domains.
6. The digital frequency selection method of claim 4, wherein: in the internal processing process of the FPGA digital frequency selection submodule, the working clock of the second clock domain for filtering is several times of the working clock of the first clock domain for down sampling and the working clock of the third clock domain for up sampling in the selected three clock domains.
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