CN101969057B - Circuit substrate - Google Patents

Abstract

The invention relates to a circuit substrate, which comprises an outer circuit layer, an inner circuit layer, a dielectric layer, a first conductive hole and a second conductive hole. The outer circuit layer comprises a first signal circuit, a first test circuit and a test contact communicated with the first test circuit. The inner circuit layer comprises a second signal circuit, a second test circuit and a first connecting circuit connected between the second signal circuit and the second test circuit. The dielectric layer is configured between the outer circuit layer and the inner circuit layer. The first conductive hole is located in the dielectric layer, wherein the first conductive hole is used for conducting the first test circuit and the second test circuit. The second conductive hole is located in the dielectric layer, wherein the second conductive hole is used for conducting the first signal line and the second signal line. The circuit substrate provided by the invention can be used for carrying out open circuit/short circuit tests. In addition, the routing pad of the first signal circuit can be conducted with the testing contact point positioned on the outer circuit layer, so that the welding non-stick test can be carried out.

Description

Circuit board

technical field

The invention relates to a circuit substrate, in particular to a circuit substrate for performing an open/short test and a non-stick test.

Background technique

At present, in semiconductor packaging technology, circuit substrate is one of the frequently used assembly components. The circuit substrate is mainly composed of multiple patterned conductive layers and multiple dielectric layers alternately stacked, and the two circuit layers can be electrically connected through conductive vias.

When the circuit board is used in the wire bonding process of chip packaging, in order to improve the yield rate of the wire bonding process of the circuit board, it is necessary to conduct a non-stick test on the circuit board According to the situation to adjust the process parameters. In addition, as the circuit density of the circuit substrate increases continuously, it becomes very difficult to inspect the circuit pattern on the circuit substrate by means of image observation. Therefore, in the process of manufacturing high-density circuit substrates, it is necessary to conduct an open circuit/short circuit test on the circuit substrates in an electrical manner to ensure the yield.

In order to perform an open circuit/short circuit test on the circuit substrate, the outer circuit layer of the circuit substrate must be removed to connect the plating line to the pad and the test circuit, wherein the purpose of the electroplating line is to form an anti- oxide layer. However, solder nonstick testing is not possible due to the removal of these plating lines.

Contents of the invention

The purpose of the present invention is to provide a circuit substrate, which can perform open circuit/short circuit test and solder non-stick test.

The invention provides a circuit substrate, which includes an outer circuit layer, an inner circuit layer, a dielectric layer, a first conductive hole and a second conductive hole. The outer circuit layer includes a first signal circuit, a first test circuit and a test contact connected to the first test circuit. The first signal line includes a bonding pad surrounded by the first test line. The inner circuit layer includes a second signal circuit, a second test circuit and a first connection circuit connected between the second signal circuit and the second test circuit. The dielectric layer is disposed between the outer circuit layer and the inner circuit layer. The first conductive hole is located in the dielectric layer, wherein the first conductive hole is used for conducting the first test circuit and the second test circuit. The second conductive hole is located in the dielectric layer, wherein the second conductive hole is used for connecting the first signal line and the second signal line.

In an embodiment of the present invention, the above-mentioned test contacts pass through the first test line, the first conductive hole, the second test line, the first connection line, the second signal line and the second conductive hole in sequence, and conduct to the first test line. a signal line.

In an embodiment of the present invention, the first signal line further includes a first pad and a connection line. The first pad is connected to the second conductive hole. The connection line is connected between the bonding pad and the first pad.

In an embodiment of the present invention, the above-mentioned second signal line includes a second pad surrounded by the second test line, wherein the first connection line is connected between the second pad and the second test line.

In an embodiment of the present invention, the circuit substrate further includes a solder mask layer disposed on the outer circuit layer and exposing part of the outer circuit layer.

In an embodiment of the present invention, the outer circuit layer further includes a third pad connected to the first conductive hole and the first test circuit.

In an embodiment of the present invention, the inner circuit layer further includes a fourth pad connected to the first conductive hole and the second test circuit.

In the circuit substrate of the present invention, none of the first signal lines on the outer circuit layer is connected to the first test line, that is, there is no traditional plating line, so the open circuit/short circuit test can be performed. In addition, the bonding pads of the first signal circuit can be conducted with the test contacts on the outer circuit layer through the test circuit on the inner circuit layer, so that the solder non-stick test can be performed.

In order to make the above-mentioned features and advantages of the present invention more comprehensible, an embodiment is exemplified below and described in detail in conjunction with the accompanying drawings.

Description of drawings

1 is a schematic top view of an outer circuit layer of a circuit substrate according to an embodiment of the present invention;

2 is a schematic top view of an inner circuit layer of a circuit substrate according to an embodiment of the present invention;

Fig. 3 is a partial structural cross-sectional view of the circuit substrate along the line AA' of Fig. 1 according to the embodiment of the present invention;

Fig. 4 is a partial structural cross-sectional view of the circuit substrate of the embodiment of the present invention along the BB' line of Fig. 2;

Fig. 5 is a cross-sectional view of a part of the structure of the circuit substrate along line CC' in Fig. 1 according to the embodiment of the present invention.

Description of main component symbols:

110: outer line layer; 112: first signal line;

112a: wire bonding pad; 112b: first pad;

112c: the second connection line; 114: the first test line;

116: test contact; 118: third pad;

120: inner line layer; 122: second signal line;

122a: the second pad; 124: the second test line;

126: the first connection line; 128: the fourth pad;

130: dielectric layer; 140: first conductive hole;

150: second conductive hole; 160: solder mask layer.

Detailed ways

Fig. 1 is a schematic top view of the outer circuit layer of the circuit substrate according to an embodiment of the present invention, Fig. 2 is a schematic top view of the inner circuit layer of the circuit substrate according to the embodiment of the present invention, and Fig. 3 is a schematic top view of the circuit substrate according to the embodiment of the present invention along Fig. 1 4 is a partial structural sectional view of the circuit substrate of the embodiment of the present invention along the BB' line of FIG. 2 , and FIG. 5 is a part of the circuit substrate of the embodiment of the present invention along the CC' line of FIG. 1 Sectional view of the structure. 1, FIG. 2, FIG. 3, FIG. 4 and FIG. 5, the circuit substrate of this embodiment includes an outer circuit layer 110, an inner circuit layer 120, a dielectric layer 130, a first conductive hole 140 and a first Two conductive holes 150 .

The outer circuit layer 110 includes a first signal circuit 112 , a first test circuit 114 and a test contact 116 connected to the first test circuit 114 . The inner circuit layer 120 includes a second signal circuit 122 , a second test circuit 124 and a first connection circuit 126 connected between the second signal circuit 122 and the second test circuit 124 .

The dielectric layer 130 (shown in FIG. 3 ) is disposed between the outer circuit layer 110 and the inner circuit layer 120 . The first conductive hole 140 is located in the dielectric layer 130 for conducting the first test line 114 and the second test line 124 . The second conductive hole 150 is located in the dielectric layer 130 for conducting the first signal line 112 and the second signal line 122 .

1 and 3, in this embodiment, the first signal line 112 includes a wire bonding pad 112a, a first pad 112b connected to the second conductive hole 150, and a wire bonding pad 112a connected to The second connection line 112c between the first pads 112b, wherein the first test line 114 surrounds the bonding pad 112a, the first pad 112b and the second connection line 112c. It is worth noting that the wire bonding pad 112a is not connected to the first test circuit 114 on the outer circuit layer 110 , that is, there is no conventional plating wire, and the open/short circuit test can be performed on the wire bonding pad 112a.

2 and 4, the second signal line 122 includes a second pad 122a, wherein the second test line 124 surrounds the second pad 122a, and the first connection line 126 is connected to the second pad 122a and the second test pad 122a. between line 124.

Referring to FIG. 1 , FIG. 2 and FIG. 5 , the outer circuit layer 110 further includes a third pad 118 connected to the first conductive hole 140 and the first test circuit 114 . The inner circuit layer 120 further includes a fourth pad 128 connected to the first conductive hole 140 and the second test circuit 124 .

In this embodiment, the bonding pad 112a can sequentially pass through the second connection line 112c, the first pad 112b, the second conductive hole 150, the second pad 122a, the first connection line 126, and the second test line 124. , the fourth pad 128 , the first conductive hole 140 , the third pad 118 , and the first test line 114 are connected to the test contact 116 , so that the solder non-stick test can be performed.

As shown in FIG. 3 , the circuit substrate of this embodiment further includes a solder mask layer 160 disposed on the outer circuit layer 110 and exposing part of the outer circuit layer 110 .

To sum up, in the circuit substrate of the present invention, none of the first signal lines on the outer circuit layer is connected to the first test line, that is, there is no traditional plating line, so open circuit/short circuit testing can be performed. In addition, the bonding pad of the first signal circuit can be conducted with the test contact on the outer circuit layer through the test circuit of the inner circuit layer, so that the solder non-stick test can be performed. That is, after the circuit substrate of the present invention is fabricated and subjected to an open circuit/short circuit test, a solder non-stick test can be directly performed in a subsequent process to improve process efficiency and productivity.

Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and not to limit them. Although the present invention has been described in detail with reference to the preferred embodiments, those of ordinary skill in the art should understand that: it still Modifications or equivalent replacements can be made to the technical solutions of the present invention, and these modifications or equivalent replacements cannot make the modified technical solutions deviate from the spirit and scope of the technical solutions of the present invention.

Claims (7)

1. A circuit substrate, characterized in that, comprising: An outer line layer, including: a first test circuit; A first signal line, comprising: a bonding pad surrounded by the first test line; a test contact, conducting with the first test line; An inner line layer, including: a second signal line; a second test line; a first connection line connected between the second signal line and the second test line; a dielectric layer disposed between the outer circuit layer and the inner circuit layer; a first conductive hole, located in the dielectric layer, for conducting the first test line and the second test line; and a second conductive hole, located in the dielectric layer, for conducting the first signal line and the second signal line, Wherein the first signal line is not connected to the first test line on the outer line layer. 2. The circuit substrate according to claim 1, wherein the test contact sequentially passes through the first test line, the first conductive hole, the second test line, and the first connection circuit, the second signal circuit and the second conductive hole, and conduct to the first signal circuit. 3. The circuit substrate according to claim 1, wherein the first signal line further comprises: a first pad connected to the second conductive hole; and A connection line connected between the bonding pad and the first pad. 4. The circuit substrate according to claim 1, wherein the second signal circuit comprises: A second pad is surrounded by the second test line, wherein the first connection line is connected between the second pad and the second test line. 5. The circuit substrate according to claim 1, wherein the outer circuit layer further comprises: A third pad, connected to the first conductive hole and the first test line. 6. The circuit substrate according to claim 1, wherein the inner circuit layer further comprises: A fourth pad, connected to the first conductive hole and the second test line. 7. The circuit substrate according to claim 1, further comprising: A solder mask layer is configured on the outer circuit layer and exposes part of the outer circuit layer.

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