CN101943938B - Power supply control device and system using same - Google Patents

Abstract

The invention provides a power supply control device and a system using the same. The power control device is used for controlling a host to safely enter a working mode from a power saving mode, wherein the host sends a power switching signal when the power saving mode is about to enter the working mode. The power control device comprises a voltage stabilizer and a control load. The voltage stabilizer is used for receiving an input voltage and providing an output voltage to the host machine through an output end; the control load is used for drawing a current from the output end of the voltage stabilizer when receiving the power supply switching signal, and sending a starting signal to the host machine after a set time so as to inform the host machine to enter the working mode.

Description

Power control device and system using the power control device

technical field

The present invention relates to a power control device, and more particularly to a power control device operating in multiple voltage modes.

Background technique

As the semiconductor process enters the sub-micron era, various electronic devices generally lower their operating voltages in order to reduce power consumption. As a result, the power supply voltages received by the electronic devices are often different and much higher than their required operating voltages. At this time, it is common practice to arrange a device such as a voltage regulator or a DC-to-DC converter between the power supply and the electronic device to coordinate the power supply and the electronic device. different voltages.

FIG. 1 is a schematic diagram of a low dropout linear regulator in the prior art. A low-dropout linear regulator (LDO for short) is a type of voltage regulator. As shown in FIG. 1 , the LDO 100 is used to receive an input voltage V _in from a power supply (not shown in the figure) and supply an output voltage V _out to an electronic device (not shown). Wherein, the sampling circuit 110 is composed of resistors R ₁ and R ₂ for obtaining a sampling voltage V _sp from the output voltage V _out , and feeding the sampling voltage V _sp back to the comparison amplifier 120 for comparison with a reference voltage V _REF , the difference between the two is amplified by the comparison amplifier 120 to control the voltage drop of the power amplifier 130 to stabilize the output voltage V _out .

It is worth noting that some electronic products do not operate with only one fixed power source, but switch between multiple power modes, during which the power variation may be quite large. Taking a host computer as an example, its common power modes include: working mode and power saving mode (even further subdivided into hibernation mode and sleep mode). FIG. 2 is a schematic diagram of a host computer switching between different power modes. When the command IN ₁ starts the high-voltage power amplifier 21, the host computer operates at a higher current (for example, 100mA) in the working mode; and when the command IN ₂ starts the low-voltage power amplifier 22, the host computer switches to a lower current (for example, 0.1 μA) operate in power saving mode to save power. There are often different operating currents between the two modes. In the case of the above-mentioned LDO100, when the output load changes drastically, the output voltage V _out has a huge voltage difference due to the slow switching speed of the output control components including the power amplifier 130. This will easily damage the LDO100 and cause the host to be abnormal. Although the traditional method can be used to solve this problem, a large capacitor is placed on the output of the LDO100 to reduce this effect. However, not all electronic products allow a large capacitor outside the IC. If the large capacitor is built into the IC It will also greatly increase the manufacturing cost.

Contents of the invention

The present invention provides a power control device for controlling a host to safely enter a working mode from a power saving mode, wherein the host sends a power switching signal when the power saving mode is about to enter the working mode. The power control device includes a voltage regulator and a control load. Wherein the voltage regulator is used to receive an input voltage, and an output terminal is used to provide an output voltage to the host; and the control load is used to generate from the voltage regulator when receiving the power switching signal The output end draws a current, and sends a start signal to the host after a predetermined time to notify the host to enter the working mode.

The present invention also provides a system that can safely enter a working mode from a power saving mode. The system includes a host, a voltage regulator, a control circuit and a dummy load. Wherein the host sends a power switching signal when the power-saving mode is about to enter the working mode; the voltage regulator is used to receive an input voltage and provide an output voltage to the host through an output terminal; The control circuit is used to send a control signal when receiving the power switching signal, and send the start signal to the host after a predetermined time to notify the host to enter the working mode; and the dummy load , coupled between the control circuit and the voltage regulator, used to receive control from the control signal to increase the current output by the voltage regulator to a certain value within the predetermined time.

The present invention provides a power control device and a system using the power control device. When the host 320 returns to the working mode from the power saving mode and the current increases sharply, it can still provide power to the host stably.

Description of drawings

Fig. 1 is the schematic diagram of a low dropout linear regulator of known technology;

FIG. 2 is a schematic diagram of a host computer switching between different power modes;

3 is a schematic diagram of a power control device according to an embodiment of the present invention;

FIG. 4 is a timing diagram of a power control device according to the present invention.

Reference number

100～LDO 110～sampling circuit

120～comparison amplifier 130～power amplifier

300～system 310～power control device

320～host 340～control load

342～control circuit 346～dummy load

V _in ～input voltage V _out ～output voltage

V _sp ～sampling voltage V _REF ～reference voltage

IN ₁ ~command IN ₂ ~command

Power_up～power switching signal I _VO ～output current

LDO_ready～start signal Crl～control signal

i _b ～saturation electric value i _a ～current value in power saving mode

t1, t2, t3～time R ₁ , R ₂ ～resistance

330～LDO

Detailed ways

In order to make the above and other objects, features, and advantages of the present invention more comprehensible, a few preferred embodiments are listed below and described in detail in conjunction with the accompanying drawings.

FIG. 3 is a schematic diagram of a power control device according to an embodiment of the invention. The host 320 can be switched between a power saving mode (low current mode in this embodiment) and a working mode (normal current mode in this embodiment). Those familiar with the art know that when the computer host switches power modes, it will send a signal to notify its peripheral devices. In this embodiment, when the host 320 is about to enter the working mode in the power saving mode, it will send a power switching signal Power_up to the power control device of the present invention, and the purpose of the power control device 310 of the present invention is That is: when the host 320 returns from the power-saving mode to the working mode and the current increases sharply, it can still provide power to the host 320 stably.

The power control device 310 of the present invention includes at least a voltage regulator 330 and a control load 340 . For example, the voltage regulator 330 in this embodiment is a low-dropout linear voltage regulator 330 (LDO330 for short), but in other embodiments it can be replaced by other voltage regulators such as a DC-to-DC converter. Technical personnel need not be limited to this. Wherein, the LDO 330 is used to receive an input voltage V _in from a voltage source (not shown in the figure), and provide an output voltage V _out to the host 320 through an output terminal A. The control load 340 is coupled to the output terminal A of the LDO 330 and the host 320, wherein when the control load 340 receives the power switching signal Power_up sent by the host 320, it will output from the LDO 330 The terminal A draws a current, and the output current I _VO of the LDO 330 will gradually increase accordingly. In addition, the control load 340 sends a startup signal LDO_ready to the host 320 after a predetermined time to notify the host 320 that it is safe to enter the working mode. For example, if the host 320 is a digital device, the host 320 can start its working mode by turning on a clock generator. Through the delay effect of the predetermined time in the present invention, the host 320 will not suddenly switch from the power saving mode to the working mode, which will prevent the LDO 330 from being damaged due to an instantaneous voltage difference, thereby affecting the stability of the host 320 .

In a preferred embodiment, the control load 340 of the present invention further includes a control circuit 342 and a dummy load (Dummy Load) 346 . The control circuit 340 is coupled to the host 320, and is used to send a control signal Cr1 to the dummy load 344 when receiving the power switching signal Power_up from the host 320, and send the startup signal after the predetermined time. LDO_ready to host 320 . The dummy load (Dummy Load) 346 is coupled between the control circuit 342 and the LDO 330, and is used to receive the control signal Cr1 to make the LDO 330 within the predetermined time. The output current I _VO is increased to a certain value. For example, the dummy load 346 can be controlled by the control signal Cr1 so that the output current of the LDO 330 enters its saturation region within the predetermined time, and the fixed value is the dummy load 346 the saturation current value. The characteristics of the dummy load 346 are a known technology, so details will not be repeated here.

FIG. 4 is a timing diagram of a power control device according to the present invention. Please also refer to the above embodiments. It can be seen from the figure that, according to the present invention, the low-level power switching signal Power_up indicates that the host 320 is still in the power-saving mode. The host 320 sends a power switching signal Power_up at time _t1 (i.e. the power switching signal Power_up is switched from a low level to a high level), at this time the host 320 will not directly enter the working mode, instead, it is controlled by the control of the present invention According to the function of the circuit 342, the host 320 will enter the working mode after an interval of a predetermined time _td . And within this predetermined time _td , the dummy load 346 will draw current from the LDO 330 so that the output current I _VO of the LDO 330 gradually increases from the current value _ia in the power saving mode, and then, for example In other words, the dummy load 346 can make the output current I _VO reach a saturation current value _ib according to its own characteristics at time t2 . After the predetermined time t _d has passed, the host computer 320 will completely enter the working mode at time _t3 . At this time, the LDO 330 has reached an ideal state after the action of the present invention and will not be damaged by the high current of the working mode. Finally, at the time _t4 , the controlling circuit 342 can turn off the function of drawing current of the dummy load 346 to save electric energy, but the present invention is not limited thereto. In addition, those skilled in the art can make appropriate configurations for each time period (including t ₁ to t ₂ , t ₂ to t ₃ ) of the predetermined time t _d according to the present invention.

Overall, the above-mentioned embodiments are a system 300 that can safely enter a working mode from a power-saving mode. Referring to FIG. 3 , the system 300 includes a host 320 , an LDO 330 , a control circuit 342 , and a dummy load 346 . Wherein the host 320 sends a power switching signal Power_up when the power saving mode is about to enter the working mode. The LDO 330 is used to receive an input voltage V _in and provide an output voltage V _out to the host 320 through an output terminal A. As shown in FIG. The control circuit 342 is used to send a control signal Cr1 when receiving the power switching signal Power_up, and send the startup signal LDO_ready to the host 320 after a predetermined time _td to notify the host 320 to enter the Operating mode. The dummy load 346 is coupled between the control circuit 342 and the LDO 330, and is used to receive the control of the control signal Cr1 to make the output current _IVO of the LDO 330 within the predetermined time t _d raised to a certain value.

All modifications and changes shall be included within the scope of the present invention, and shall be protected by the claims.

Claims (18)

1. power control; It is characterized in that; Get into a mode of operation in order to control a main frame from a battery saving mode safety, wherein said main frame sends a power supply switching signal when said battery saving mode is about to get into said mode of operation, and said power control comprises:

One voltage stabilizer, in order to receiving an input voltage, and with an output terminal in order to an output voltage to said main frame to be provided; And

One control load in order to when receiving said power supply switching signal, draws an electric current from the said output terminal of said voltage stabilizer, and behind a given time, sees an enabling signal to said main frame off and get into said mode of operation to notify said main frame; Wherein, said control load comprises: a control circuit, in order to when receiving said power supply switching signal, sending a control signal, and behind said given time, see said enabling signal off; And a dummy load, being coupled between said control circuit and the said voltage stabilizer, the said current boost that in said given time, makes said voltage stabilizer output in order to the control that receives said control signal is to certain value.

2. power control as claimed in claim 1 is characterized in that, said definite value is higher than said main frame and under said battery saving mode, operates required current value.

3. power control as claimed in claim 1 is characterized in that, said control circuit makes said dummy load in said given time, make said voltage stabilizer output get into a saturation region.

4. power control as claimed in claim 1 is characterized in that, said control circuit cuts out said dummy load after said main frame gets into said mode of operation.

5. power control as claimed in claim 1 is characterized in that, said battery saving mode is a low current mode; And said mode of operation is a normal current pattern.

6. power control as claimed in claim 1 is characterized in that, said voltage stabilizer is that a direct current is to direct current transducer.

7. power control as claimed in claim 1 is characterized in that, said voltage stabilizer is a low pressure difference linear voltage regulator.

8. power control as claimed in claim 1 is characterized in that said input voltage is different from said output voltage.

9. power control as claimed in claim 1 is characterized in that, said main frame gets into said mode of operation through opening a clock pulse generator.

10. a system that uses power control is characterized in that, can get into a mode of operation from a battery saving mode safety, and said system comprises:

One main frame sends a power supply switching signal when said battery saving mode is about to get into said mode of operation;

One voltage stabilizer in order to receiving an input voltage, and provides an output voltage to said main frame with an output terminal;

One control circuit in order to when receiving said power supply switching signal, sending a control signal, and is seen enabling signal to said main frame off and is got into said mode of operation to notify said main frame behind a given time; And

One dummy load is coupled between said control circuit and the said voltage stabilizer, and the current boost that in said given time, makes said voltage stabilizer output in order to the control that receives said control signal is to certain value.

11. system as claimed in claim 10 is characterized in that, said definite value is higher than said main frame and under said battery saving mode, operates required current value.

12. system as claimed in claim 10 is characterized in that, said control circuit makes said dummy load in said given time, make said voltage stabilizer output get into a saturation region.

13. system as claimed in claim 10 is characterized in that, said control circuit cuts out said dummy load after said main frame gets into said mode of operation.

14. system as claimed in claim 10 is characterized in that, said battery saving mode is a low current mode; And said mode of operation is a normal current pattern.

15. system as claimed in claim 10 is characterized in that, said voltage stabilizer is that a direct current is to direct current transducer.

16. system as claimed in claim 10 is characterized in that, said voltage stabilizer is a low pressure difference linear voltage regulator.

17. system as claimed in claim 10 is characterized in that, said input voltage is different from said output voltage.

18. system as claimed in claim 10 is characterized in that, said main frame gets into said mode of operation through opening a clock pulse generator.

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