CN101938274B - Integrated gate drive circuit - Google Patents

Abstract

An integrated grid drive circuit comprises an output drive circuit and a voltage stabilizing circuit, wherein the voltage stabilizing circuit is used for stabilizing the output voltage output by the output drive circuit so as to eliminate the ripple of the output voltage.

Description

Integrated gate drive circuit

technical field

The invention relates to a liquid crystal display, in particular to an integrated gate driving circuit of a liquid crystal display.

Background technique

A liquid crystal display controls the operation of each pixel through a plurality of gate drive circuits and source drive circuits to display images. In order to increase the definition of the picture displayed by the liquid crystal display, the resolution of the liquid crystal display is rapidly increased, thus more driving circuits are required for driving, resulting in a substantial increase in manufacturing.

Please refer to FIG. 1, which shows a schematic diagram of a known liquid crystal display, wherein the gate drive circuit of the liquid crystal display 9 and the pixel matrix 91 can be fabricated on the same substrate at the same time to reduce the production cost. This gate drive circuit is called It is an integrated gate driver circuit (integrated gate driver circuit) 92 . The integrated gate drive circuit 9 may be composed of multiple drive units connected in series.

Please refer to FIGS. 2a and 2b. FIG. 2a shows a circuit diagram of the driving unit 920 of the integrated gate driving circuit; FIG. 2b shows an operation timing diagram of the driving unit 920. The driving unit 920 receives an input signal Input, a first clock signal CK1 and a second clock signal CK2; and generates an output signal Output.

In the first time interval t1, the first clock signal CK1 turns on the first switch T1 and the third switch T3 at the same time, and at this time, the voltage of a node X is converted from a low level (low) to a high level (high). Turn on the second switch T2. Since the second clock signal CK2 is at a low level during this time interval, the driving unit 920 outputs a low level output signal Output.

In the second time interval t2, the second clock signal CK2 changes from a low level to a high level. Since the potential of the node X is still maintained at a high level at this time, the driving unit 920 outputs a high level output The signal Output, wherein the output signal Output is simultaneously used as the input signal of the next cascaded stage of the driving unit 920 .

In the third time interval t3, the first clock signal CK1 turns on the first switch T1 and the third switch T3 simultaneously again, at this moment, the potentials of the node X and the output signal Output are both changed to low level. In a fourth time interval t4, the second clock signal CK2 is converted to a high level again, and at this time, the potential of the node X is subjected to the coupling effect of the parasitic capacitance of the second switch T2 to generate ripples, and cause The output signal Output generates ripples.

In view of this, it is necessary to propose another integrated gate driving circuit, which has better output driving characteristics, so as to avoid malfunction of the liquid crystal display.

Contents of the invention

The present invention proposes an integrated gate drive circuit, which eliminates the ripple of the output signal output by the integrated gate drive circuit by setting a voltage stabilizing circuit.

The present invention proposes an integrated gate drive circuit that receives multiple clock signals and includes multiple serially connected drive units. Each drive unit includes an input terminal, an output terminal, an output drive circuit and a first voltage stabilizing circuit. The output driving circuit includes a first switch, a second switch and a third switch. The first switch has a control terminal for receiving a first clock signal, a first terminal coupled to the input terminal and a second terminal coupled to a first node. The second switch has a control end coupled to the first node, a first end receiving a second clock signal, and a second end coupled to the output end. The third switch has a control terminal for receiving the first clock signal, a first terminal coupled to the output terminal and a second terminal coupled to a first potential. The first voltage stabilizing circuit includes a fourth switch, a fifth switch and a sixth switch. The fourth switch has a first terminal coupled to a second potential, a second terminal coupled to a second node, and a control terminal coupled to the first terminal of the fourth switch. The fifth switch has a first end coupled to the second node, a second end coupled to the first potential, and a control end coupled to the output end. The sixth switch has a first terminal coupled to the output terminal, a second terminal coupled to the first potential and a control terminal coupled to the second node.

The present invention also proposes an integrated gate drive circuit that receives multiple clock signals and includes multiple identical and serially connected drive units, each drive unit includes an input terminal, an output terminal, an output drive circuit and a voltage stabilizing circuit . The output driving circuit includes a first switch, a second switch and a third switch. The first switch has a control terminal for receiving a first clock signal, a first terminal coupled to the input terminal and a second terminal coupled to a first node. The second switch has a control end coupled to the first node, a first end receiving a second clock signal, and a second end coupled to the output end. The third switch has a control terminal for receiving the first clock signal, a first terminal coupled to the output terminal and a second terminal coupled to a voltage source. The voltage stabilizing circuit includes a tenth switch, an eleventh switch, a twelfth switch and a thirteenth switch. The tenth switch has a first terminal coupled to the output terminal, a second terminal coupled to the voltage source, and a control terminal coupled to a second node. The eleventh switch has a first terminal coupled to the second node, a second terminal coupled to the voltage source, and a control terminal coupled to the first node. The twelfth switch has a first terminal coupled to the second node, a second terminal coupled to the first node of the driving unit next to the driving unit, and a control terminal coupled to the second terminal. The thirteenth switch has a first terminal coupled to the first node, a second terminal coupled to the voltage source, and a control terminal coupled to the second node.

The present invention further proposes an integrated gate driving circuit that receives multiple clock signals and includes multiple driving units connected in series, each driving unit includes an input terminal, an output terminal, an output driving circuit and a balancing capacitor. The output driving circuit includes a first switch, a second switch and a third switch. The first switch has a control terminal for receiving a first clock signal, a first terminal coupled to the input terminal and a second terminal coupled to a node. The second switch has a control terminal coupled to the node, a first terminal receiving a second clock signal and a second terminal coupled to the output terminal. The third switch has a control terminal for receiving the first clock signal, a first terminal coupled to the output terminal and a second terminal coupled to a voltage source. The balancing capacitor is coupled between the node and the control terminal of the third switch.

The present invention further proposes an integrated gate driving circuit that receives multiple clock signals and includes multiple serially connected driving units, each driving unit includes an output driving circuit and a first voltage stabilizing circuit. The output driving circuit has an output terminal. The first voltage stabilizing circuit includes a fourth switch, a fifth switch and a sixth switch. The fourth switch has a first terminal coupled to a high potential, a second terminal coupled to a second node, and a control terminal coupled to the first terminal of the fourth switch. The fifth switch has a first terminal coupled to the second node, a second terminal coupled to a low potential, and a control terminal coupled to the output terminal. The sixth switch has a first terminal coupled to the output terminal, a second terminal coupled to the low potential, and a control terminal coupled to the second node; wherein, when the output voltage of the output driving circuit is high , the fifth switch is turned on and the sixth switch is turned off to maintain the output voltage at a high level; when the output voltage of the output drive circuit is at a low level, the fifth switch is turned off and the sixth switch is turned on To maintain the output terminal voltage as a low level.

In the integrated gate drive circuit of the present invention, by setting a voltage stabilizing circuit to stabilize the output voltage of the output drive circuit of the integrated gate drive circuit, the malfunction of the liquid crystal display can be avoided.

Description of drawings

FIG. 1 shows a schematic diagram of a conventional liquid crystal display.

FIG. 2a shows a circuit diagram of a conventional integrated gate driving circuit.

FIG. 2b shows a timing diagram of the operation of the integrated gate driving circuit of FIG. 2a.

FIG. 3 a shows a block diagram of an integrated gate driving circuit according to an embodiment of the present invention.

FIG. 3b shows a block diagram of a driving unit of the integrated gate driving circuit of FIG. 3a.

FIG. 4 a shows a circuit diagram of a driving unit of an integrated gate driving circuit according to an embodiment of the present invention.

FIG. 4b shows a timing diagram of the operation of the driving unit in FIG. 4a.

FIG. 5 a shows a circuit diagram of a driving unit of an integrated gate driving circuit according to another embodiment of the present invention.

FIG. 5b shows a schematic diagram of the operation of the driving unit in FIG. 5a.

FIG. 6 shows a circuit diagram of a driving unit of an integrated gate driving circuit according to another embodiment of the present invention.

Detailed ways

In order to make the above and other objects, features, and advantages of the present invention more apparent, a detailed description will be given below with reference to the accompanying drawings. In the description of the present invention, the same components are denoted by the same symbols, and they will be described in advance.

Please refer to FIG. 3 a , which shows a block diagram of an integrated gate driving circuit 1 according to an embodiment of the present invention. The integrated gate drive circuit 1 includes a plurality of identical drive units connected in series, such as a first drive unit 10 (assumed to be a first-level drive unit), a second drive unit 20 and a third drive unit shown in the figure. drive unit 30 and the like. Each driving unit receives an input signal and a plurality of clock signals, and generates an output signal as an input signal of the next-level driving unit, for example, the first driving unit 10 receives two clock signals CK1, CK2 and an input signal Sin and Generate an output signal Sout, the output signal Sout is also used as the input signal Sin' of the second driving unit 20; wherein, these clock signals CK1, CK2, CK3 are provided by a clock generator (not shown), and the A clock generator may or may not be included in the integrated gate drive circuit 1 .

Next, the first driving unit 10 is taken as an example to illustrate the circuit diagram and operation method of each driving unit, and other driving units are similar to the first driving unit 10 . In addition, in the description of the present invention, the high level can be, for example, 17 volts, and the low level can be, for example, -10 volts, but this is not intended to limit the present invention. The switch referred to in this specification can be, for example, a thin film field effect transistor or a semiconductor switching element.

Please refer to Figure 3b, the first drive unit 10 includes an output drive circuit 11 and a voltage regulator circuit 12, the output drive circuit 11 receives two clock signals CK1, CK2 and an input signal Sin; and outputs an output signal Sout , wherein the output signal Sout is also used as the input signal Sin′ of the next-level driving unit (for example, the second driving unit 20 ). The voltage stabilizing circuit 12 is used to stabilize the output signal Sout. There is a preset phase difference between the clock signals CK1 and CK2.

Please refer to FIG. 4 a , which shows an embodiment of the circuit diagram of the first driving unit 10 , including an output driving circuit 11 , a first voltage stabilizing circuit 121 and a second voltage stabilizing circuit 122 . The output driving circuit 11 includes a first switch T1, a second switch T2, a third switch T3 and a capacitor Cx. The control end of the first switch T1 receives the first clock signal CK1 , the first switch T1 has a first end receiving an input signal Sin; a second end coupled to a node X. A control terminal of the second switch T2 is coupled to the node X, and the second switch T2 has a first terminal for receiving the second clock signal CK2. The control end of the third switch T3 is coupled to the control end of the first switch T1 to receive the first clock signal CK1, the third switch T3 has a first end coupled to the second end of the second switch T2; The second end is coupled to a voltage source Vss, such as a low voltage source of -10 volts, wherein the connection between the second switch T2 and the third switch T3 is used as the output drive circuit 11 (the first drive unit 10 ) The output terminal O. The capacitor Cx is coupled between the node X and the output terminal O of the output driving circuit 11, so as to reduce the coupling effect between the parasitic capacitance of the first switch T1 and the second switch T2 and the signal, however, the capacitor Cx may not be be implemented.

In this embodiment, the first voltage stabilizing circuit 121 is coupled to the output terminal O of the output driving circuit 11 for stabilizing the output signal Sout of the first driving unit 10; the second voltage stabilizing circuit 122 is coupled to the The node X of the output driving circuit 11 is used to stabilize the voltage of the node X. The first voltage stabilizing circuit 121 includes a fourth switch T4 , a fifth switch T5 and a sixth switch T6 . The fourth switch T4 has a first terminal coupled to a voltage source Vdd, such as a high voltage source of 17 volts; a second terminal coupled to a node Z0, the control terminal of the fourth switch T4 coupled to its first terminal one end. The control terminal of the fifth switch T5 is coupled to the output terminal O of the output driving circuit 11 , and the fifth switch T5 has a first terminal coupled to the node Z0 and a second terminal coupled to the voltage source Vss. The control terminal of the sixth switch T6 is coupled to the node Z0 , and the sixth switch T6 has a first terminal coupled to the output terminal O of the output driving circuit 11 ; a second terminal coupled to the voltage source Vss.

The second voltage stabilizing circuit 122 includes a seventh switch T7 , an eighth switch T8 and a ninth switch T9 . The seventh switch T7 has a first terminal coupled to the voltage source Vdd; a second terminal coupled to a node ZX, and a control terminal of the seventh switch T7 coupled to the first terminal. The control terminal of the eighth switch T8 is coupled to the node X of the output driving circuit 11 , the eighth switch T8 has a first terminal coupled to the node ZX; a second terminal coupled to the voltage source Vss. The control terminal of the ninth switch T9 is coupled to the node ZX, and the ninth switch T9 has a first terminal coupled to the node X of the output driving circuit 11 ; a second terminal coupled to the voltage source Vss.

Please refer to FIGS. 4a and 4b. FIG. 4b is a timing diagram of the operation of FIG. 4a. In the first time interval t1, a high level first clock signal CK1 is simultaneously input to the control terminals of the first switch T1 and the third switch T3; the first terminal of the first switch T1 receives a high level The input signal Sin. At this time, the first switch T1 and the third switch T3 are turned on. Thereby, the voltage of the node X is changed to a high level and the eighth switch T8 is turned on so that the voltage of the node ZX is changed to a low level; the output signal Sout is also maintained at a low level and the fifth switch T5 is turned off so that The voltage of the node Z0 maintains a high level.

In the second time interval t2, a high-level second clock signal CK2 is input to the first end of the second switch T2; the first clock signal CK1 and the input signal Sin are converted to low-level during this time interval . At this time, the first switch T1 and the third switch T3 are turned off and the second switch T2 is turned on. Thus, the voltage of the node X is still at a high level and the eighth switch T8 is turned on so that the voltage of the node ZX is still at a low level; the output signal Sout is converted to a high level and the fifth switch T5 is turned on so that The voltage of the node Z0 is converted to a low level.

In the third time interval t3, the input signal Sin is maintained at a low level; the first clock signal CK1 is switched to a high level; and the second clock signal CK2 is switched to a low level. At this moment, the first switch T1 and the third switch T3 are turned on again, thereby, the voltage of the node X turns into a low level and the eighth switch T8 is turned off so that the voltage of the node ZX turns into a high level; The output signal Sout is at a low level and the fifth switch T5 is turned off so that the voltage of the node Z0 is converted to a high level and the sixth switch T6 is turned on so that the output signal Sout remains at a low level.

In the fourth time interval t4, the input signal Sin is maintained at a low level; the first clock signal CK1 is switched to a low level; and the second clock signal CK2 is switched to a high level. At this time, the first switch T1, the second switch T2 and the third switch T3 are all turned off. In this time interval, when the second clock signal CK2 changes from a low level to a high level, the parasitic capacitance of the second switch T2 will cause the voltage of the node X to fluctuate through the coupling effect, thereby causing the output signal Sout The voltage floats. Therefore, in the present invention, through the first voltage stabilizing circuit 121, the voltage floating of the output signal Sout can be maintained at a low level through the sixth switch T6 of the first voltage stabilizing circuit 121; the voltage floating of the node X can be maintained via The ninth switch T9 of the second voltage stabilizing circuit 122 maintains a low level. In this embodiment, by setting the first voltage stabilizing circuit 121 and/or the second voltage stabilizing circuit 122 , the voltage of the output signal Sout of the first driving unit 10 can be effectively stabilized. In one embodiment, the first driving unit 10 is only provided with the first voltage stabilizing circuit 121 . In addition, the capacitor Cx is used to reduce the coupling effect between the parasitic capacitance of the first switch T1 and the second switch T2 and the signal.

Please refer to FIG. 5 a , which shows another embodiment of the circuit diagram of the first driving unit of the present invention. The first driving unit 10 ′ includes an output driving circuit 11 and a voltage stabilizing circuit 12 ′. In this embodiment, the output driving circuit 11 is the same as the output driving circuit 11 shown in FIG. 4 a , so details are omitted here. The voltage stabilizing circuit 12 ′ is coupled to the node X and the output terminal O of the output driving circuit 11 for stabilizing the voltages of the node X and the output terminal O.

The voltage stabilizing circuit 12' includes a tenth switch T10, an eleventh switch T11, a twelfth switch T12 and a thirteenth switch T13. The control terminal of the tenth switch T10 is coupled to a node P, and the tenth switch T10 has a first terminal coupled to the output terminal O of the output driving circuit 11; a second terminal coupled to a voltage source Vss, for example A low voltage source of -10 volts. The tenth switch T10 is used to stabilize the voltage of the output terminal O of the output driving circuit 11 . The control terminal of the eleventh switch T11 is coupled to the node X of the output driving circuit 11 ; the eleventh switch T11 has a first terminal coupled to the node P; a second terminal coupled to the voltage source Vss. The twelfth switch T12 has a first end coupled to the node P; a second end coupled to a signal source X', which is the node X' in the next-stage drive unit of the first drive unit 10' ; and a control terminal coupled to the second terminal. The control terminal of the thirteenth switch T13 is coupled to the node P. The thirteenth switch T13 has a first terminal coupled to the node X of the output driving circuit 11 ; a second terminal coupled to the voltage source Vss. The voltage stabilizing circuit 12' may further include a capacitor coupled between the node P and the voltage source Vss for maintaining the voltage of the node P.

Please refer to FIG. 5 b , which shows a schematic diagram of the operation of the first driving unit 10 ′ in FIG. 5 a , wherein “1” represents a high level voltage; “0” represents a low level voltage. In the first time interval t1, a high-level input signal Sin is input to the first end of the first switch T1; a low-level second clock signal CK2 is input to the first end of the second switch T2; The high-level first clock signal CK1 is simultaneously input to the control terminals of the first switch T1 and the third switch T3 to simultaneously turn on the first switch T1 and the third switch T3 . Thereby, the voltage of the node X changes to a high level to turn on the second switch T2 and the eleventh switch T11 so that the voltage of the node P becomes a low level to turn off the tenth switch T10; the signal source X' In this time interval, the twelfth switch T12 is turned off to keep the voltage of the node P at a low level, and the thirteenth switch T13 is turned off, so that the potential of the node X can be kept at a high level and The output signal Sout is maintained at a low level.

In the second time interval t2, the input signal Sin and the first clock signal CK1 are switched from high level to low level; the second clock signal CK2 is switched from low level to high level. Thereby, the first switch T1 and the third switch T3 are turned off, the potential of the node X is still maintained at a high level, and the second switch T2 is turned on so that the output signal Sout is converted to a high level; The eleventh switch T11 is turned on so that the node P is still maintained at a low level to close the tenth switch T10; the signal source X' is at a high level during this time interval to turn on the twelfth switch T12 to make the node P The voltage of P is maintained at a low level and the thirteenth switch T13 is turned off, so that the potential of the node X is maintained at a high level and the output signal Sout is maintained at a high level.

In the third time interval t3, the input signal Sin is still at a low level; the first clock signal CK1 is switched to a high level; the second clock signal CK2 is switched to a low level. Thereby, the first switch T1 and the third switch T3 are turned on again so that the potential of the node X is converted to a low level and the second switch T2 and the eleventh switch T11 are turned off; the output signal Sout is converted to low level. The signal source X' is maintained at a high level during this time interval, and the twelfth switch T12 is turned on so that the voltage of the node P is converted to a high level, and the thirteenth switch T13 is turned on to maintain the potential of the node X as At the same time, the tenth switch T10 is turned on to maintain the output signal Sout at the low level.

In the fourth time interval T4, the input signal Sin is still at a low level; the first clock signal CK1 is switched to a low level; the second clock signal CK2 is switched to a high level. At this time, the first switch T1, the second switch T2 and the third switch T3 are all turned off. During this time interval, the potential of the node X remains at a low level and the eleventh switch T11 is turned off; the output signal Sout also remains at a low level. The signal source X' is switched to a low level during this time interval, the twelfth switch T12 is turned off so that the voltage of the node P is maintained at a high level, and the thirteenth switch T13 is turned on to maintain the potential of the node X at At the same time, the tenth switch T10 is turned on to maintain the output signal Sout at the low level. In the present invention, by setting the voltage stabilizing circuit 12', the floating voltage of the node X can be maintained at a low level through the thirteenth switch T13 of the voltage stabilizing circuit 12'; the voltage floating of the output signal Sout can be maintained through the The tenth switch T10 of the voltage stabilizing circuit 12' is maintained at a low level. In this embodiment, the output voltage of the output signal Sout of the first driving unit 10' can be effectively stabilized by providing the voltage stabilizing circuit 12'.

Please refer to FIG. 6, which shows another embodiment of the circuit diagram of the first driving unit of the present invention, the output driving circuit of the first driving unit 10 "is the same as the output driving circuit 11 of FIGS. 4a and 5a, and is not described here. Let me repeat. In this embodiment, a balance capacitor Ct is connected between the control terminal of the second switch T2 and the control terminal of the third switch T3. Since the level of the first clock signal CK1 and the level of the second clock signal CK2 The level changes in the opposite direction, so the capacitance value of the balance capacitor Ct is set to just offset the coupling effect caused by the parasitic capacitance of the first switch T1 and the change of the second clock signal CK2 when the first clock signal CK1 changes. Due to the coupling effect generated by the parasitic capacitance of the second switch T2, the voltage of the node X is stabilized to reduce the ripple of the output signal Sout.

As mentioned above, since the output of the known integrated control terminal drive circuit has ripples, it is easy to cause malfunction of the liquid crystal display. The present invention eliminates the ripple of the output signal output by the integrated gate drive circuit by disposing a voltage stabilizing circuit (FIGS. 4a and 5a) or a balancing capacitor (FIG. 6) at the output terminal of the integrated control terminal driving circuit.

Although the present invention has been disclosed by the foregoing embodiments, they are not intended to limit the present invention. Any person skilled in the art may make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention should be determined by the appended claims.

Claims (24)

1. integrated gate drive circuitry receives a plurality of clock signals and comprises the driver element of a plurality of serial connections, and each driver element comprises:

One input end;

One output terminal;

One output driving circuit comprises:

One first switch has that a control end receives one first clock signal, a first end couples this input end and one second end couples a first node;

One second switch has that a control end couples this first node, a first end receives a second clock signal and one second end couples this output terminal; And

One the 3rd switch has that a control end receives this first clock signal, a first end couples this output terminal and one second end couples one first current potential; And

One first mu balanced circuit comprises:

One the 4th switch has a first end and couples one second current potential, one second end and couple the first end that a Section Point and a control end couple the 4th switch;

One the 5th switch has that a first end couples this Section Point, one second end couples this first current potential and a control end couples this output terminal; And

One the 6th switch has that a first end couples this output terminal, one second end couples this first current potential and a control end couples this Section Point.

2. according to claim 1 integrated gate drive circuitry, wherein the output terminal of each driver element is coupled to the input end of next stage driver element.

3. according to claim 1 integrated gate drive circuitry, wherein this driver element comprises in addition one second mu balanced circuit and couples this first node.

4. according to claim 3 integrated gate drive circuitry, wherein this second mu balanced circuit comprises:

One minion is closed, and has that a first end couples this second current potential, one second end couples one the 3rd node and a control end couples the first end that this minion is closed;

One the 8th switch has that a first end couples the 3rd node, one second end couples this first current potential and a control end couples this first node; And

One the 9th switch has that a first end couples this first node, one second end couples this first current potential and a control end couples the 3rd node.

5. according to claim 4 integrated gate drive circuitry, wherein the 7th to the 9th switch is Thin Film Transistor (TFT).

6. according to claim 1 integrated gate drive circuitry, wherein this output driving circuit comprises in addition an electric capacity and is coupled between this first node and this output terminal.

7. according to claim 1 integrated gate drive circuitry, wherein this first to the 6th switch is Thin Film Transistor (TFT).

8. according to claim 1 integrated gate drive circuitry, wherein this first current potential is lower than this second current potential.

9. according to claim 1 integrated gate drive circuitry wherein has a phase differential between this first clock signal and this second clock signal.

10. integrated gate drive circuitry receives a plurality of clocks letters and comprises the driver element of a plurality of identical and serial connections, and each driver element comprises:

One input end;

One output terminal;

One output driving circuit comprises:

One first switch has that a control end receives one first clock signal, a first end couples this input end and one second end couples a first node;

One second switch has that a control end couples this first node, a first end receives a second clock signal and one second end couples this output terminal; And

One the 3rd switch has that a control end receives this first clock signal, a first end couples this output terminal and one second end couples a voltage source; And

One mu balanced circuit comprises:

The tenth switch has that a first end couples this output terminal, one second end couples this voltage source and a control end couples a Section Point;

The 11 switch has that first end couples this Section Point, one second end couples this voltage source and a control end couples this first node;

One twelvemo is closed, and has a first end and couples first node and the control end that this Section Point, one second end couple the next stage driver element of this driver element and couple this second end; And

The 13 switch has that a first end couples this first node, one second end couples this voltage source and a control end couples this Section Point.

11. integrated gate drive circuitry according to claim 10, wherein this mu balanced circuit comprises in addition an electric capacity and is coupled between this Section Point and this voltage source.

12. integrated gate drive circuitry according to claim 10, wherein the output terminal of each driver element is coupled to the input end of next stage driver element.

13. integrated gate drive circuitry according to claim 10, wherein this output driving circuit comprises in addition an electric capacity and is coupled between this first node and this output terminal.

14. integrated gate drive circuitry according to claim 10, wherein this first to the 3rd switch and the tenth to the 13 switch are Thin Film Transistor (TFT).

15. integrated gate drive circuitry according to claim 10, wherein this voltage source is a low-potential voltage source.

16. integrated gate drive circuitry according to claim 10 wherein has a phase differential between this first clock signal and this second clock signal.

17. an integrated gate drive circuitry receives the driver element that a plurality of serial connections are believed and comprised to a plurality of clocks, each driver element comprises:

One input end;

One output terminal;

One output driving circuit comprises;

One first switch has a control end and receives one first clock signal, and a first end couples this input end and one second end couples a node;

One second switch has a control end and couples this node, and a first end receives a second clock signal and one second end couples this output terminal; And

One the 3rd switch has a control end and receives this first clock signal, and a first end couples this output terminal and one second end couples a voltage source; And

One balancing capacitance is coupled between the control end of this node and the 3rd switch.

18. integrated gate drive circuitry according to claim 17, wherein the capacitance of this balancing capacitance is set as the coupling effect that the stray capacitance of this first and second switch of balance causes.

19. integrated gate drive circuitry according to claim 17, wherein the output terminal of each driver element is coupled to the input end of next stage driver element.

20. integrated gate drive circuitry according to claim 17 wherein has a phase differential between this first clock signal and this second clock signal.

21. an integrated gate drive circuitry receives the driver element that a plurality of serial connections are believed and comprised to a plurality of clocks, each driver element comprises:

One output driving circuit comprises an output terminal; And

One first mu balanced circuit comprises:

One the 4th switch has a first end and couples a noble potential, one second end and couple the first end that a Section Point and a control end couple the 4th switch;

One the 5th switch has that a first end couples this Section Point, one second end couples an electronegative potential and a control end couples this output terminal; And

One the 6th switch has that a first end couples this output terminal, one second end couples this electronegative potential and a control end couples this Section Point;

Wherein, when the output end voltage of this output driving circuit was high levle, it was high levle that the 5th switch open and the 6th switch close to keep this output end voltage; When the output end voltage of this output driving circuit is low level, the 5th switch close and the 6th switch open to keep this output end voltage as low level.

22. integrated gate drive circuitry according to claim 21, wherein this output driving circuit comprises in addition:

One input end;

One first switch has that a control end receives one first clock signal, a first end couples this input end and one second end couples a first node;

One second switch has that a control end couples this first node, a first end receives a second clock signal and one second end couples this output terminal; And

One the 3rd switch has that a control end receives this first clock signal, a first end couples this output terminal and one second end couples this electronegative potential.

23. integrated gate drive circuitry according to claim 22, other comprises one second mu balanced circuit, comprises:

One minion is closed, and has that a first end couples this noble potential, one second end couples one the 3rd node and a control end couples the first end that this minion is closed;

One the 8th switch has that a first end couples the 3rd node, one second end couples this electronegative potential and a control end couples this first node; And

One the 9th switch has that a first end couples this first node, one second end couples this electronegative potential and a control end couples the 3rd node.

24. integrated gate drive circuitry according to claim 22, wherein this output driving circuit comprises in addition an electric capacity and is coupled between this first node and this output terminal.

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