CN101937639A - A pulse modulation circuit - Google Patents

Abstract

The invention discloses a pulse modulation circuit, which is suitable for generating a grid driving signal and comprises: an input unit for providing an input voltage; a voltage conversion unit comprising: a first transistor having a gate connected to an input voltage; a second transistor having a source connected to a first threshold voltage; a third transistor; and a fourth transistor having a drain connected to the second threshold voltage; a buffer unit having an input terminal and an output terminal, the input terminal being connected to the drain of the first transistor; and a complementary module including NMOS and PMOS transistors, the source of the former being connected to the first threshold voltage through a regulating resistor, and the source of the latter being connected to the second threshold voltage. By adopting the pulse modulation circuit, the input voltage signal is converted by the voltage conversion unit and the buffer unit, so that the normal work of corresponding transistors in the complementary module can be ensured, and the problem of unstable voltage caused by unidirectional conduction of a diode on a current path of a driving signal is solved.

Description

A pulse modulation circuit

technical field

The invention relates to a pulse modulation circuit, in particular to a pulse modulation circuit used for generating grid driving signals in a thin film transistor liquid crystal display.

Background technique

For the traditional thin film transistor liquid crystal display (Thin Film Transistor Liquid Crystal Display, TFT-LCD), the driving principle for TFT is usually designed to use the gate control signal to operate the TFT on or off, so as to control each Whether the subpixel is charged. Specifically, when a gate control signal is input to make the TFT "ON", the data signal to be displayed is transmitted to the corresponding sub-pixel through the TFT; when another gate control signal is input to make the TFT "OFF" (off), the data signal to be displayed cannot be transmitted to the corresponding sub-pixel through the TFT.

Generally speaking, the image display of the liquid crystal panel is formed by combining many pixels. In the pixel array of the entire panel, each sub-pixel may be regarded as an equivalent resistance and an equivalent capacitance. In this case, when each gate control signal passes through a series of equivalent resistance and equivalent capacitance to transmit the signal, it will inevitably cause the front-end signal input waveform to be different from the back-end signal input waveform, that is, the waveform delay phenomenon, because these equivalent The resistance and equivalent capacitance create an RC delay constant that delays the input waveform of the signal.

A solution in the prior art is to connect a diode in parallel to AVDD at the output end of the relevant clipping circuit, and use the unidirectional conduction characteristic of the diode to control the lower limit threshold voltage of the clipping circuit, so that the near-end and remote The FeedThrough Voltage (FeedThrough Voltage) is closer. However, in the actual waveform measurement process, the lower limit of the chamfering circuit is not a constant voltage value, because when the diode is turned on, the current path from AVDD to the gate driver will be affected by the unidirectional conduction characteristic of the diode, so that In the past, the flicker phenomenon of the LCD panel could not be better improved.

In view of this, how to design a new type of pulse modulation circuit to generate a suitable gate driving signal is a problem to be solved urgently by technicians in the industry.

Contents of the invention

Aiming at the above-mentioned defects in the design of the pulse modulation circuit used to generate the gate drive signal in the prior art, the present invention provides a new type of pulse modulation circuit.

According to one aspect of the present invention, a pulse modulation circuit is provided, which is suitable for generating a gate drive signal, and the pulse modulation circuit includes:

an input unit, configured to provide an input voltage;

Voltage conversion unit, including:

a first transistor, the gate of which is electrically connected to the input voltage, and the source of which is electrically connected to the first threshold voltage;

a second transistor, the gate of which is electrically connected to the input voltage through an inverter, and the source of which is electrically connected to the first threshold voltage;

a third transistor, the gate of which is electrically connected to the drain of the second transistor, the source of which is electrically connected to the drain of the first transistor, and the drain of which is electrically connected to the second threshold voltage; and

a fourth transistor whose gate is electrically connected to the drain of the first transistor, whose source is electrically connected to the drain of the second transistor, and whose drain is electrically connected to the second threshold voltage;

a buffer unit having an input terminal and an output terminal, the input terminal of the buffer unit is electrically connected to the drain of the first transistor; and

The complementary module includes an NMOS transistor and a PMOS transistor, the respective gates and drains of the NMOS transistor and the PMOS transistor are connected correspondingly, and the source of the NMOS transistor is electrically connected to the first threshold voltage through an adjustable resistor, and the PMOS The source of the transistor is electrically connected to the second threshold voltage.

Preferably, the buffer unit includes a fifth transistor and a sixth transistor, wherein the gate of the fifth transistor is electrically connected to the input terminal of the buffer unit and the gate of the sixth transistor, and the drain of the fifth transistor is electrically connected to the buffer The output terminal of the cell and the drain of the sixth transistor, the source of the fifth transistor is connected to the second threshold voltage and the source of the sixth transistor is connected to the first threshold voltage. In addition, the gate of the fifth transistor is active low, and the gate of the sixth transistor is active high.

Preferably, the complementary module is electrically connected to the output end of the buffer unit through another inverter.

Preferably, the drain of the NMOS transistor is electrically connected to the drain of the PMOS transistor and a gate driver to generate a gate driving signal. In one embodiment, when the input voltage from the input unit is at a low level, the second transistor and the third transistor are turned on and the first transistor and the fourth transistor are turned off, and the output terminal of the buffer unit outputs the first threshold voltage. In another embodiment, when the input voltage from the input unit is at a high level, the first transistor and the fourth transistor are turned on and the second transistor and the third transistor are turned off, and the output terminal of the buffer unit outputs the second threshold voltage. In addition, the pulse modulation circuit further includes a capacitor, one end of the capacitor is electrically connected to the respective drains of the NMOS transistor and the PMOS transistor and the gate driver, and the other end of the capacitor is grounded.

By adopting the pulse modulation circuit of the present invention, the input voltage signal is converted by the voltage conversion unit and the buffer unit, which can ensure the normal operation of the NMOS transistor and the PMOS transistor in the complementary module, and solve the voltage problem caused by the unidirectional conduction of the diode on the current path of the driving signal. unstable problem. In addition, the converted voltage is electrically connected to the preset lower limit of the voltage output of the clipping circuit through an adjustment resistor, when the PMOS transistor is turned on, it can be charged to the upper threshold voltage through the PMOS transistor, and when the NMOS transistor is turned on, Discharge via the NMOS transistor and trim resistor for clipping to the lower threshold voltage.

Description of drawings

Readers will have a clearer understanding of various aspects of the present invention after reading the detailed description of the present invention with reference to the accompanying drawings. in,

Fig. 1 shows a schematic circuit diagram of a pulse modulation circuit according to a preferred embodiment of the present invention;

Fig. 2 shows in the pulse modulating circuit of Fig. 1, the voltage conversion unit and the buffer unit connected in series are a schematic diagram of the circuit state when the input voltage is low level; and

FIG. 3 shows a schematic diagram of the circuit state of the voltage conversion unit and the buffer unit connected in series in the pulse modulation circuit of FIG. 1 when the input level is high.

Detailed ways

Specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

FIG. 1 shows a schematic circuit diagram of a pulse modulation circuit according to a preferred embodiment of the present invention. Referring to FIG. 1, the pulse modulation circuit includes: an input unit, a voltage conversion unit, a buffer unit and a complementary module. Wherein, the input unit is used to provide the input voltage, that is, the input voltage VIN is provided from the signal input terminal in FIG. 1 . The voltage conversion unit mainly includes transistors M1 , M2 , M3 and M4 (hereinafter also referred to as first transistor, second transistor, third transistor and fourth transistor in turn). Specifically, the gate of the first transistor M1 is electrically connected to the input voltage VIN, and the source is electrically connected to the lower limit threshold voltage AVDD (ie, the lower limit voltage after the output waveform is truncated). The gate of the second transistor M2 is electrically connected to the input voltage VIN through an inverter (that is, the level polarity of the input voltage VIN is opposite to the level polarity applied to the gate of the transistor M2), and the source is electrically connected to the input voltage VIN. Connect to the lower threshold voltage, AVDD, above. It can also be drawn from here that since the gate of transistor M1 is directly connected to the input voltage VIN, and the gate of transistor M2 is connected to the input voltage VIN through an inverter, the voltage levels applied to the respective gates of transistors M1 and M2 Polarity is reversed.

The gate of the third transistor M3 is electrically connected to the drain of the transistor M2, its source is electrically connected to the drain of the transistor M1, and its drain is electrically connected to the upper limit threshold voltage VGH, the upper limit threshold voltage is determined by the forward voltage. side to provide. Similarly, the gate of the fourth transistor M4 is electrically connected to the drain of the transistor M1 , the source thereof is electrically connected to the drain of the transistor M2 , and the drain is electrically connected to the upper threshold voltage. From the above, it can be seen that the polarities of the voltage levels applied to the respective gates of transistors M1 and M2 are opposite. From the connection relationship between transistors M3 and M4 and transistors M1 and M2, it can be seen that transistors M1 and M2 have only one drain of the transistor at any time The lower limit threshold voltage AVDD is present, that is, the gate voltage level of only one transistor of the transistors M3 and M4 can turn on the corresponding transistor at any moment.

The buffer unit has an input terminal and an output terminal, and the input terminal is electrically connected to the drain of the transistor M1 (or the source of the transistor M3). Its output end is electrically connected to the input end of the complementary module. In the preferred embodiment shown in FIG. 1, the buffer unit includes a fifth transistor M5 and a sixth transistor M6, and the gate of the transistor M5 is electrically connected to the input terminal of the buffer unit and the gate of the transistor M6, and the gate of the transistor M5 The drain is electrically connected to the output terminal of the buffer unit and the drain of the transistor M6, and the source of the transistor M5 is connected to the lower threshold voltage AVDD and the source of the transistor M6 is connected to the upper threshold voltage VGH. Preferably, the gate of the transistor M5 can be set to be active at low level, and the gate of the transistor M6 can be set to be active at high level. Those of ordinary skill in the art should understand that the buffer unit in the figure only schematically enumerates the connection situation including two transistors with completely opposite gate control voltage levels, but the present invention is not limited thereto. For example, buffer A unit may also include other circuit connections.

In addition, the complementary module includes an NMOS transistor N1 and a PMOS transistor P1, wherein the gate of the transistor N1 is electrically connected to the gate of the transistor P1, the drain of the transistor N1 is electrically connected to the drain of the transistor P1, and the transistor N1 The source of the transistor P1 is electrically connected to the lower threshold voltage AVDD through the adjusting resistor RADJ, and the source of the transistor P1 is electrically connected to the upper threshold voltage VGH. In a specific embodiment, the complementary module can also be electrically connected to the output terminal of the buffer unit through another inverter, and the other inverter realizes normal operation through the voltages VGH and AVDD. It can be seen from FIG. 1 that the drain of the transistor N1 is electrically connected to the drain of the transistor P1 and a gate driver, and the gate driving signal required by the gate driver is generated by the output terminal of the complementary module.

FIG. 2 shows a schematic diagram of the circuit state of the voltage conversion unit and the buffer unit connected in series in the pulse modulation circuit of FIG. 1 when the input voltage is at a low level. It may be assumed that the input voltage VIN at this time is a low-level voltage VSS, and the principle of the main working part of the pulse modulation circuit is briefly described below: the gate of the transistor M1 is a low-level voltage, so M1 is in an off state; and the gate of the transistor M2 is High-level voltage, so M2 is in the conduction state, and node B presents the lower limit threshold voltage AVDD. Next, the gate of the transistor M3 is at a high level voltage, M3 is in a conduction state, and the node A presents an upper threshold voltage VGH. In this way, the input end of the buffer unit receives the upper limit threshold voltage VGH, the transistor M6 is turned on and the transistor M5 is turned off, so that the output end of the buffer unit outputs the lower limit threshold voltage AVDD to achieve the purpose of waveform clipping.

FIG. 3 shows a schematic diagram of the circuit state of the voltage conversion unit and the buffer unit connected in series in the pulse modulation circuit of FIG. 1 when the input level is high. Similarly, it may be assumed that the input voltage VIN at this time is a high-level voltage VDD. In this case, the working process of the main circuit part of the pulse modulation circuit is as follows: the gate of the transistor M1 is at a high-level voltage, so M1 is in the conduction state. The gate of the transistor M2 is in the low level voltage, so M2 is in the off state, and the node A presents the lower limit threshold voltage AVDD. Next, the gate of the transistor M4 is at a high level voltage, M4 is in the on state, the node B presents the upper limit threshold voltage VGH, so the transistor M3 is in the off state, and the drain of the transistor M1 is at the lower limit threshold voltage AVDD. In this way, the input end of the buffer unit receives the lower limit threshold voltage AVDD, the transistor M5 is turned on and the transistor M6 is turned off, so that the upper limit threshold voltage VGH is output through the output end of the buffer unit.

In one embodiment, the pulse modulation circuit further includes a capacitor, one end of the capacitor is electrically connected to the respective drains of the transistor N1 and the transistor P1 and the gate driver, and the other end of the capacitor is grounded.

By adopting the pulse modulation circuit of the present invention, the input voltage signal is converted by the voltage conversion unit and the buffer unit, which can ensure the normal operation of the NMOS transistor and the PMOS transistor in the complementary module, and solve the voltage problem caused by the unidirectional conduction of the diode on the current path of the driving signal. unstable problem. In addition, the converted voltage is electrically connected to the preset lower limit of the voltage output of the clipping circuit through an adjustment resistor, when the PMOS transistor is turned on, it can be charged to the upper threshold voltage through the PMOS transistor, and when the NMOS transistor is turned on, Discharge via the NMOS transistor and trim resistor for clipping to the lower threshold voltage.

Hereinbefore, specific embodiments of the present invention have been described with reference to the accompanying drawings. However, those skilled in the art can understand that without departing from the spirit and scope of the present invention, various changes and substitutions can be made to the specific embodiments of the present invention. These changes and substitutions all fall within the scope defined by the claims of the present invention.

Claims (8)

1. A pulse modulation circuit adapted to generate a gate drive signal, the pulse modulation circuit comprising: an input unit, configured to provide an input voltage; Voltage conversion unit, including: a first transistor, the gate of which is electrically connected to the input voltage, and the source of which is electrically connected to the first threshold voltage; a second transistor, the gate of which is electrically connected to the input voltage through an inverter, and the source of which is electrically connected to the first threshold voltage; a third transistor, the gate of which is electrically connected to the drain of the second transistor, the source of which is electrically connected to the drain of the first transistor, and the drain of which is electrically connected to the second threshold voltage; and a fourth transistor, the gate of which is electrically connected to the drain of the first transistor, the source of which is electrically connected to the drain of the second transistor, and the drain of which is electrically connected to the second threshold voltage; a buffer unit having an input terminal and an output terminal, the input terminal being electrically connected to the drain of the first transistor; and The complementary module includes an NMOS transistor and a PMOS transistor, the gates and drains of the NMOS transistor and the PMOS transistor are respectively connected correspondingly, and the source of the NMOS transistor is electrically connected to the first threshold voltage, and the source of the PMOS transistor is electrically connected to the second threshold voltage. 2. The pulse modulation circuit according to claim 1, wherein the buffer unit comprises a fifth transistor and a sixth transistor, wherein the gate of the fifth transistor is electrically connected to the input of the buffer unit terminal and the gate of the sixth transistor, the drain of the fifth transistor is electrically connected to the output terminal of the buffer unit and the drain of the sixth transistor, and the source of the fifth transistor is connected to to the second threshold voltage and the source of the sixth transistor is connected to the first threshold voltage. 3. The pulse modulation circuit according to claim 2, wherein the gate of the fifth transistor is active low, and the gate of the sixth transistor is active high. 4. The pulse modulation circuit as claimed in claim 1, wherein the complementary module is electrically connected to the output terminal of the buffer unit through another inverter. 5. The pulse modulation circuit as claimed in claim 1, wherein the drain of the NMOS transistor is electrically connected to the drain of the PMOS transistor and a gate driver to generate the gate driving signal. 6. The pulse modulation circuit according to claim 5, wherein when the input voltage from the input unit is low, the second transistor and the third transistor are turned on and the first transistor and the fourth transistor are turned on. When off, the output terminal of the buffer unit outputs the first threshold voltage. 7. The pulse modulation circuit according to claim 5, wherein when the input voltage from the input unit is at a high level, the first transistor and the fourth transistor are turned on and the second transistor and the third transistor are turned on. When off, the output terminal of the buffer unit outputs the second threshold voltage. 8. The pulse modulation circuit according to claim 5, wherein the pulse modulation circuit further comprises a capacitor, one end of the capacitor is electrically connected to the respective drains of the NMOS transistor and the PMOS transistor and the gate driver, the other end of the capacitor is grounded.

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