CN101931580A - System on chip adopting ARINC 659 rear panel data bus interface chip - Google Patents
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Abstract
The invention provides a system on a chip adopting an ARINC 659 rear panel data bus interface chip with high reliability and credibility and low cost in a novel communication mechanism. The system on the chip comprises a PCI (Peripheral Component Interconnect) bus interface module, a two-port RAM, a bus command list mapping storage, a command list self-loading functional module and an ARINC 659 bus protocol processing module. The invention ensures complete certainty of the communication.
Description
Technical field
The invention belongs to computer communication field, relate to a kind of ARINC 659 backboard data bus interface chip SOC (system on a chip).
Background technology
ARINC 659 backboard data/address buss (are called for short later on: the fault-tolerant universal serial bus that ARINC 659 buses) is based on two-two remaining configurations of Time Triggered framework, it supports the time subregion and the space partition zone of robust, is the key technology of synthesization modular avionics system.ARINC 659 buses come from the SAFEBus of Honeywell company
TMBus, 1993, SAFEBus
TMBus is adopted by US Airways Electronic Engineering Association (AEEC) and is become standard, issues the 659 core bus standards into ARINC.In the aeronautical data bus of using at present, the reliability that ARINC 659 buses provide, integrality and remaining grade are the highest.
ARINC 659 buses have been used for Airplane Information Management System (the Airplane InformationManagement System of Boeing 777, AIMS) system, VersatilIntegrated Avionics (VIA) system of aircrafts such as Boeing 717N, MD-10, KC-130 and the Highly Reliable LayeredSystem system that is used for space exploration of future generation are applied; ARINC 659 buses have broad application prospects in the Safety-Critical System of space flight, aviation, industrial control field.
Abroad, ARINC 659 buses are proprietary core technologies of Honeywell company, and Honeywell does not externally provide independent Bus Interface Chip and Related product.Domestic, as far back as last century end, minority scholar ARINC 659 buses that begin one's study are just arranged, but also do not have ripe total line products at present.Grasp ARINC 659 these international advanced technologies of backboard data/address bus, ARINC 659 Bus Interface Chips of development China independent intellectual property right (are called for short later on: interface chip), can partly fill up the domestic technique blank, the exploitation that can be China novel synthesization modularization safety-critical applying electronic system provides new approach and strong technical support.
Summary of the invention
In order to solve the above-mentioned technical problem that exists in the background technology, the invention provides a kind of reliability of new communication mechanisms, credible high and ARINC 659 backboard data bus interface chip SOC (system on a chip) with low cost of adopting.
Technical solution of the present invention is: the invention provides a kind of ARINC 659 backboard data bus interface chip SOC (system on a chip), its special character is: described ARINC 659 backboard data bus interface chip SOC (system on a chip) comprise pci bus interface module, dual port RAM, bus line command table mapping memory, command list bootstrap loading functional module and ARINC 659 bus protocol processing modules; Described command list bootstrap loading functional module electrically connects by bus line command table mapping memory and ARINC 659 bus protocol processing modules; Described pci bus interface module electrically connects by dual port RAM and ARINC 659 bus protocol processing modules; Described pci bus interface module and ARINC 659 bus protocol processing modules electrically connect.
Above-mentioned ARINC 659 bus protocol processing modules comprise clock generation unit, microprocessor, internal register group, data transmitter, data sink, clock-pulse generator, lock-out pulse detection check unit, initialization pulse detector, internal bus, interface bus and initialization timer; Described clock generation unit inserts microprocessing unit, internal bus and pci bus interface module respectively; Described microprocessor, internal register group, data transmitter, data sink, clock-pulse generator, lock-out pulse detection check unit, initialization pulse detector and initialization timer insert internal bus respectively; Described data transmitter inserts data sink; Described internal register group inserts the pci bus interface module by interface bus; Described dual port RAM, bus line command table mapping memory, command list bootstrap loading functional module insert internal bus respectively.
Above-mentioned lock-out pulse detection check unit comprises lock-out pulse detector and lock-out pulse checker; Described lock-out pulse detector inserts internal bus by the lock-out pulse checker.
Above-mentioned internal register group comprises version number's register, the full resolution time register, factor register between predetermined timestamp, the time limit register is waited in initialization synchronously, message gap register, master or reserve step length register, LRM module No. register, the interface chip status register, the Host Command register, the debugging control register, the debug time breakpoint register, OIER, interrupt status register, command address register, the frame switching enables or status register and frame switching or synchronization message accepting state register.
Above-mentioned initialization pulse detector comprises first counter and the first pulse pattern decision device, and described first counter and the first pulse pattern decision device electrically connect.
Above-mentioned lock-out pulse detector comprises second counter and the second pulse pattern decision device, and described second counter and the second pulse pattern decision device electrically connect.
Above-mentioned clock-pulse generator comprises the 3rd counter and variable connector, and described the 3rd counter and variable connector electrically connect.
Above-mentioned initialization timer comprises 1024 times of frequency dividers and anti-phase counter, and described 1024 times of frequency dividers and anti-phase counter electrically connect.
Above-mentioned microprocessor comprises and is used to finish to the reading of command list, and the pre-decode unit of the row decoding of going forward side by side, is used to deposit the pre-decode instruction buffer unit of four core instructions after the pre-decode and is used for being responsible for forming according to the pre-decode result transmitting-receiving control unit that transmitting-receiving is controlled to waveform; Described pre-decode unit, pre-decode instruction buffer unit and transmitting-receiving control unit electrically connect successively.
Advantage of the present invention is:
1, adopts advanced Time Triggered communication mechanism, guarantee the complete certainty of communication.The present invention develops the ARINC 659 Bus Interface Chip SOC (system on a chip) of independent intellectual property right, adopts advanced Time Triggered communication mechanism on the basis of realizing strong time synchronized, guarantees the complete certainty of communication.
2, high available, high credible, can tolerate to comprise " Byzantium's fault " almost various single fault patterns.The present invention develops the ARINC 659 Bus Interface Chip SOC (system on a chip) of independent intellectual property right, and data send and adopt two remainings, system applies is two-two remaining configurations, not only has high availability, has also guaranteed the high credible of transfer of data.
3, good reliability, with low cost.The present invention adopts SOC (System On Chip, SOC (system on a chip)) technology on ARINC 659 Bus Interface Chips, reduced peripheral components, has improved the reliability of application system, greatly reduces the development cost of application system.
4, fill up the domestic technique blank, the exploitation that can be China novel synthesization modularization safety-critical applying electronic system provides new approach and strong technical support.
Description of drawings
Fig. 1 is ARINC 659 backboard data bus interface chip system on chip structure schematic diagrames provided by the present invention;
Fig. 2 is the inner structural representation of forming of protocol processes functional module of the present invention;
Fig. 3 is that clock generation inside modules of the present invention is formed structural representation;
Fig. 4 is the control flow schematic diagram of transmitting-receiving control unit of the present invention;
Fig. 5 is a pulse generator structural representation of the present invention;
Fig. 6 is a pulse detector structural representation of the present invention;
Fig. 7 is an initialization pulse detector member structural representation of the present invention;
Fig. 8 is that the counter structure schematic diagram is waited in initialization of the present invention;
Fig. 9 is the internal structure schematic diagram of Data Receiving of the present invention unit;
Figure 10 is the sequential schematic diagram of over-sampling circuit of the present invention.
Embodiment
Referring to Fig. 1, the invention provides a kind of ARINC 659 backboard data bus interface chip SOC (system on a chip), mapping RAM), command list bootstrap loading functional module and protocol processes functional module ARINC 659 core bus interface chips (be called for short: interface chip, BIU) interface chip has the SOC (system on a chip) of Harvard's framework dedicated frame descriptive language (FDL) microcommand processor in being, BIU inside mainly comprises five parts: pci bus interface module, dual port RAM, bus line command table mapping memory (are called for short:; Command list bootstrap loading functional module electrically connects by bus line command table mapping memory and ARINC 659 bus protocol processing modules; The pci bus interface module electrically connects by dual port RAM and ARINC 659 bus protocol processing modules; Pci bus interface module and ARINC 659 bus protocol processing modules electrically connect.
The interface chip host interface adopts the pci bus interface of standard, interface is except that not supporting accord with PCI 2.2 electrical codes the hot plug, pci bus interface mainly is responsible for the read-write and the external interrupt request responding of docking port chip internal dual port RAM, internal register with from pattern mode operational module.
When interface chip powered on, internal command table bootstrap loading functional module was moved the command list in the outside FLASH memory among the inner mapping RAM automatically.Command list bootstrap loading module produces address sense data from outside FLASH memory automatically, and writes among the mapping RAM, and command list bootstrap loading process does not need the main frame intervention.After command list loaded and finishes, interface chip carried out operations such as initialization internal register, order pre-decode, preparation synchronously.The content of outside FLASH memory will be revised by TM bus (or substitute with JTAG).
Mapping RAM in the interface chip is the table demanded storage parts of interface chip, and that deposits interface chip is provided with parameter and bus scheduling control command, and interface chip realizes that by carrying out this order each LRM sequential is in accordance with regulations carried out data communication on ARINC 659 buses.Interface chip can only read the content of mapping RAM.
Dual port RAM in the interface chip is as the medium of information exchange between subsystem main frame and the interface chip.Busy (BUSY) logic of dual port RAM provides the mechanism of the same unit of a kind of exclusive reference memory.When visit is initiated to the same unit of dual port RAM simultaneously in two ends, only allow port A (or port B) reference to storage, and the BUSY signal of port B (or port A) can be effectively, the equipment dual port RAM of informing request access port B (or port A) is just busy, equipment will be hung up the read-write operation to port B (or port A), when the write operation to port A (or port B) finished, it is invalid that the BUSY signal of port B (or port A) will become, and can carry out read-write operation this moment to port B (or port A).Two ports of dual port RAM have separately independently control, address and I/O signal, and any unit can both be independently by two port access.
The protocol processes functional module comprise Harvard's framework special-purpose micro-order processor, realize that time synchronized, table command execution, Data Receiving and transmission, data are temporary, interruption and functions such as abnormality processing and report.The pci bus interface module is realized by the pci interface IP kernel of purchasing and some internal interface decoding logics.Dual port RAM and mapping RAM are realized by the IP kernel of purchasing.
Referring to Fig. 2, protocol processes functional module internal clocking generating unit, microprocessor, internal register group, data transmitter, data sink, clock-pulse generator, lock-out pulse detection check unit, initialization pulse detector, internal bus, interface bus and initialization timer; Clock generation unit inserts microprocessing unit, internal bus and pci bus interface module respectively; Microprocessor, internal register group, data transmitter, data sink, clock-pulse generator, lock-out pulse detection check unit, initialization pulse detector and initialization timer insert internal bus respectively; Data transmitter inserts data sink; The internal register group inserts the pci bus interface module by interface bus; Dual port RAM, bus line command table mapping memory, command list bootstrap loading functional module insert internal bus respectively.Wherein, the lock-out pulse detector inserts internal bus by the lock-out pulse checker.Microprocessor is transmitted data by data transmitter and clock-pulse generator by internal bus after the information that reception data sink, initialization timer, lock-out pulse detector, lock-out pulse checker and initialization pulse detector are sent by internal bus.
Referring to Fig. 3, the interface chip internal clocking produces by its inner PLL frequency multiplication, and a PLL of external crystal produces the frequency output of 240MHz, will be as the clock of weak point/long lock-out pulse testing circuit; The frequency of 240MHz is 60MHz behind 1/4 frequency divider frequency division of band clear terminal, as bus clock.Another PLL of external crystal produces the frequency output of 120MHz, is used for host interface.
Chip internal FDL microcommand processor is a processor of intermittently carrying out, when microprocessor begins at current total linear window, begin to handle the instruction of next total linear window correspondence, simultaneously send control signal, finish corresponding operation according to the current window order request, be in halted state afterwards, wait for next window commencing signal after microprocessor start working again.
The microcommand processor can be carried out all instruction and self-defining INT interrupt instructions of " ARINC 659 backboard data/address bus standards-1993 " regulation.
The microcommand processor is made up of pre-decode unit, pre-decode instruction buffer unit, transmitting-receiving control unit.The pre-decode unit is mainly finished command list is read the row decoding of going forward side by side.This unit is controlled by state machine.The pre-decode instruction buffer unit is a register file, is used to deposit four core instructions after the pre-decode.The transmitting-receiving control unit is responsible for according to the pre-decode result waveform transmitting-receiving being controlled, and is used for control data transmitting element and Data Receiving unit to receive or send the waveform of appointment.
The transmitting-receiving control unit is the actuator of microcommand processor, also be its most crucial parts, the transmitting-receiving control unit is the state machine of autonomous Design, and each state and the switch condition thereof of this state machine are as shown in table 1 below, and transmitting-receiving control unit state machine workflow is referring to Fig. 4.
The status list of table 1 transmitting-receiving control unit
In table 1:
The GAP--transmission data mode of reading to give an order;
S_GAP1--reads to give an order and sends first word;
The S_GAP2--data status word is effective;
First word of S_GAP_END--is effective;
S_GAP_WAIT--o'clock enters this state in GAP＞2.
The interface chip internal register accounts for the main frame external reference address space of 0X5F * 32bit, and the definition of each register is as shown in table 2, and the reference address of each register is: the offset address in base address+0x00080000+ table 2.The internal register group comprises version number's register, the full resolution time register, factor register between predetermined timestamp, the time limit register is waited in initialization synchronously, message gap register, master or reserve step length register, LRM module No. register, the interface chip status register, the Host Command register, the debugging control register, the debug time breakpoint register, OIER, interrupt status register, command address register, the frame switching enables or status register and frame switching or synchronization message accepting state register.
Table 2 interface chip internal register gathers
| Initial address | Title | Bit wide | Quantity | Total bit | Read-write type | Remarks |
| 0-7? | Version number's register | 64? | 1? | 64? | R? | ? |
| 8-F? | The full resolution time register | 64? | 1? | 64? | R? | ? |
| 10-13? | Factor register between |
32? | 1? | 32? | R? | ? |
| 14-17? | The time limit register is waited in initialization synchronously | 32? | 1? | 32? | R? | ? |
| 18-1B? | Message gap register | 32? | 1? | 32? | R? | GAP? |
| 1C-1F? | Master/reserve |
32? | 1? | 32? | R? | Δ? |
| 20-23? | LRM |
32? | 1? | 5? | R? | Only with low 5 |
| 24-27? | The interface |
32? | 1? | 32? | R? | ? |
| 28-2B? | The Host Command register | 32? | 1? | 32? | R/W? | ? |
| 2C-2F? | The debugging control register | 32? | 1? | 32? | R/W? | Debugging mode only |
| 30-37? | The debug time breakpoint register | 64? | 1? | 64? | R/W? | Debugging mode only |
| 38-3B? | |
32? | 1? | 32? | R/W? | ? |
| 3C-3F? | Interrupt status register | 32? | 1? | 32? | R/W? | ? |
| 40-43? | Command address register | 32? | 1? | 16? | R? | Only with low 16 |
| 44-47? | Frame switch enable status register | 32? | 1? | 32? | R/W? | ? |
| 48-4B? | Frame switch synchronization message accepting |
32? | 1? | 32? | R? | ? |
Data transmission blocks is one group of shift register, and it sends to bus by turn with data under bus clock drives.
Referring to Fig. 5, pulse generator is made up of the 3rd counter and variable connector, and the 3rd counter externally excitation of start-up control signal produces 4 long low pulse signals down.Variable connector is delivered to this pulse signal respectively on CLOCK, DATA0, the DATA1 circuit according to the pulse pattern control signal of outside.The control of the pulse pattern that pulse generator produces is as shown in table 3 below.
The pulse of table 3 pulse generator produces the type control table
| |
|
Pulse pattern |
| ?0? | 0? | Change pulse at the beginning |
| ?0? | 1? | Short lock-out pulse |
| ?1? | 0? | Long lock-out pulse |
| ?1? | 1? | The pulse of frame debug suspend |
2 pulse signal generators are arranged in each interface chip, correspond respectively to A, B bus.
Pulse generator is made up of the 3rd counter and variable connector.The message sink register is received the validity of data by an indication.Data are to relatively being used for to then carrying out following data relatively: Ax=Ay, Ax=By, Bx=Ay, Bx=By.In case BIU determines whether complete word and has received and finished data relatively that it will determine the validity of each digit order number according to " the ARINC 659 backboard data/address bus standards-1993 " rule that provides.If the multi-path digital position is effective, will from the data bit on effective road, select arbitrarily.If there is not the active data road, the value of the data bit of selection is arbitrarily.If from the data bit on all buses is good, then the data bit of Xuan Zeing is faultless.If from the data bit on all buses is bad, then the data bit of Xuan Zeing is uncorrectable.If some data bit is that effectively some is not that then the data bit of Xuan Zeing is correctable.
Referring to Fig. 6, pulse detector is made up of second counter and the second pulse pattern decision device, second counter is if can (comprise 4 times) more than 4 times by continuous counter, just confirming has lock-out pulse to send, and the second pulse pattern decision device went out the lock-out pulse type and exported index signal according to the level detection of DATA0 line and DATA1 line immediately this moment.Second counter is if can (comprise 8 times) more than 8 times by continuous counter, and the output low pulse signal is to pulse generator, and stop pulse sends.
4 pulse detectors are arranged in the interface chip, correspond respectively to 4 buses, the second pulse pattern checker is according to the index signal (three unlike signals) of the pulse detector output of 4 bus correspondences, judge whether to have at least one group of index signal effective at AxAy, AxBy, BxAy, BxBy, and then in not collinear output pulse marker pulse type.
Referring to Fig. 7, the initialization pulse detector is made up of first counter and the first pulse pattern decision device, first counter is if can (comprise 32 times) more than 32 times by continuous counter, just confirming has lock-out pulse to send, this moment, whether the first pulse pattern decision device was initialization pulse according to the electrical level judging of CLOCK line and DATA1 line immediately, and the output index signal.
4 initialization pulse detectors are arranged among the BIU, correspond respectively to 4 buses.
Referring to Fig. 8, initialization wait counter is made up of 1024 times of frequency dividers and an anti-phase counter.When BIU enters asynchronous regime or receives synchronization pulse, anti-phase counter heavy duty initial value starts the frequency divider sum counter simultaneously starts working, and Counter Value is reduced to 0, exports a pulse signal initialization BIU.BIU one enters synchronous regime, and the frequency divider sum counter quits work at once.
Referring to Fig. 9, the reception of single expection basic waveform is responsible in the Data Receiving unit, will compare with the expection waveform after finishing receiving, and returns accepting state.
In receiving course,, adopt 3 algorithms of averaging to carry out the burr filtration treatment to clock line and data line signal earlier in order to improve reliability.Signal after filtering is carried out again the over-sampling of 8 frequencys multiplication.The sequential of over-sampling circuit is referring to shown in Figure 10, use the clock signal of the certain umber of beats of register-stored, when the rising edge that detects clock, be that sample8 1 claps afterwards, sample3, sample4 among the use figure, sample5, sample6, sample7 totally 5 sampled points votings produce output signals, judge the signal value that samples.Data on the bus have been carried out the stability that signals collecting is guaranteed in the sampling of 8 frequencys multiplication.
The another one function of Data Receiving unit is that the data bit that samples is decoded, compares, judges that validity splices output then.The validity of data bit is according to setting, according to the validity table and the integrality list deciding of " ARINC 659 backboard data/address bus standards-1993 ".
Claims (9)
1. ARINC 659 backboard data bus interface chip SOC (system on a chip), it is characterized in that: described ARINC 659 backboard data bus interface chip SOC (system on a chip) comprise pci bus interface module, dual port RAM, bus line command table mapping memory, command list bootstrap loading functional module and ARINC 659 bus protocol processing modules; Described command list bootstrap loading functional module electrically connects by bus line command table mapping memory and ARINC 659 bus protocol processing modules; Described pci bus interface module electrically connects by dual port RAM and ARINC 659 bus protocol processing modules; Described PCL bus interface module and ARINC 659 bus protocol processing modules electrically connect.
2. ARINC 659 backboard data bus interface chip SOC (system on a chip) according to claim 1, it is characterized in that: described ARINC 659 bus protocol processing modules comprise clock generation unit, microprocessor, internal register group, data transmitter, data sink, clock-pulse generator, lock-out pulse detection check unit, initialization pulse detector, internal bus, interface bus and initialization timer; Described clock generation unit inserts microprocessing unit, internal bus and pci bus interface module respectively; Described microprocessor, internal register group, data transmitter, data sink, clock-pulse generator, lock-out pulse detection check unit, initialization pulse detector and initialization timer insert internal bus respectively; Described data transmitter inserts data sink; Described internal register group inserts the pci bus interface module by interface bus; Described dual port RAM, bus line command table mapping memory, command list bootstrap loading functional module insert internal bus respectively.
3. ARINC 659 backboard data bus interface chip SOC (system on a chip) according to claim 2, it is characterized in that: described lock-out pulse detection check unit comprises lock-out pulse detector and lock-out pulse checker; Described lock-out pulse detector inserts internal bus by the lock-out pulse checker.
4. ARINC 659 backboard data bus interface chip SOC (system on a chip) according to claim 3, it is characterized in that: described internal register group comprises version number's register, the full resolution time register, factor register between predetermined timestamp, the time limit register is waited in initialization synchronously, message gap register, master or reserve step length register, LRM module No. register, the interface chip status register, the Host Command register, the debugging control register, the debug time breakpoint register, OIER, interrupt status register, command address register, the frame switching enables or status register and frame switching or synchronization message accepting state register.
5. according to claim 2 or 3 or 4 described ARINC 659 backboard data bus interface chip SOC (system on a chip), it is characterized in that: described initialization pulse detector comprises first counter and the first pulse pattern decision device, and described first counter and the first pulse pattern decision device electrically connect.
6. ARINC 659 backboard data bus interface chip SOC (system on a chip) according to claim 5, it is characterized in that: described lock-out pulse detector comprises second counter and the second pulse pattern decision device, and described second counter and the second pulse pattern decision device electrically connect.
7. ARINC 659 backboard data bus interface chip SOC (system on a chip) according to claim 5, it is characterized in that: described clock-pulse generator comprises the 3rd counter and variable connector, described the 3rd counter and variable connector electrically connect.
8. ARINC 659 backboard data bus interface chip SOC (system on a chip) according to claim 5, it is characterized in that: described initialization timer comprises 1024 times of frequency dividers and anti-phase counter, described 1024 times of frequency dividers and anti-phase counter electrically connect.
9. ARINC 659 backboard data bus interface chip SOC (system on a chip) according to claim 5, it is characterized in that: described microprocessor comprises and is used to finish to the reading of command list, and the pre-decode unit of the row decoding of going forward side by side, is used to deposit the pre-decode instruction buffer unit of four core instructions after the pre-decode and is used for being responsible for forming according to the pre-decode result transmitting-receiving control unit that transmitting-receiving is controlled to waveform; Described pre-decode unit, pre-decode instruction buffer unit and transmitting-receiving control unit electrically connect successively.
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