CN101924077B - Manufacturing method for reducing area of SONOS storage unit - Google Patents
Manufacturing method for reducing area of SONOS storage unit Download PDFInfo
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- CN101924077B CN101924077B CN2009100574240A CN200910057424A CN101924077B CN 101924077 B CN101924077 B CN 101924077B CN 2009100574240 A CN2009100574240 A CN 2009100574240A CN 200910057424 A CN200910057424 A CN 200910057424A CN 101924077 B CN101924077 B CN 101924077B
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 19
- 238000003860 storage Methods 0.000 title abstract description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 80
- 229910052681 coesite Inorganic materials 0.000 claims abstract description 40
- 229910052906 cristobalite Inorganic materials 0.000 claims abstract description 40
- 239000000377 silicon dioxide Substances 0.000 claims abstract description 40
- 235000012239 silicon dioxide Nutrition 0.000 claims abstract description 40
- 229910052682 stishovite Inorganic materials 0.000 claims abstract description 40
- 229910052905 tridymite Inorganic materials 0.000 claims abstract description 40
- 239000010410 layer Substances 0.000 claims abstract description 34
- 238000001039 wet etching Methods 0.000 claims abstract description 21
- 238000005530 etching Methods 0.000 claims abstract description 16
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 16
- 239000010703 silicon Substances 0.000 claims abstract description 16
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 15
- 238000010438 heat treatment Methods 0.000 claims abstract description 14
- 238000001259 photo etching Methods 0.000 claims abstract description 12
- 238000000034 method Methods 0.000 claims abstract description 10
- 239000011241 protective layer Substances 0.000 claims abstract description 10
- 239000000758 substrate Substances 0.000 claims abstract description 9
- 238000001312 dry etching Methods 0.000 claims abstract description 5
- 229920002120 photoresistant polymer Polymers 0.000 claims description 27
- 150000004767 nitrides Chemical class 0.000 claims description 15
- 230000004888 barrier function Effects 0.000 claims description 11
- 239000012528 membrane Substances 0.000 claims description 8
- 239000000463 material Substances 0.000 claims description 5
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 4
- 230000015572 biosynthetic process Effects 0.000 claims description 4
- 230000008021 deposition Effects 0.000 claims description 4
- 230000012010 growth Effects 0.000 claims description 4
- 239000001301 oxygen Substances 0.000 claims description 4
- 229910052760 oxygen Inorganic materials 0.000 claims description 4
- 239000000126 substance Substances 0.000 claims description 4
- 230000003068 static effect Effects 0.000 claims description 3
- 230000007773 growth pattern Effects 0.000 claims description 2
- 235000014347 soups Nutrition 0.000 claims description 2
- 238000000151 deposition Methods 0.000 abstract description 4
- 238000009740 moulding (composite fabrication) Methods 0.000 abstract 1
- 235000012431 wafers Nutrition 0.000 abstract 1
- 238000005516 engineering process Methods 0.000 description 8
- 238000001228 spectrum Methods 0.000 description 4
- 235000019593 adhesiveness Nutrition 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- ISQINHMJILFLAQ-UHFFFAOYSA-N argon hydrofluoride Chemical compound F.[Ar] ISQINHMJILFLAQ-UHFFFAOYSA-N 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000002146 bilateral effect Effects 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 230000008595 infiltration Effects 0.000 description 1
- 238000001764 infiltration Methods 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 230000014759 maintenance of location Effects 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 238000004017 vitrification Methods 0.000 description 1
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Abstract
The invention discloses a manufacturing method for reducing an area of an SONOS storage unit, comprising the following steps: (1) completely depositing SiO2 on a silicon substrate; (2), removing SiO2 in an SONOS pipe zone by photoetching and etching, and forming a SiO2 protective layer in a common transistor zone; (3) completely depositing an ONO three-layer film; (4) protecting the ONO zone of the SONO pipe by photoetching, and forming a SiO2 protective layer on the zone; (5) removing ON in the common transistor zone by dry etching; (6) carrying out heating on silicon wafers; (7) removing the rest of SiO2 in the common transistor zone by wet etching; and (8) forming a gate oxide and a grid electrode in the follow-up steps. The method can reduce horizontal etching of SiO2 on the upper layer of the ONO structure of the SONO storage in the wet etching, so that the distance between the SONOS pipe and the common transistor is shortened, thereby reaching the purpose of reducing the area.
Description
Technical field
The invention belongs to the technology integrating method of semiconductor device, relate in particular to a kind of manufacturing approach of the SONOS of dwindling memory unit area.
Background technology
Traditional SONOS (silicon-oxide-nitride--oxide-silicon) memory by an ONO (Oxide-Nitride-Oxide, oxide-nitride thing-oxide) for the transistor of gate insulator and common be that the transistor of insulating barrier is formed a memory cell (see figure 1) with SiO2.The basic principle of SONOS pipe is that the SiO2 that lower floor contacts with active area is a tunnel oxide 4, and very thin thickness is for 0.13um (micron) technology; Operating voltage+/-15V in, its thickness is approximately 15～25 dusts, under certain vertical voltage; Electronics in the active area can pass this tunnel oxide 4 and get into nitride layer 3; And be stored, under reverse voltage, the electronics of nitride layer 3 storages can get into active area through this tunnel oxide 4 on the contrary.Middle nitride layer 3 is a capacitor layers, is used for storing the electronics of tunnelling.The oxide on upper strata (oxide) is an insulating oxide 2, guarantees that the electronics in the nitride layer 3 can not get into grid, and the electric current on the grid can not get into nitride layer 3.
As shown in Figure 4, the manufacturing process flow of traditional SONOS memory is:
1) on silicon substrate 5, deposits SiO2 comprehensively, form SiO2 layer 4, see Fig. 4 A;
2) chemical wet etching is removed the SiO2 in territory, SONOS area under control, and (being the normal transistor zone) forms the protective layer (antireflection barrier layer 7 and photoresist 8) of SiO2 in other zones, sees Fig. 4 B;
3) deposit the ONO trilamellar membrane, from top to bottom be insulating oxide 2 comprehensively, nitride layer 3, and tunnel oxide 4 is seen Fig. 4 C;
4) the ONO zone of photoetching protection SONOS pipe, the protective layer of formation SiO2 (antireflection barrier layer 7 and photoresist 8) on this zone;
5) dry etching is removed the ON (insulating oxide 2 and nitride layer 3) in normal transistor zone, sees Fig. 4 D;
6) wet etching is removed the remaining SiO2 in normal transistor zone, sees Fig. 4 E;
7) subsequent step forms grid oxygen and grid, sees Fig. 4 F and Fig. 4 G.
In step 6) because the isotropism principle of wet etching; The insulating oxide 2 in SONOS zone since with far short of what is expected than nitride layer 3 and tunnel oxide 4 of anti-reflecting layer 7 or photoresist 8 adhesivenesses, can cause insulating oxide 2 to produce lateral etchings, and then when forming grid; The grid of SONOS pipe must form in insulating oxide 2 residual zones; Because insulating oxide 2 is an insulating barrier, if there is not this layer, device can directly puncture inefficacy; Therefore receive the restriction of insulating oxide 2 lateral etchings, the minimum range between SONOS pipe and the normal transistor receives process technology limit.
Summary of the invention
The technical problem that the present invention will solve provides a kind of manufacturing approach of the SONOS of dwindling memory unit area; This method can reduce the lateral etching of upper strata SiO2 in wet etching of SONOS memory ONO structure; Spacing between SONOS pipe and the normal transistor can be dwindled, thereby reach the purpose of dwindling area.
For solving the problems of the technologies described above, the present invention provides a kind of manufacturing approach of the SONOS of dwindling memory unit area, comprises the steps:
1) on silicon substrate, deposits SiO2 comprehensively;
2) chemical wet etching is removed the SiO2 in territory, SONOS area under control, forms the protective layer of SiO2 in the normal transistor zone;
3) deposit the ONO trilamellar membrane comprehensively;
4) the ONO zone of photoetching protection SONOS pipe, the protective layer of formation SiO2 on this zone;
5) dry etching is removed the ON in normal transistor zone;
6) silicon chip is heated, photoresist is flowed along sidewall cover the upper strata oxide of ONO trilamellar membrane;
7) wet etching is removed the remaining SiO2 in normal transistor zone;
8) subsequent step forms grid oxygen and grid.
Temperature in the step 6) is 80～160 ℃, and the time is 10s～240s.
The mode of heating that step 6) heats silicon chip is that Direct Contact Heating or infrared ray heat at a distance, rotation or static during the silicon chip heating.
Step 2) and the employed material of the photoetching process in the step 4) be G-Line, I-line, I-line+I-Line BARC, KrF+KrF BARC or ArF+ArF BARC.
Step 7) adopts the HF wet etching to remove SiO2.
Compare with prior art; The present invention has following beneficial effect: the present invention utilizes photoresist heat flow technology; Before the wet etching of SiO2, carry out a heat flow, can reduce the lateral etching of upper strata SiO2 in wet etching of SONOS memory ONO structure; Spacing between SONOS pipe and the normal transistor can be dwindled, thereby reach the purpose of dwindling the SONOS memory unit area.
Description of drawings
Fig. 1 is the memory cell sketch map of existing SONOS memory;
Fig. 2 is the memory cell sketch map of SONOS memory of the present invention;
Fig. 3 is the sketch map of step 6) heat flow technology among the present invention.
Fig. 4 is the manufacturing process flow diagram of existing SONOS memory;
Fig. 5 is the manufacturing process flow diagram of SONOS memory of the present invention.
Wherein, 1 grid for the SONOS pipe, 2 is insulating oxide, and 3 is nitride layer, and 4 is tunnel oxide, and 5 is silicon substrate, and 6 is the grid of common selection pipe, and 7 is antireflection barrier layer (BRAC), and 8 is photoresist, L is the spacing of SONOS pipe and common selection pipe.
Embodiment
Below in conjunction with accompanying drawing and embodiment the present invention is done further detailed explanation.
As shown in Figure 5, the present invention provides a kind of manufacturing approach of SONOS memory, and its processing step is:
1) on silicon substrate 5, deposits SiO2 comprehensively, form SiO2 layer 4, see Fig. 5 A; With interior device, its thickness is 50～250 dusts for operating voltage 15V, and its growth pattern is generally heat growth or PVD, the CVD deposition.
2) chemical wet etching is removed the SiO2 in territory, SONOS area under control, and (being the normal transistor zone) forms the protective layer (antireflection barrier layer 8 and photoresist 7) of SiO2 in other zones, sees Fig. 5 B; The general wet etching that contains the HF soup that adopts of etching.
3) deposit ONO trilamellar membrane (Oxide-Nitride-Oxide, insulating oxide 2-nitride layer 3-tunnel oxide 4) comprehensively, see Fig. 5 C; With interior device, thickness is that tunnel oxide 4 is 10～100 dusts usually for operating voltage 15V, and nitride layer 3 is 40～350 dusts, and insulating oxide 2 is 50～250 dusts, adopts heat growth or PVD usually, the CVD deposition.
4) the ONO zone of photoetching protection SONOS pipe, the protective layer of formation SiO2 (antireflection barrier layer 8 and photoresist 7) on this zone;
5) dry etching is removed the ON (insulating oxide 2 and nitride layer 3) in normal transistor zone, sees shown in Fig. 5 D; Described have high selectivity to the substrate oxide layer when being dry-etched in nitride layer 3 etchings, guarantees can not etch into substrate.
6) silicon chip is heated, photoresist 8 is flowed along sidewall cover the insulating oxide 2 of ONO trilamellar membrane, see Fig. 5 E;
7) wet etching is removed the remaining SiO2 in normal transistor zone, adopts HF etching SiO2 as this step 1, can not produce reaction with photoresist 8, sees Fig. 5 F;
8) subsequent step forms grid oxygen and grid, sees Fig. 5 G and Fig. 5 H.
Wherein, step 2), the employed material of photoetching process 4) is a G-Line (G line; Corresponding spectrum 436nm), I-line (I line, corresponding spectrum 365nm); I-line photoresist+I-LineBARC (antireflection barrier layer), KrF (KrF, corresponding spectrum 248nm)+KrF BARC; Or ArF (argon fluoride, corresponding spectrum 193nm)+ArF BARC.For G-line, I-line is because the side direction etching of HF is less in wet etching; Generally do not adopt BARC; But also can use BARC to strengthen adhesiveness,, need to use BARC usually for KrF and ArF; Only if employed photoresist material is very strong or very strong with the substrate binding ability for the side direction etching resistance of HF, horizontal infiltration does not take place.Its concrete etching resistance and adhering criterion are lateral etching amount＜vertical etch amount that wet method produces.
Wherein, the concrete process conditions of step 6) heat flow step are that temperature is 70 ℃-250 ℃, and be 10s-600s heating time, and preferably, temperature is 80～160 ℃, and the time is 60s～120s.Mode of heating can be Direct Contact Heating, the remote heating of infrared ray etc., and silicon chip can rotate when heating or be static.
The photoresist heat flow that step 6) adopts is the process below a kind of 0.13um of being widely used in (micron); Its principle is after photoetching is accomplished; Photoresist is heated, and the vitrification point that makes it to surpass photoresist produces lateral flow, dwindles the size after the photoetching.
As shown in Figure 3, solid line is the photoresist after the common photoetching among Fig. 3 A, after heating surpasses uniform temperature; Photoresist is from the solid-state solid-liquid coexistence attitude that is converted into; Take place to flow, this moment, photoresist was a dotted line, and this moment, monolateral or bilateral change in size was called as the change in size that heat flow produces.This change in size and material itself, the temperature of heating, mode and time are closely related; What Fig. 3 B represented is the sketch map with heating-up temperature heat flow change in size.
The present invention utilizes photoresist heat flow technology, before the wet etching of SiO2, carries out a heat flow, photoresist is flowed along sidewall cover the upper strata oxide layer, in follow-up wet etching, generally adopts HF etching SiO2, can not produce reaction with photoresist.Therefore can protect the upper strata SiO2 of ONO structure can not produce lateral etching, make the spacing L between SONOS pipe and the normal transistor can dwindle (seeing Fig. 1 and Fig. 2), thereby reach the purpose of dwindling the SONOS memory unit area.
Claims (9)
1. a manufacturing approach of dwindling the SONOS memory unit area is characterized in that, comprises the steps:
1) on silicon substrate, deposits SiO2 comprehensively;
2) chemical wet etching is removed the SiO2 in territory, SONOS area under control, forms the protective layer of SiO2 in the normal transistor zone;
3) deposit the ONO trilamellar membrane, said ONO trilamellar membrane is followed successively by insulating oxide, nitride layer and tunnel oxide from top to bottom comprehensively;
4) the ONO zone of photoetching protection SONOS pipe, the protective layer of formation SiO2 on this zone;
5) dry etching is removed the insulating oxide and the nitride layer in normal transistor zone;
6) silicon chip is heated, photoresist is flowed along sidewall cover the insulating oxide of ONO trilamellar membrane;
7) wet etching is removed the remaining SiO2 in normal transistor zone;
8) subsequent step forms grid oxygen and grid.
2. manufacturing approach of dwindling the SONOS memory unit area according to claim 1 is characterized in that, in the step 1), with interior device, the thickness of said SiO2 is 50～250 dusts for operating voltage 15V, and its growth pattern is heat growth or PVD, the CVD deposition.
3. manufacturing approach of dwindling the SONOS memory unit area according to claim 1 is characterized in that step 2) in etching adopt the wet etching contain the HF soup.
4. manufacturing approach of dwindling the SONOS memory unit area according to claim 1 is characterized in that, in the step 3); For operating voltage 15V with interior device; Said tunnel oxide is 10～100 dusts, and said nitride layer is 40～350 dusts, and said insulating oxide is 50～250 dusts; This step adopts heat growth or PVD, the CVD deposition.
5. manufacturing approach of dwindling the SONOS memory unit area according to claim 1 is characterized in that, the temperature in the step 6) is 70～250 ℃, and the time is 10s～600s.
6. manufacturing approach of dwindling the SONOS memory unit area according to claim 5 is characterized in that, the temperature in the step 6) is 80～160 ℃, and the time is 60s～120s.
7. manufacturing approach of dwindling the SONOS memory unit area according to claim 1 is characterized in that, the mode of heating that step 6) heats silicon chip is that Direct Contact Heating or infrared ray heat at a distance, rotation or static during the silicon chip heating.
8. manufacturing approach of dwindling the SONOS memory unit area according to claim 1; It is characterized in that; Step 2) and the employed material of the photoetching process in the step 4) be G line photoresist, I line photoresist, I line photoresist+I line antireflection barrier layer; KrF photoresist+KrF antireflection barrier layer, or ArF photoresist+ArF antireflection barrier layer.
9. manufacturing approach of dwindling the SONOS memory unit area according to claim 1 is characterized in that, step 7) adopts the HF wet etching to remove SiO2.
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| CN2009100574240A CN101924077B (en) | 2009-06-17 | 2009-06-17 | Manufacturing method for reducing area of SONOS storage unit |
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| CN2009100574240A CN101924077B (en) | 2009-06-17 | 2009-06-17 | Manufacturing method for reducing area of SONOS storage unit |
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| CN104810264B (en) * | 2014-01-26 | 2017-12-01 | 国家电网公司 | A kind of SiC terminal structure preparation methods based on ONO structure |
| CN108831888B (en) * | 2018-06-13 | 2021-01-29 | 上海华力微电子有限公司 | SONOS memory and manufacturing method thereof |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6878642B1 (en) * | 2000-10-06 | 2005-04-12 | Taiwan Semiconductor Manufacturing Company | Method to improve passivation openings by reflow of photoresist to eliminate tape residue |
| CN1877818A (en) * | 2005-06-07 | 2006-12-13 | 东部电子有限公司 | Method for fabricating CMOS image sensor |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6878642B1 (en) * | 2000-10-06 | 2005-04-12 | Taiwan Semiconductor Manufacturing Company | Method to improve passivation openings by reflow of photoresist to eliminate tape residue |
| CN1877818A (en) * | 2005-06-07 | 2006-12-13 | 东部电子有限公司 | Method for fabricating CMOS image sensor |
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Owner name: SHANGHAI HUAHONG GRACE SEMICONDUCTOR MANUFACTURING Free format text: FORMER OWNER: HUAHONG NEC ELECTRONICS CO LTD, SHANGHAI Effective date: 20140110 |
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Effective date of registration: 20140110 Address after: 201203 Shanghai city Zuchongzhi road Pudong New Area Zhangjiang hi tech Park No. 1399 Patentee after: Shanghai Huahong Grace Semiconductor Manufacturing Corporation Address before: 201206, Shanghai, Pudong New Area, Sichuan Road, No. 1188 Bridge Patentee before: Shanghai Huahong NEC Electronics Co., Ltd. |