CN101923583B

CN101923583B - Method for modifying OTP memory layout into ROM memory layout

Info

Publication number: CN101923583B
Application number: CN 200910099488
Authority: CN
Inventors: 赵启永; 陈焱; 何群; 周炯
Original assignee: Hangzhou Silan Integrated Circuit Co Ltd
Current assignee: Hangzhou Silan Integrated Circuit Co Ltd
Priority date: 2009-06-10
Filing date: 2009-06-10
Publication date: 2013-01-16
Anticipated expiration: 2029-06-10
Also published as: CN101923583A

Abstract

The invention provides a method for modifying an OTP memory layout into a ROM memory layout, which is characterized in that (1) the OTP memory layout comprises an N-type active region, a polycrystal, a lead hole for connecting the N-type active region and polycrystal with a first aluminum layer (first aluminum), first aluminum, a through hole for connecting the first aluminum with a second aluminum layer (second aluminum), and second aluminum; (2) when the OTP memory layout is modified into the ROM memory layout, the memory circuit and the polycrystal of the first NMOS transistor are firstly deleted; (3) and if the grid electrode and the source electrode of the memory circuit is required to be burned, the N-type active region of the source electrode of the memory circuit is connected to the first aluminum of the memory circuit through the lead hole in the ROM memory layout. On the basis of one OTP layout, the invention only modifies parts of the layers so as to modify the OTP layout into the ROM layout, thereby saving the design time, reducing the design risk and lowering the plate-making cost and the manufacturing cost.

Description

A kind of method that the otp memory domain is changed into ROM storer domain

Technical field

The present invention relates to the layout design method of integrated circuit, relate in particular to and utilize one-time programmable memory cell that the gate oxide breakdown phenomenon realizes and by the layout design method of the array of these cell formations.

Background technology

In the design production run of programmable integrated circuit, the general OTP technology that adopts is carried out the trial-production of the integrated circuit of short run, after trial-produceing successfully, owing to utilizing the manufacturing of OTP technology, test, burning cost higher, often adopt the ROM technology to carry out large batch of integrated circuit production, with the direct mask of program embedded in the integrated circuit in the ROM circuit.

The way that traditionally the OTP circuit is made into the ROM circuit is to design respectively otp memory domain and ROM storer domain, needs to make two cover reticle, has both delayed design time, has also increased design risk and plate-making expense.

Summary of the invention

The present invention is intended to solve the deficiencies in the prior art, provides a kind of based on a cover otp memory domain, only revises the method that the part level changes the otp memory domain into ROM storer domain.

The present invention also provides a kind of ROM storer domain of the method acquisition that utilizes the otp memory domain to change ROM storer domain into.

A kind of method that the otp memory domain is changed into ROM storer domain is characterised in that two ends that will need the memory circuit structure that burning punctures in the otp memory domain, realizes by short circuit in ROM storer domain; Two ends that do not need the memory circuit structure of burning puncture, in ROM storer domain, realize by disconnecting:

1) according to the domain level, the otp memory domain comprises: N-type active area, polycrystalline, connection N-type active area be connected with polycrystalline ground floor aluminium (aluminium) fairlead, an aluminium, connect an aluminium with through hole, two aluminium of second layer aluminium (two aluminium);

2) polycrystalline on the memory circuit and an aluminium belong to the first voltage end P of storage unit in the otp memory domain, connect by fairlead with each storage unit of delegation;

When 3) the otp memory domain changes ROM storer domain into, first the polycrystalline of memory circuit and the first nmos pass transistor is deleted;

4) need grid and the source electrode of the memory circuit of burning, in ROM storer domain, be connected with an aluminium of memory circuit by the N-type active area of fairlead with the memory circuit source electrode;

Described otp memory is comprised of One Time Programmable unit bag, the One Time Programmable unit comprises: memory element, the first nmos pass transistor and the second nmos pass transistor, the grid of memory element connects the first voltage end P, the source of described memory element and connect the drain electrode of described the first nmos pass transistor, the grid of the first nmos pass transistor connects second voltage end D, the source electrode of the first nmos pass transistor connects described the second nmos transistor drain, the grid of the second nmos pass transistor connects row selecting side R, and the source electrode of the second nmos pass transistor connects column selection end C.

The otp memory domain is changed into the method for ROM storer domain, be further characterized in that the structure that guarantees not change the otp memory domain in the modification process, such as shape, size, layout.

The method of utilizing above-mentioned otp memory domain to change ROM storer domain into obtains a kind of ROM storer domain, it is characterized in that:

ROM storer domain level comprises successively: N-type active area, polycrystalline, connection N-type active area/polycrystalline with fairlead, an aluminium of ground floor aluminium (aluminium), connect an aluminium with through hole, two aluminium of second layer aluminium (two aluminium);

Described ROM storer is comprised of memory cell array, and storage unit has two types: i.e. ROM_1, ROM_0; Wherein ROM_1 comprises:

One connecting line is as the first voltage end P;

Nmos pass transistor, the grid of described nmos pass transistor are drawn as row selecting side R, and the nmos pass transistor source electrode is drawn as column selection end C;

The domain of described ROM_1 is characterised in that by fairlead and connects the N-type active area of nmos transistor drain and the aluminium of the first voltage end P;

Wherein ROM_0 comprises:

One connecting line is as the first voltage end P;

Nmos pass transistor, the grid of described nmos pass transistor are drawn as row and are selected line R, and the source electrode of nmos pass transistor is drawn as column selection line C;

The feature of the domain of described ROM_0 is not connected with the aluminium of the first voltage end P at the N-type active area of nmos transistor drain;

Each storage unit of ROM storer selects line R, column selection line C to interconnect by the first voltage end P, row respectively.

Beneficial effect of the present invention is, based on a cover otp memory domain, only revise the part level and change the otp memory domain into ROM storer domain, save design time, reduce the design risk, plate-making expense and manufacturing cost, simultaneously, because the otp memory domain is consistent with the domain of ROM storer domain before polycrystalline, manufacture also consistent before the polycrystalline, therefore wait selecting factors otp memory domain or ROM storer domain according to sale again after can waiting until polycrystalline, determine that final output is OTP product or ROM product, convenient tissue is produced and stock control.

Description of drawings

The storage unit circuit figure of accompanying drawing 1OTP storer

The equivalent circuit diagram of the otp memory storage unit that punctures among accompanying drawing 2 Fig. 1

The storage unit ROM_1 circuit diagram of accompanying drawing 3ROM storer

The storage unit ROM_0 circuit diagram of accompanying drawing 4ROM storer

Accompanying drawing 5OTP storer schematic diagram

The domain of the otp memory unit that accompanying drawing 6 is shown in Figure 1

The domain of the ROM storage unit ROM_1 that accompanying drawing 6-1 is shown in Figure 3

The domain of the ROM storage unit ROM_0 that accompanying drawing 6-2 is shown in Figure 4

The domain of the otp memory that accompanying drawing 7 is shown in Figure 5

The domain of the otp memory of accompanying drawing 7-1 Fig. 7 is revised as the domain of ROM storer

Accompanying drawing 8 changes the otp memory domain into the process flow diagram of ROM storer domain

Specific embodiment

The present invention will be described below in conjunction with accompanying drawing.

Otp memory is comprised of One Time Programmable unit bag, the One Time Programmable unit comprises as shown in Figure 1: memory element, the first nmos pass transistor and the second nmos pass transistor, the grid of memory element connects the first voltage end P, the source electrode of described memory element connects the drain electrode of described the first nmos pass transistor, the grid of the first nmos pass transistor connects second voltage end D, the source electrode of the first nmos pass transistor connects described the second nmos transistor drain, the grid of the second nmos pass transistor connects row selecting side R, and the source electrode of the second nmos pass transistor connects column selection end C.

Otp memory comprises M every trade line Ri, i is from 1 to M, N row alignment Cj, j is from 1 to N, and M * N One Time Programmable unit, the One Time Programmable unit be positioned at separately line and the point of crossing of alignment, the first voltage end P of each One Time Programmable unit connects the first voltage end P of programmable array, the second voltage end D of each One Time Programmable unit connects the second voltage end D of programmable array, the capable selecting side R of each One Time Programmable unit connects a certain line Ri of programmable array, and the column selection end C of each One Time Programmable unit connects a certain alignment Cj of programmable array.For example understand as shown in Figure 5 the otp memory of one or two row, two row.

When the storage unit of otp memory needs to puncture under the burning pattern, its storage unit is breakdown, the equivalent circuit diagram of the storage unit that punctures is seen Fig. 2, resistance among Fig. 2 is less, flow through the first voltage end P larger to the electric current of second voltage end D, can be on the basis of accompanying drawing 2 resistance be considered as wire (seeing accompanying drawing 3) this moment;

When the storage unit of otp memory did not need to puncture under the burning pattern, the equivalent circuit diagram of the storage unit that does not puncture was seen Fig. 4.

The equivalence principle of storage unit after burning according to otp memory, the present invention proposes a kind of method that the otp memory domain is changed into ROM storer domain, in the otp memory domain, will need to it is characterized in that two ends of the circuit structure that burning punctures, in ROM storer domain, realize by short circuit; Two ends that do not need the circuit structure of burning puncture, in ROM storer domain, realize by disconnecting:

Shown in Figure 8 such as flow process:

1) according to the domain level, otp memory domain as shown in Figure 7 comprises: N-type active area, polycrystalline, connection N-type active area be connected with polycrystalline ground floor aluminium (aluminium) fairlead, an aluminium, connect an aluminium with through hole, two aluminium of second layer aluminium (two aluminium);

The through hole of the same aluminium of wherein said two aluminium and the fairlead of the same aluminium of N-type active area in position can be overlapping.

Polycrystalline on the same line of each storage unit of wherein said otp memory with is connected aluminium and can connects by one or more fairleads.

The ROM storer domain shown in accompanying drawing 7-1 that the method for utilizing above-mentioned otp memory domain to change ROM storer domain into obtains is characterized in that:

Described ROM storer is comprised of memory cell array, and storage unit has two types: i.e. ROM_1, ROM_0;

ROM_1 wherein as shown in Figure 3, comprising:

One connecting line is as the first voltage end P;

ROM_0 wherein as shown in Figure 4, comprising:

One connecting line is as the first voltage end P;

It should be understood that above-described embodiment is just to explanation of the present invention; rather than limitation of the present invention; any innovation and creation that do not exceed in the connotation scope of the present invention are revised: as changing the circuit structure of otp memory, ROM storer and the NMOS in the domain into PMOS etc., all fall within the protection domain of the present invention.

Claims

1. the otp memory domain is changed into the method for ROM storer domain, be characterised in that two ends of the memory circuit structure that in the otp memory domain, will need the burning puncture, in ROM storer domain, realize by short circuit; Two ends that do not need the memory circuit structure of burning puncture, in ROM storer domain, realize by disconnecting:

1) according to the domain level, the otp memory domain comprises: N-type active area, polycrystalline, connection N-type active area be connected with polycrystalline aluminium fairlead, an aluminium, connect an aluminium with through hole, two aluminium of two aluminium;

Described otp memory is comprised of One Time Programmable unit bag, the One Time Programmable unit comprises: memory element, the first nmos pass transistor and the second nmos pass transistor, it is described that to need burning to puncture element be the two ends memory element, the grid of memory element connects the first voltage end P, the source electrode of described memory element connects the drain electrode of described the first nmos pass transistor, the grid of the first nmos pass transistor connects second voltage end D, the source electrode of the first nmos pass transistor connects described the second nmos transistor drain, the grid of the second nmos pass transistor connects row selecting side R, and the source electrode of the second nmos pass transistor connects column selection end C.

2. the method that the otp memory domain is changed into ROM storer domain as claimed in claim 1 is further characterized in that the structure that guarantees not change the otp memory domain in the modification process.

3. the method that the otp memory domain is changed into ROM storer domain as claimed in claim 2 is characterized in that guaranteeing not change in the modification process shape, size and the layout of otp memory domain.