CN101923135A - Scan chain circuit for FPGA interpolation interconnection test - Google Patents

Abstract

The invention relates to a scanning chain circuit for an FPGA (Field Programmable Gate Array) interpolating and interconnecting test, belonging to the FPGA technical field. By using triggers of programmable logic parts in a chip, the programmable logic parts of an FPGA are mutually serially connected to form a scanning chain which is specially used for testing an interconnecting wire and controlled by using a scanning mode signal; meanwhile, according to the requirements, the scanning chain is segmented into a plurality of sections by using IO to improve the flexibility of the scanning chain. Because of multiplexing the triggers, the area added because of inserting the scanning chain is very little, and the difficulty of the interconnecting test can be greatly reduced.

Description

Scan chain circuit for FPGA interpolation interconnection test

technical field

The invention belongs to the technical field of FPGA, in particular to an FPGA interpolation interconnection test scan chain circuit.

Background technique

In the design and implementation of Field Programmable Gate Array FPGA, the test of interconnection (Interconnect) has always been a relatively difficult problem to solve. There are many interconnect lines and interconnect switches inside the chip, and it usually takes a lot of time and configuration files to locate the problematic interconnect lines or interconnect switches. The usual test method is to select an interconnection path in the chip, connect this path to the IO, add excitation from the input IO, and observe whether the output is the same as the input at the output IO. The disadvantage of this method is that if the interconnection path is stretched very long, once there is an error on the path, it will be more difficult to locate the error; and if the path is very short, it is necessary to write a large number of configuration files to cover the entire chip.

In order to reduce the difficulty of testing interconnection wires and interconnection switches and save test time. The present invention utilizes the flip-flop in the programmable logic unit as the flip-flop for scanning in the FPGA chip we designed, inserts the special-purpose scan chain of interconnection test in the chip, and sets the scan mode to be used for testing interconnection line and interconnection switch. Since we reuse the flip-flops, the area increased by inserting scan chains is minimal, but at the same time it can greatly reduce the difficulty of interconnection testing.

Contents of the invention

The purpose of the present invention is to provide an improved programmable logic circuit in FPGA to reduce the difficulty of interconnection testing .

Aiming at the shortcomings of complex interconnection structure and difficult testing in FPGA, the invention inserts scan chains for interconnection testing into the programmable logic part of FPGA. Specifically, the flip-flops in the programmable logic part of the chip are used to form a scan chain in series, which is specially used for the test of the interconnection line, and is controlled by a scan mode signal; at the same time, the scan chain can be divided into Several segments, which can also improve the flexibility of the scan chain.

The scan chain circuit in the entire chip is shown in Figure 1. The scan chains in each column of programmable logic blocks are connected in series from the top to the bottom, and then reversed back to the top. The data terminals and scan control signals of each column scan chain in the entire chip can be connected in series, and can be configured to be transmitted from left to right or from right to left. The scan input of the scan chain of each column can be output from the scan chains on both sides, or from the IO at the top of the column, and the scan result can also be output from the top IO of the programmable logic block of the column, or can be sent to the left and right scan chains output.

technical effect

After adopting the improved interpolation scan chain technology, the efficiency of interconnection testing and the efficiency and accuracy of error positioning have been greatly improved. When there was no scan chain in the past, the test of interconnection can only use the method of traversal test, which is to connect many interconnection lines to see if the line is smooth. This method cannot accurately locate the wrong position, but with the scan chain, it becomes very easy to locate the error.

Description of drawings

FIG. 1 is an overall schematic diagram of a scan chain circuit.

Figure 2 is a schematic diagram of a scan chain within a programmable logic block.

FIG. 3 is a schematic diagram of a scanning control signal gating circuit.

FIG. 4 is a schematic diagram of the scanning path inside each SLICE.

Detailed ways

The se signal in Figure 2 is the Scan Enable signal. This signal is used to control the scan chain to enter the scan mode. The scan chain in each programmable logic block enters from SLICE1 in the upper left corner through the sil signal, and then enters SLICE2 in the lower left corner. , and then go out from the sol in the lower left corner, and enter the upper left corner of the next SLICE, so that it goes all the way to the bottom of the chip, and then goes to the SLICE in the lower right corner, and then goes up and back into SLICE3, and SLICE4 goes up and out, each column The scan chain of the programmable logic block can be output from the IO on the top, so that the entire scan chain can be segmented by column, which can save scanning time and improve the efficiency of error detection when locating interconnection errors.

In order to improve the flexibility of the scan chain, we set the scan chain to scan from left to right or from right to left by column. There is a multiplexer in each top IO that is responsible for controlling the direction of the scan chain, which is the multiplexer MUX in Figure 1. This multiplexer can output the scan data stream input from the right column of programmable logic blocks, or the scan data stream output from the left column of programmable logic blocks.

In addition, in order to cooperate with the separation and bidirectionality of the scan chain, we have added multiplexers for the selection of the scan control signal se, which are the multiplexers in Figure 3. The default configuration of the se signal in this column is 0. After the scan mode is turned on, you can choose to give it from the outside of the PAD, or transmit it from the se signal of the scan chain on the left or right. Similarly, the se signal of this column will also be transmitted to the scan chains on the left and right.

It can be seen from Figure 4 that there are two D flip-flops in each SLICE. In non-scan mode, data enters the flip-flop latch from the other input terminals of the two MUXs. In the scan mode, the se signal is turned on, and the data is sequentially sent from the s_data_in terminal through the D1 and D2 two-level flip-flops to pass through the SLICE, and then transmitted to the next SLICE or PAD from the s_data_out terminal. It can be seen from this figure that each CLB has four SLICEs, so each CLB can measure 8 interconnection lines or 8 interconnection switches at a time.

references:

[1] Ouyang Yiming, Liu Juan, Liang Huaguo, and Chen Tian, "A low-power scan chain structure based on selection", Computer Engineering and Applications, 2010 46(1).

[2] Yu Weilai, Jinmei Sun Chengshou, Tong Jiarong, "Design and Implementation of Boundary Scan Circuit in FPGA Chip", Computer Engineering 2007 13.

[3] Ma Xiaojun Tong Jiarong, "A Boundary Scan Circuit Applied to FPGA Chip", Microelectronics 2004 3.

Claims (4)

1. FPGA interpolating and interconnecting test scan chain circuits, it is characterized in that the FPGA (Field Programmable Gate Array) part at FPGA, utilize the trigger of FPGA (Field Programmable Gate Array) part in the chip, series connection forms a scan chain mutually, be specifically designed to the test of interconnection line, and control with a scan pattern signal; Simultaneously, as required, scan chain is divided into several sections, to improve the dirigibility of scan chain by IO.

2. FPGA interpolating and interconnecting test scan chain circuits according to claim 1 is characterized in that scan chain is to be connected in series to bottom and then the anti-portion of returning back to top of wearing from the top in each row programmable logic block; The data terminal of each column scan chain and scan control signal are contacted mutually in the entire chip, can be configured to transmit from left to right or transmission from right to left; The scanning input of the scan chain of each row comes from the scan chain output on both sides, and perhaps the IO output from this row top comes, and scanning result is from the top IO output of the programmable logic block of these row, perhaps scan chain output to the left and right sides.

3. FPGA interpolating and interconnecting test scan chain circuits according to claim 2 is characterized in that

All be provided with a multi-channel gating device among each each programmable logic block top IO, be responsible for the gated sweep chain direction specially, the scan data stream of this multi-channel gating device output one row programmable logic block input, the perhaps scan data stream of one row programmable logic block output from the left side from the right.

4. FPGA interpolating and interconnecting test scan chain circuits according to claim 3 is characterized in that

Be provided with scan control signal se and select to use MUX; This MUX is 0 to the scan control signal se signal default configuration of these row, after scan pattern is opened, selects to be given by the outside from PAD, is perhaps passed by the scan control signal se of the left side or the right one column scan chain and comes.

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