CN101919162B - Layout method for soft-error-resistant electronic devices and radiation-hardened logic cells - Google Patents
Layout method for soft-error-resistant electronic devices and radiation-hardened logic cells Download PDFInfo
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Abstract
The present invention includes a layout method for effectively protecting a logic circuit from a soft error (non-destructive error) and a circuit cell having a layout protected from a soft error. In particular, the method prevents a situation where multiple nodes in the circuit are affected by a single event. These particles cause multiple errors in the circuit and while there are several methods to handle single-node errors, it is difficult to handle multi-node errors with the currently existing protection methods. This approach is particularly beneficial for CMOS based logic circuits (< 90nm) in modern technologies where the occurrence of multi-node pulses becomes high (due to high integration levels). The method uses a unique layout structure that protects the circuit from single event generated soft errors.
Description
The cross reference of related application
The application requires the priority of No. 61/068483 of submitting on March 7th, No. 61/011989 1 that on January 22nd, No. 61/011599 1 that on January 17th, 2008 submits submits and No. 61/123003 U.S. Provisional Application of submitting on April 5th, 2008, and these applications are contained in this by reference.
Technical field
The application comprises a kind of circuit unit for preventing that logical circuit from suffering the layout method of soft error (non-destructive mistake) and having the layout that prevents from suffering soft error.Especially, the method prevents the situation that the multinode in circuit is affected by single-particle.These particles cause a plurality of mistakes in circuit, although and exist several method to process the single node mistake, utilize current existing guard method to be difficult to process the multinode mistake.The method is especially useful for the logical circuit based on CMOS (≤90nm) in the modern technologies that uprise (due to high integrated horizontal) of multinode pulse.The method is used soft error, the unique layout structure that prevents that circuit from generated by single-particle.
The soft error problem generated by single-event transients (and single-particle inversion) be expected in sub-micro (<90nm) technology increase more serious.The particularly important is, the logical circuit expection soft error generated for radiation that becomes is more responsive, and may surmount the main source that memory becomes the single-particle mistake.In addition, the incidence of many mistakes, multidigit upset (MBU) and single event multiple bit upset (SEMU) increases.
The main cause of this problem is, along with feature is integrated higher higher with frequency, the spatial distribution of single-event transients (SET) becomes relative larger with pulse length, thus increased the SET pulse latched for (soft) mistake or produce the SET pulse by a single-particle on several circuit nodes simultaneously may.
Because the cost of semiconductor design and manufacture increases gradually, the problem that soft error rate increases is further complicated.Exploitation and maintain related expensive of semiconductor FAB and make the also Application standard business semiconductor manufacture of application of expecting very much for the high radiation tolerance of needs.Therefore, exist very strong power to carry out radiation-hardened design (RHBD) technology of and robust effective for these application and developments.
In addition, it is very complicated and expensive that design process also becomes, and expect that very much application can be reused standard design IP and storehouse as much as possible for radioresistance.
Background technology
The radiation-hardened design technology of current single-particle mistake comprise three times (triplication redundancy, TMR) or twice (for example, embed the soft error reparation, BiSER).Two or more redundant copy of these circuit carrier signals, and determine the correct signal in these redundant signals with voting or the filtering circuit of form of some.In the situation that one of redundant signals is wrong (by comparing the value of redundant signals), filter anti-stop signal and pass through, select correct signal in most of redundant signals of voting circuit from several (3 or a plurality of) redundant signals.
These technology produce undesirable electric power and regional expense, and the current version of these technology can not be processed MBU or SEMU.The error-correcting code, ECC that also can (not strictly) be classified as the memory of RHBD than twice/tri-times of redundancies more effective, and can process a plurality of mistakes in memory circuitry with extra-pay.For example, yet corresponding error correction is (, selectivity parity check or insert special-purpose check circuit IP) of very limited and application-specific for the application of logical circuit.
The state-of-the art of the topology designed for soft fault preventing mainly comprises simple setting space, size is set and increases extra contact zone.
Summary of the invention
When the contact area on Semiconductor substrate is collected the electric charge for example, generated in semi-conducting material by one or more (secondary) electric charge particle, radiation generates, single-particle (soft) mistake (SEE) occurs.Current impulse on this circuit network that causes being connected with these contact areas, these current impulses produce the potential pulse in circuit conversely, can overturn sequential element (latch, trigger) or propagate and next sequential element place in circuit is latched as mistake by combinational logic of these potential pulses.
The present invention includes a kind of new layout method of uniqueness, it utilizes the integrated circuit response for the single particle effect, and comprises the circuit unit with the layout that prevents soft error.The method is used the layout in critical contact zone in the following way: single-particle impulse action that generate on multinode, in circuit is opposite each other and thereby offset (or greatly reducing) single particle effect.In the situation that with primary circuit and secondary circuit maintain or treatment circuit in signal, use the additional rules described in part 4, thereby make can not be in the primary and secondary both circuits generation errors all, thereby the combination of primary and secondary circuit will not have mistake fully.
The accompanying drawing explanation
Table 1: use the state of the node in the circuit of elementary (node n1, n2) and secondary (node n3, n4) circuit, wherein, the primary and secondary circuit is for storage or process this state.
Fig. 1: in latch unit about the elementary relative node of latch state.
Fig. 2: the example of the layout placement of the relative node of latch cicuit (draining 1 is connected with one of network, drain 2 be connected with another network of the opposite voltage state with first network).
Fig. 3: node 1～4, p1～p4 and n1～n4 are respectively the Basic Net table of the DICE latch units (prior art [Nic05]) of pMOSFET drain electrode and nMOSFET drain electrode.
Fig. 4: the first preferable layout of the layout of DICE latch units is arranged.Ns/ps is the source contact area of two adjacent mosfet of drain electrode.P1～p4 and n1～n4 are respectively pMOSFET drain electrode and the nMOSFET drain electrode of 4 primary storage nodes.Any circulation synchronous displacement of n and p node will be (and being a part of the present invention) be equal to.These mosfet can be placed on the independent zone of action or adjacent n and p node can be arranged on the same zone of action.Can the MOSFET source electrode be set along drain electrode or with the perpendicular direction of drain node.The trap contact zone can only be arranged on a side or also can be around adjacent node pair.Also can be by following rule with the different nodes that is disposed in order: two adjacent n drain electrodes or two adjacent p drain electrodes be strange/couple (for example, p1& always; P2 or n2& N3), adjacent n drain p drain electrode always strange/very to or idol/couple (for example, n2& P2 or p3& N1).
Fig. 5: corresponding to the net table of the second preferred arrangements.As long as drain electrode 6a and p1 that node 6 is connected in Fig. 5 physically separate with 6a, can comprise or can not comprise yellow MOSFET.
Fig. 6: the second preferable layout is arranged.Ns/ps is the source contact area of two adjacent mosfet of drain electrode.Node 6a is connected with 6b.Can comprise or can not comprise the yellow grid adjacent with node 6a (these two kinds of modification include in the claims), but p1 and 6a physically separate.This layout derives from the layout in Fig. 1, and application is about the identical modification of node arrangement, activation, source electrode and trap contact zone layout.
Fig. 7: corresponding to the net table of the 3rd preferred arrangements.As long as drain electrode 6a, p1 physically separate with 6a and node 7 is connected in Fig. 4 drain electrode 7a, n1 that node 6 is connected in Fig. 4 physically separate with 7a, can comprise or can not comprise yellow MOSFET.
Fig. 8: the 3rd preferable layout is arranged.Ns/ps is the source contact area of two adjacent mosfet of drain electrode.Node 6a～6b is connected, and node 7a/7b also is connected.Can comprise or can not comprise the yellow grid adjacent with 7a with node 6a (these two kinds of modification include in the claims), but adjacent drain region physically separates.This layout derives from the layout in Fig. 1, and application is about the identical modification of node arrangement, activation, source electrode and trap contact zone layout.
Fig. 9: corresponding to the net table of the 4th preferred arrangements.As long as node 6 is connected to drain electrode 6a, 7 to 7a, 8 to 8a and 9 in Fig. 8 to 9a, and 6a, 7a, 8a and 9a physically separate with their adjacent drain node, can comprise or can not comprise yellow MOSFET.
Figure 10: the 4th preferable layout is arranged.Ns/ps is the source contact area of two adjacent mosfet of drain electrode.Node 6a/6b, 7a/7b, 8a/8b and 9a/9b are connected.Can comprise or can not comprise the yellow grid adjacent with node 6a, 7a, 8a and 9a (these two kinds of modification include in the claims), but node 6a, 7a, 8a and 9a physically separate with their adjacent mos FET drain electrode.This layout derives from the layout in Fig. 1, and application is about the identical modification of node arrangement, activation, source electrode and trap contact zone layout.Naturally, claim also contains the various extra modification that comprises or omitted the combination of additional nodes 6a/6b, 7a/7b, 8a/8b and 9a/9b.
Figure 11: circuit theory diagrams and the layout (for example,, for BISER) of the latch units of the repetition to guarantee to prevent fully single node and multinode single particle effect are set for using layout and size.For the single-particle of the several nodes of impact, only have elementary latching when node 1 is " height " to overturn, and only have redundancy when node 1 (r) is " low " to latch and could overturn.Therefore, any single-particle that affects two latchs one of two latchs of BISER structure that can only overturn, thereby generation error in two latchs simultaneously.
Figure 12: the example of claim 9 and 10 repeat circuit.At redundant node and elementary node, carry in the inverter of repetition of contrary state, 1 all effected if n drain electrode 0 and p drain (if D is " height ") if or n drain electrode 1 and p 0 influenced (D is " low ") that drain, can generate the rub-out signal on elementary node and redundant node.By node is set as follows: if particulate track process can be exported two nodes of generation error transition in elementary output and redundancy, then track also passes through the pulse on one of other node and Suppression network.For example, consider the track in figure: if node 0 is " height ", the electric charge of collecting in n drain electrode 0 will drag down node 0 (mistake transition), the electric charge of collecting in node p drain electrode 1 will be drawn high node 1, yet contrary with the effect in p drain electrode 1, the electric charge of collecting in node n drain electrode 1 will drag down node 1, and keep node 1 low (that is, preventing the transition on node 1).If node 0 is " low ", the electric charge of collecting in node n drain electrode 1 will drag down node 1 (mistake transition), yet the n electric charge that 0 place collects that drains will keep node 0 low (that is, preventing the transition on node 0).It should be pointed out that in normal circumstances, have some pulses on all nodes, but only at a node and only on a duplicate node, to generate full swing pulse (transition that can propagate) always genuine.
Figure 13: the example that increases protection MOSFET device for c element filters circuit.By protection MOSFETn1 by the c element (; the n drain electrode of the output network that becomes unsteady if two inputs have different voltage statuss) is connected to the N-shaped contact area near the n drain electrode of input network 2; or, by the second protection MOSFET, n2 is connected to the n drain electrode of input network 2.When the n drain electrode of the layout n drain electrode that is c element output and input node 2 for the most responsive contact area to (; other mutual responsive contact area further separates; and/or have other a contrary contact area between them) time, it is enough that this protection will become.In the situation that the DICE circuit if necessary, can increase more protection MOSFET device and protect other contact area pair of sensitivity mutually.
Embodiment
The present invention includes a kind of new layout method of uniqueness, it utilizes the integrated circuit response for the single particle effect.The present invention also comprises the particular electrical circuit unit with the layout built according to this new layout method.
When collecting the electric charge for example, generated by one or more (secondary) charged particle in semi-conducting material by contact area, radiation generates, single-particle (soft) mistake (SEE) occurs.The low-resistance coefficient zone that contact area is on Semiconductor substrate or Semiconductor substrate is interior and network in circuit is connected, for example, the source electrode in the MOSFET technology and drain region.Circuit network (or node) refers to that circuit passes through the part that low-resistance coefficient zone (metal) connects, and this part maintains specific magnitude of voltage (voltage status that is called as network) in its gamut.Network can be connected to any amount of contact area.
Contact area collected electric charge during single particle causes the current impulse in circuit, and these current impulses cause the variation of the voltage in the circuit network be connected with these contact areas conversely, i.e. potential pulse in circuit.Can overturn sequential element (latch, trigger) or propagate and next the sequential element place in circuit is latched as mistake by combinational logic (that is, set of number gate) of these potential pulses.
For different contact areas, the effect difference of single-particle to the voltage on circuit network, for example, where be arranged in substrate and how they are connected with circuit according to contact area, single-particle can have the effect that increases the voltage on the network be connected to contact area, or reduces to be connected to the effect of the voltage on the network of contact area.Method of the present invention is used the contact area of following mode to arrange: contrary to effect with regard to the effect of the voltage of circuit network with regard to them in the pulse that occur on a plurality of contact areas, that single-particle in circuit generates, and thereby offset the effect of (or greatly reducing) single-particle.
The method also comprises: when expectation realizes the gross effect for the expectation of circuit, regulate the intensity of single-particle for the effect of circuit network voltage.Size that can be by changing contact area also changes their positions with respect to other assembly in layout, realizes this adjusting.
The method can be applied to sequential logical element (latch, trigger, memory cell), combinational logic (connections of one or more digital logic gates) or analog circuit unit.
Below two part explanations for the details of two kinds of ad hoc fashions applying the method.At first, part 4.1 is used and is arranged and intensity adjustment, thereby makes the single particle effect on several contact areas cancel out each other with regard to the effect of the circuit network be connected with them with regard to them.Secondly, part 4.2 is used and arranged and intensity adjustment, thereby makes single-particle differently affect as follows the two or more redundant networks in circuit: single-particle can not change the voltage status on several redundant networks simultaneously.
A is used the layout method-method 1 be arranged symmetrically with
The committed step of method 1 of the present invention is:
1. when identification is affected by single-particle simultaneously, circuit network there is the contact area of adverse effect;
By these node placements in layout adjacent one another are, and with about other adjacent contact zone mode completely symmetrically:
A. particularly in the CMOS technology, in symmetry (equivalence) the position configuration contact zone about trap binding site and trap contact zone;
If b. two contact areas be sequential element (for example, latch) part, this layout guarantees that these two nodes can not be affected the single-particle inversion in two zones, be that particle has the electric charge (for example, being generated by the charged particle passed) along the expansion of the direction that affects these two nodes;
The part that c. if node is composition element, when the generation single-particle affects two nodes, this layout guarantees that generated output pulse is greatly suppressed, and particle has the electric charge (for example, being generated by the charged particle passed) along the expansion of the direction that affects these two nodes.
3. in the element that uses extra protective circuit (redundant network); the direction of the contact area of redundant network is arranged to: when the elementary network of the charge affects from single-particle and secondary network; the party, make progress, the phase antinodal points that it also always affects the phase antinodal points of elementary or secondary circuit or affects the primary and secondary both circuits.
In particular for the CMOS technology, above-mentioned steps 1 and 2 will be used following mode to characterize the single particle effect on source electrode or drain contact region territory:
A. when single-particle affects n drain electrode (or source electrode), the effect of single-particle will reduce the voltage on the network be connected with this contact area, that is, if this node is " height ", switched voltage, when node is " low ", its general is switched voltage not.
B. when single-particle affects n drain electrode (or source electrode), the effect of single-particle will reduce the voltage on the network be connected with this contact area,, if this node is " height ", by switched voltage, when node is " low ", incite somebody to action not switched voltage that is.
In addition, in particular for the CMOS technology, above-mentioned steps 3 will be used following rule for two nodes that are connected with the network that carries redundant signals (primary and secondary network) separately:
A. when one with elementary network, be connected, one is connected with secondary network, and two n drain (or source electrode) affected by single-particle, and when they always have contrary voltage status, only with one of upset (changing its voltage) primary/secondary network.
B. when one with elementary network, be connected, one is connected with secondary network, and two p drain (or source electrode) affected by single-particle, and they are while always having contrary voltage status, only with one of the primary/secondary network that overturns.
C. when from the n of network drain electrode (or source electrode) and from the p drain electrode (or source electrode) of another affected network, affected by single-particle, and when the network be connected with these drain electrodes (or source electrode) always has identical voltage status, only with one of upset primary/secondary network.
B is used the layout method-method 2 of asymmetric layout
For carry out the situation of the element of store status (that is, voltage or signal) with elementary and redundant network, substituting of the layout of cancelling out each other for the synthesis of single particle effect allows one of contact area become stronger about the single-particle charge-trapping wittingly.Then, this contact area will always determine the result (for example,, for the p drain electrode, will always finish with " high (Vdd) ") of the single-particle on connected network.When network (2 the elementary networks that have four store statuss, 2 redundant networks), and we manage to guarantee and partly account at primary circuit the network that leading contact area is connected, the state that storage is contrary with partly account for network that leading contact area is connected at redundant circuit, the particle that affects two circuit parts can only overturn two redundant circuits one of partly.Use this modification, the unit synthetic method of robust is as follows:
For carry out the design of store status with elementary and redundant network:
The contact area (at elementary and redundancy section) that there is the antimetrical circuit effect when a. identification is affected by single-particle simultaneously;
B. these nodes are arranged in layout adjacent to each other, and make one of these nodes take (for example,, by making drain area become large and changing to the trap junction point and the distance of trap knot) as the leading factor about single-particle;
C. guarantee the network be connected with the leading contact area of primary circuit part, the state that storage is contrary with the network that the leading contact area of redundant circuit part is connected;
D. and redundant circuit elementary with single-particle impact and always affect the mode of the leading and non-dominant node of elementary and redundancy section, relative to each other arrange elementary and redundancy contact area;
(i) by this way, elementary or redundancy section will guarantee that this circuit part can not be reversed the state of (that is, changing its state or voltage) in leading node.Therefore, in any case, in redundancy section, only have one can be overturn by single-particle.
C discussion, explanation and particular electrical circuit unit
In basic sequential logical circuit element (latch, static random type memory cell etc.), there is the master network of two hold modes.They always have contrary state (voltage).Fig. 1 illustrates the schematic diagram of the basic module of the latch circuit of implementing with the CMOS technology.In this latch, each in these two (master) networks is connected with two contact areas (nmos device drain and pmos device drain) in layout.
In this structure, when being subject to same single-particle to affect the contact area that the state about latch is had to a contrary effect, can be identified as (above-mentioned steps 1):
A. the single-particle that affects two pmos drain electrodes will have reverse effect for the state of latch;
B. the single-particle that affects two nmos drain electrodes will have reverse effect for the state of latch;
C. affect drain both single-particle of the nmos drain electrode of same node and pmos and will there is reverse effect for the state of latch.
In symmetry approach, layout placement is become being arranged symmetrically with (that is, about symmetrical, about layout on every side and be of similar shape) in be adjacent to arrange the drain electrode with opposite effect.This is the step 2 in said method 1.Fig. 2 illustrates the layout of having utilized the contrary contact area identification of above-mentioned the first two.We have such latch now: if the direction of single-particle is two networks through oversampling circuit, this latch can not be reversed.
Situation when (redundancy) circuit (being herein latch) that the concern the same as method 2 of the step 3 in method 1 adds is available.In with two latchs, carrying out the circuit structure of hold mode, will there be 4 host nodes: from n1, the n2 of elementary latch and from n3, the n4 of secondary latch.Will be in contrary state from the node of a latch, and at correct circuit run duration, each node in elementary latch will always have and a state that node is identical in secondary latch.Table 1 illustrates this situation, and wherein, n1 and n3 keep identical state, and n2 and n4 keep identical state.
According to step 3, the node of the second latch is set about the first latch now, make when the particle of the expansion that affects two latchs occurs it will be in affecting each independent latch two phase antinodal points or the direction of one of them at least.Figure 11 illustrates this layout, wherein, uses to have the method (said method 2) of leading node, and two latchs relative to each other are set as follows: can overturn at most one of two latchs rather than all of any single-particle.
For example, for other sequential element (, memory cell) situation, be also identical, this method also is applicable to these elements.The method also is applicable to use more than 2 nodes to be carried out the element of hold mode and has elementary and non-sequential element redundant network.
| Node: | n1 | n2 | n3 | n4 |
| State 0 | 0 | 1 | 0 | 1 |
| |
1 | 0 | 1 | 0 |
Table 1: use the state of the node in the circuit of elementary (node n1, n2) and secondary (node n3, n4) circuit, wherein, the primary and secondary circuit is for storage or process this state.
In order from two or more redundant networks, to extract correct signal, use and filter or voting circuit.Filtering circuit guarantee one of redundant network at any time in wrong situation (for example, if the voltage status difference, the situation of carrying the same electrical pressure condition for redundant network) do not allow signal to pass through filtering circuit.Embedding soft error (BISER) design [Mitra2005] is the example of this structure.The voting circuit of use at least 3 redundant circuits put to the vote between the voltage status of redundant network.Triplication redundancy (TMR) structure is used this redundancy.
The present invention also comprises the special-purpose DICE unit that this layout method of several uses generates.DICE (double interlock unit) latch [Nic2005] that Fig. 3 illustrates its circuit also carrys out the memory circuit state with four networks, but as seen from Figure 3, these networks are not to be connected as two independent latchs, but are connected with the form of interlocking.
Primarily being arranged as of 4 storage networkings of DICE of the present invention unit: the contact area that network is set along a direction (for example, Fig. 4), and these contact areas have specific order, so dwindle or eliminate the effect of single-particle, thereby reduce or eliminate the possibility that memory element can be overturn by single-particle.Fig. 4 illustrates the first modification (modification 1).In this modification, MOSFET, to being arranged in the same zone of action, and is had to shared MOSFET source contact area between them.Yet they can also be arranged in the zone of action separately, use source contact area separately, and they can be oriented to the direction of source electrode and drain node is perpendicular.
Increased the protection node in modification 2～4 (Fig. 5～10).The protection node for the protection of specific sensitive nodes to and the normal circuit run duration not (essential) act on.Yet the protection node can also be as the effect device that its grid is connected with other memory node.For example, although modification 1 than normal arrangement (its sensitive nodes between do not have other node) robust more, but still have the responsive residue of some single-particles, be mainly to p1-n2 for node.By modification 1 is expanded to shown in Fig. 5～6, also protect node to p1-n2.This is modification 2.Node the most responsive in modification 2, to being n1-p4 node pair, utilizes this node pair of extended protection in modification 3 (Fig. 7～8).By increasing extra protection node, it is symmetrical that latch finally can be become.Fig. 9～10 (the 3rd modification) illustrate the full symmetric of protection node and arrange.
Increase extra protection MOSFET and there is conventional application for the circuit that uses redundant network.The identical mode with the situation with the DICE circuit, they can be used for remaining on during single-particle the state of circuit node of unsteady (being not or not VSS or VDD are connected with power supply) of becoming.It is very responsive for the single-particle electric charge that unsteady network becomes, and its voltage status (that is, even by the very faint interaction with single-particle) easily changes.Even extra protection device just partly starts during single-particle, also will make the node that becomes unsteady during single-particle more firm.Figure 13 illustrates another example (not being DICE) that increases this protection device for c element filters circuit.
The present invention also comprises the combinational circuit of repeating part as follows or overall network: exist carry (elementary) network of signal and carry the signal on elementary network opposite signal second (redundancy) network (, when the voltage on elementary network is " height ", voltage on redundant network is always " low ", vice versa), and the combinational circuit that the contact area on elementary and redundant network is set as follows according to layout method: when single-particle affects two networks, only with formation voltage pulse on a network rather than on two networks.Combinational circuit for this repetition also needs output (some the some places before depositing signal lock in single sequential element) application is filtered, the propagation of this anti-stop signal, unless two networks all have its correct status (that is, be another contrary).Alternatively, also sequential element be can repeat, and error detection and correction (by comparing the signal identification error on two redundant networks) increased at some some places of circuit.Figure 12 illustrates the combinational circuit of this repetition.
Claims (15)
1. the method for the layout electronic circuit, wherein, described electronic circuit comprises contact area, described method comprises:
A. for each contact area in described circuit determine due near the single-particle occurred each contact area, cause, for the impact of the voltage status of the one or more networks in described circuit;
B. as follows described contact area is classified: the identification form particle has the contact area of otherwise impact for the voltage status of the network in described circuit, and single-particle has the contact area of non-otherwise impact for the voltage status of the network in described circuit;
C., these contact areas are set as follows: when single-particle has otherwise impact for the voltage status of circuit network, with regard to described circuit and design rule, allow near-earth as far as possible mutually that the first and second contrary contact areas are set;
D., the non-otherwise impact of the first contact area and the second contact area have to(for) the voltage status of the network in described circuit are set, described non-otherwise impact is produced by single-particle, wherein, described the first contact area and described the second contact area are non-adjacent, and between described the first contact area and described the second contact area, the 3rd contact area is set, wherein, described the 3rd contact area has the impact contrary with the impact of described the first contact area and described the second contact area for the voltage status of the network in described circuit, and wherein said the 3rd contact area is to be produced by single-particle for the impact of the voltage status of the network in described circuit, and
E. regulate as follows the intensity of single-particle on set contact area impact: relative to affect intensity identical but contrary.
2. method according to claim 1, wherein, described circuit has at least two networks that carry same signal, wherein, each in these networks has single-particle and the voltage status of described two networks is had at least two contact areas of otherwise impact, and described method comprises:
A., the first contact area and the second contact area from independent redundant network are set separately, single-particle has the impact that changes the voltage status on two redundant networks, wherein, described the first contact area and described the second contact area are non-adjacent, and between described the first contact area and described the second contact area, the 3rd contact area is set, for described redundant network, voltage status one of at least has impact to described the 3rd contact area, and the impact of wherein said the 3rd contact area is that by single-particle, produced and contrary with the impact of described the first contact area and described the second contact area, and
B. regulate as follows the intensity of the single-particle impact on set contact area: any single-particle maximum that affects described two redundant networks can change the state of one of described network rather than two networks.
3. method according to claim 1, wherein, described circuit has at least two networks that carry signal and its inverted signal, wherein, each in these networks has single-particle and the voltage status of described two networks is had at least two contact areas of otherwise impact, and described method comprises:
A., the first contact area and the second contact area from independent redundant network are set separately, single-particle has the impact that changes the voltage status on two redundant networks, wherein, described the first contact area and described the second contact area are non-adjacent, and between described the first contact area and described the second contact area, the 3rd contact area is set, for described redundant network, voltage status one of at least has impact to described the 3rd contact area, and the impact of wherein said the 3rd contact area is that by single-particle, produced and contrary with the impact of described the first contact area and described the second contact area, and
B. regulate as follows the intensity of the single-particle impact on set contact area: any single-particle maximum that affects described two redundant networks can change the state of one of described network rather than two networks.
4. wherein regulate as follows according to the method in claim 2 or 3, the intensity of the single-particle impact on set contact area: the state that can change one of described network rather than two networks through any single-particle maximum of described two redundant networks.
5. according to claim 1 or 2 or 3 described methods, wherein, described circuit utilizes the MOSFET device, and described method also comprises:
A. whole MOSFET source electrodes (S) that identification is not direct and electric power network (VSS, VDD) connects and drain electrode (D) doped region, as described contact area; And
B. identify N-shaped MOSFET drain electrode or source electrode and there is the contact area of the impact that the voltage status of the network will be connected with this contact area drags down as single-particle, and the MOSFET drain electrode of identification p-type or source electrode have the contact area of the impact that the voltage status of the network will be connected with this contact area draws high as single-particle.
6. method according to claim 5 also comprises:
A. increase extra MOSFET device between two networks, described extra MOSFET device all carries contrary voltage status at any time as follows: if the first network in described two networks is affected by single-particle, its voltage status is changed, described extra MOSFET device starts, connect described two networks, thereby guarantee that the state of second network does not change; And
B. connect source electrode or the drain electrode of the p-type MOSFET in described two networks by extra p-type MOSFET, and its grid is connected to high level electric power network (VDD), and connect source electrode or the drain electrode of the N-shaped MOSFET in described two networks by extra N-shaped MOSFET, and its grid is connected to low level power network (VSS).
7. the layout structure of a sequential logic or memory cell, it carrys out the state of memory element with two or more latchs, each latch has at least one network of storage voltage state and at least one network of the inverse value of storing this voltage status, and the layout structure of described sequential logic or memory cell comprises:
A. the layout of the contact area of each network in the following manner: place symmetrically the contact area of at least 4 these networks along a line in described layout structure, and relative to each other be placed to make and there is no two contact areas:
I. carry identical voltage status, and single-particle has identical impact for the voltage status of network; Or
Ii. carry different voltage statuss, and single-particle has contrary impact for the voltage of the network of adjacent setting.
8. the layout structure of sequential logic according to claim 7 or memory cell, wherein, filtering circuit is connected to the output of redundant network, described filtering circuit is for the situation of two redundant networks, prevent that data-signal from passing through, unless described two networks all have correct data, the layout structure of described sequential logic or memory cell comprises:
A. a layout, the intensity wherein single-particle responded is adjusted to and makes the upper total impact produced by single-particle of one of network contrary with the total impact produced by single-particle on its redundancy corresponding part, thereby guarantee when single-particle affects two networks in these networks one and only have one can change its state.
9. the layout structure of sequential logic according to claim 7 or memory cell, wherein, voting circuit is connected to the output of redundant network, described voting circuit is for three redundant networks, between the state of described redundant network, put to the vote, the layout structure of described sequential logic or memory cell comprises:
A. a layout, the intensity wherein single-particle responded is adjusted to and makes the upper total impact produced by single-particle of one of network contrary with the total impact produced by single-particle on its redundancy corresponding part, thereby guarantee when single-particle affects three networks in these networks one and only have one can change its state.
10. a sequential logic unit, it comprises four inverter circuits, each inverter circuit comprises a p-type MOSFET and a N-shaped MOSFET, wherein, be connected to the grid of the N-shaped MOSFET of the grid of p-type MOSFET of another the second inverter and another the 3rd inverter by the output by each inverter, inverter is connected to double interlock unit (DICE), each grid only is connected to an output, thereby there are four networks, one is connected to each inverter output and two grids, two networks carry voltage status anti-phase that identical voltage status and two other network carry the first two network, each network has a p-type drain contact region territory and a N-shaped drain contact region territory, described sequential logic unit comprises:
A. the layout that the contact area of each in four networks arranges along the line in the layout of described sequential logic unit; And
B. wherein, two adjacent n drain contact region territories or two adjacent p drain contact region territories always belong to the network that carries the opposite voltage state, and wherein adjacent n drain contact region territory and p drain contact region territory always belong to the network that carries the same electrical pressure condition.
11. sequential logic according to claim 10 unit, wherein, described two adjacent n drain contact region territories or described two adjacent p drain contact region territories are connected to the described network that carries the opposite voltage state.
12. sequential logic according to claim 10 unit; wherein in described sequential double interlock unit (DICE); one or more extra protection MOSFET devices increase and be connected to described sequential logic unit two networks between, comprising:
A. a structure, wherein said extra MOSFET device is connected so that the grid of extra p-type device is connected to high level (VDD), one in drain electrode or source electrode is shared the p-type contact area of the first network in described sequential logic unit, and the other one in drain electrode or source electrode is connected to source electrode or the drain contact region territory of another the second extra p-type MOSFET, other drain electrode of the described second extra p-type MOSFET or source electrode Share interlinkage are to the p-type contact area of the second network in described sequential logic unit, or be connected to p-type with the second network of the described sequential logic unit adjacent contact area that drains, but be not attached to network, described second network in described sequential logic unit has the reverse voltage state of described first network, and the grid of extra N-shaped device is connected to low voltage level (VSS), and the one in drain electrode or source electrode is shared the N-shaped contact area of the first network in described sequential logic unit, and the another one in drain electrode or source electrode is connected to source electrode or the drain contact region territory of another the second extra N-shaped MOSFET, other drain electrode of the described second extra N-shaped MOSFET or source electrode are shared the N-shaped contact area of the second network in described sequential logic unit, or be connected to N-shaped with the second network of the described timing unit adjacent contact area that drains, but be not attached to network, described second network in described sequential logic unit has the reverse voltage state of described first network, and
B. a structure, any additional drain or the source contact area territory that wherein belong to described extra MOSFET device are arranged by the same line in the layout of the contact area along described sequential logic unit.
A 13. combinational circuit, wherein, whole or the selected part of logic element is repeated, and data-signal is by elementary network and carry this signal or its anti-phase secondary network is carried, and wherein, before each sequential element, filtering circuit is set, this filtering circuit passes through for anti-stop signal, unless two redundant networks carry correct signal, or described sequential element also is repeated, and described combinational circuit comprises:
A. a layout, wherein the contact area of primary and secondary network is configured such that separately between the first contact area of independent redundant network and the second contact area, not having straight line, single-particle has the impact that changes the voltage status in the network be connected with described circuit region, unless had at least one the 3rd contact area along the line between described the first contact area and described the second contact area between described the first contact area and described the second contact area, for described the 3rd contact area, the impact of single-particle voltage status one of at least for described two redundant networks is contrary with the impact on described the first contact area and described the second contact area.
14. combinational circuit according to claim 13 comprises:
A. a layout, it is contrary that the intensity wherein single-particle responded is adjusted to the total impact produced by single-particle on another network made in upper two redundant networks of total impact and this that produced by single-particle of one of two redundant networks, thereby guarantee when single-particle affects described two redundant networks to only have energy generation error signal in circuit in these two networks.
15. combinational circuit according to claim 13, be included in error detection and/or the correcting circuit of the end of repeat circuit.
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| PCT/US2009/031160 WO2009091928A2 (en) | 2008-01-17 | 2009-01-15 | Layout method for soft-error hard electronics, and radiation hardened logic cell |
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| WO2013082611A2 (en) | 2011-12-02 | 2013-06-06 | Robust Chip Inc. | Soft error hard electronics layout arrangement and logic cells |
| WO2014066402A1 (en) | 2012-10-22 | 2014-05-01 | Klas Olof Lilja | Circuit and layout design methods and logic cells for soft error hard integrated circuits |
| US9082624B2 (en) * | 2013-01-02 | 2015-07-14 | International Business Machines Corporation | Signal path of a multiple-patterned semiconductor device |
-
2009
- 2009-01-15 EP EP13176436.7A patent/EP2685633A3/en not_active Withdrawn
- 2009-01-15 CN CN2009801024867A patent/CN101919162B/en not_active Expired - Fee Related
- 2009-01-15 WO PCT/US2009/031160 patent/WO2009091928A2/en active Application Filing
- 2009-01-15 US US12/354,655 patent/US20090184733A1/en not_active Abandoned
- 2009-01-15 JP JP2010543259A patent/JP2011512026A/en active Pending
- 2009-01-15 KR KR1020107017290A patent/KR20100138874A/en not_active Ceased
- 2009-01-15 EP EP09702623.1A patent/EP2245740B8/en not_active Not-in-force
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2011
- 2011-10-19 US US13/277,135 patent/US8566770B2/en active Active
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2013
- 2013-09-13 US US14/026,648 patent/US9081926B2/en active Active
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2014
- 2014-10-10 JP JP2014208823A patent/JP2015053498A/en active Pending
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| CN2218426Y (en) * | 1994-06-16 | 1996-01-24 | 东南大学 | High performance hybrid integrated optic trunker |
| CN1152798A (en) * | 1995-09-08 | 1997-06-25 | 日本电气株式会社 | Method for making radiation-resistance semiconductor integrated circuit |
| CN2629309Y (en) * | 2003-06-06 | 2004-07-28 | 戴迪 | Antiinterference protector for electric appliance |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9081926B2 (en) | 2008-01-17 | 2015-07-14 | Klas Olof Lilja | Soft error and radiation hardened sequential logic cell |
| US9083341B2 (en) | 2008-01-17 | 2015-07-14 | Robust Chip Inc. | Soft error resilient circuit design method and logic cells |
Also Published As
| Publication number | Publication date |
|---|---|
| US20090184733A1 (en) | 2009-07-23 |
| WO2009091928A3 (en) | 2009-10-22 |
| EP2245740A4 (en) | 2013-01-16 |
| CN101919162A (en) | 2010-12-15 |
| JP2016001741A (en) | 2016-01-07 |
| KR20100138874A (en) | 2010-12-31 |
| EP2245740B8 (en) | 2014-10-01 |
| EP2685633A3 (en) | 2014-05-07 |
| WO2009091928A2 (en) | 2009-07-23 |
| US9081926B2 (en) | 2015-07-14 |
| JP2011512026A (en) | 2011-04-14 |
| EP2245740B1 (en) | 2014-03-12 |
| EP2245740A2 (en) | 2010-11-03 |
| US8566770B2 (en) | 2013-10-22 |
| EP2685633A2 (en) | 2014-01-15 |
| US20140019921A1 (en) | 2014-01-16 |
| US20120185816A1 (en) | 2012-07-19 |
| JP2015053498A (en) | 2015-03-19 |
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