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CN101916782A - Recessed channel transistor using ferroelectric material and manufacturing method thereof - Google Patents

Recessed channel transistor using ferroelectric material and manufacturing method thereof Download PDF

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CN101916782A
CN101916782A CN 201010251137 CN201010251137A CN101916782A CN 101916782 A CN101916782 A CN 101916782A CN 201010251137 CN201010251137 CN 201010251137 CN 201010251137 A CN201010251137 A CN 201010251137A CN 101916782 A CN101916782 A CN 101916782A
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recessed channel
doping type
type
transistor
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臧松干
王鹏飞
张卫
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Fudan University
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Fudan University
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Abstract

本发明属于快速开关技术领域，具体为一种使用铁电材料的凹陷沟道型晶体管及其制造方法。本发明中，源极为窄禁带宽度，栅介质为铁电材料与氧化硅或高k材料叠层。一方面，窄禁带宽度的源极材料，使得晶体管的驱动电流上升；另一方面，凹陷型沟道的使用，抑制了漏电流的增加；同时，铁电材料的栅介质使得亚阈值电压摆幅变得更小，提高了器件的开关速度。进一步地，本发明还公开了所述半导体场效应晶体管的制造方法。

Figure 201010251137

The invention belongs to the technical field of fast switches, in particular to a recessed channel transistor using ferroelectric materials and a manufacturing method thereof. In the present invention, the source has a narrow forbidden band width, and the gate dielectric is stacked with ferroelectric material and silicon oxide or high-k material. On the one hand, the source material with a narrow band gap increases the driving current of the transistor; on the other hand, the use of the recessed channel suppresses the increase of the leakage current; at the same time, the gate dielectric of the ferroelectric material makes the subthreshold voltage swing The amplitude becomes smaller, which increases the switching speed of the device. Further, the invention also discloses a manufacturing method of the semiconductor field effect transistor.

Figure 201010251137

Description

Use the depression channel type transistor and the manufacture method thereof of ferroelectric material
Technical field
The invention belongs to the high-speed switch technical field, be specifically related to a kind of semiconductor field effect transistor and manufacture method thereof, particularly a kind of depression channel type transistor and manufacture method thereof of using ferroelectric material.
Background technology
The subthreshold value amplitude of oscillation (SS) of Metal-oxide-silicon field-effect transistor (MOSFET) is defined as under the sub-threshold region condition of work, needed grid voltage increment when drain current changes an order of magnitude, and its formula is:
Figure 65365DEST_PATH_IMAGE002
In the formula,
Figure 356407DEST_PATH_IMAGE004
Be grid voltage,
Figure 136144DEST_PATH_IMAGE006
Be surface potential,
Figure 469036DEST_PATH_IMAGE008
Be the surface depletion layer capacitance,
Figure 283409DEST_PATH_IMAGE010
Be the gate oxidation layer capacitance,
Figure 2010102511376100002DEST_PATH_IMAGE011
Be the electric current between the leakage of source.Ideally,
Figure 43554DEST_PATH_IMAGE012
Value be 1, SS at room temperature can reach minimum value 60mv/dec.Be subjected to the restriction of minimum SS value 60mv/dec, the switching speed of the MOSFET under the small size situation is slower.Collision ionization type field effect transistor (IFET) and tunneling field-effect transistor (TFET) can be by changing
Figure 2010102511376100002DEST_PATH_IMAGE013
Value reduce the SS value, and floating boom transistor (SGFET) can be by changing
Figure 687419DEST_PATH_IMAGE014
Value reduce the SS value.
Recently, a kind of field-effect transistor (Fe-FET) that uses ferroelectric material has been carried, its basic structure as shown in Figure 1, this Fe-FET 100 comprises Semiconductor substrate 101, and forms source region 102 and drain region 103 on substrate 101.FET compares with conventional MOS, has added the thin ferroelectric material 105 of one deck between the gate oxide 104 of Fe-FET 100 and the gate electrode 106.Ferroelectric material layer 105 is equivalent to an electric pressure converter, can the amplifying gate pole tension, and so just can make the SS value be lower than minimum 60mv/dec.
Simultaneously, along with constantly dwindling of MOSFET size, the transistor density that unit matrix lists is also more and more higher, and thing followed short-channel effect is also obvious further.Integrated circuit (IC)-components technology node of today has been in about 50 nanometers, and the leakage current between the MOSFET source-drain electrode rises rapidly along with dwindling of channel length.When channel length drops to 30 nanometers when following, be necessary to use novel device to obtain less leakage current, thereby reduce chip power-consumption.
Grid control PNPN transistor and grid-control P-i-N transistor all are the very little transistors of leakage current, can reduce the power consumption of chip greatly.But along with grid-control PNPN field-effect transistor and the transistorized size of grid-control P-i-N narrow down to below 20 nanometers, its leakage current is also dwindling and rise with device.Therefore common grid control PNPN transistor and the transistorized drive current of grid-control P-i-N need to improve its drive current, to improve the performance of integrated grid control PNPN transistor and the transistorized chip of grid-control P-i-N than low 2-3 the order of magnitude of MOSFET.
Summary of the invention
In view of this, the objective of the invention is to propose a kind of semiconductor field effect transistor, this semiconductor field crystalline substance also can suppress the increase of the leakage current and the subthreshold value amplitude of oscillation when improving drive current.And provide the preparation method of this semiconductor field effect transistor.
The semiconductor field effect transistor that the present invention proposes is a kind of depression channel type grid-control P-i-N transistor and grid control PNPN transistor of the SiGe of use source electrode.
Described grid-control P-i-N transistor comprises at least:
Semiconductor substrate with first kind of doping type;
The drain region that on described Semiconductor substrate, forms with second kind of doping type;
The SiGe source region that on described Semiconductor substrate, forms with first kind of doping type;
The recess channel zone that between described drain region and described source region, forms;
The insulation film in the whole recess channel of the covering zone that on described recess channel zone, forms;
The ferroelectric material layer of the described insulation film of covering that on described recess channel zone, forms;
The conductive layer of the described ferroelectric material layer of covering that on described recess channel zone, forms.
Further, described Semiconductor substrate is monocrystalline silicon, polysilicon or is the silicon (SOI) on the insulator.Described insulation film is SiO 2Or high k material, one deck or two-layer.Described ferroelectric material layer is bipolymer P (VDF-TrFE), the strontium bismuth tantalate SBT(SrBi of vinylidene fluoride and trifluoro-ethylene 2Ta 2O 9) or be lead zirconate titanate PZT (PbZr xTi 1-xO 2).Described conductive layer is polysilicon, tungsten metal, titanium nitride, tantalum nitride or metal silicide, perhaps is several mixture among them.Described first kind of doping type is the p type, and second kind of doping type is the n type; Perhaps, described first kind of doping type is the n type, and second kind of doping type is the p type.
Described grid control PNPN transistor comprises at least:
Semiconductor substrate with first kind of doping type;
The drain region that on described Semiconductor substrate, forms with second kind of doping type;
The umbilicate type channel region that a side in close described drain region forms in described Semiconductor substrate;
In the SiGe source region that the non-drain region in the above recess channel zone of described Semiconductor substrate side forms with first kind of doping type;
The SiGe depletion region that under the above SiGe source region of described Semiconductor substrate, forms with second kind of doping type;
The insulation film in the whole recess channel of the covering zone that on described recess channel zone, forms;
The ferroelectric material layer of the described insulation film of covering that on described recess channel zone, forms;
The conductive layer of the described ferroelectric material layer of covering that on described recess channel zone, forms.
Further, described Semiconductor substrate is monocrystalline silicon, polysilicon or is the silicon (SOI) on the insulator.Described insulation film is SiO 2, one deck in the high k material or two-layer.Described ferroelectric material layer is bipolymer P (VDF-TrFE), the strontium bismuth tantalate SBT(SrBi of vinylidene fluoride and trifluoro-ethylene 2Ta 2O 9) or be lead zirconate titanate PZT (PbZr xTi 1-xO 2).Described conductive layer is polysilicon, tungsten metal, titanium nitride, tantalum nitride or metal silicide, perhaps is several mixture among them.Described first kind of doping type is the p type; Second kind of doping type is the n type; Perhaps, described first kind of doping type is the n type; Second kind of doping type is the p type.
The grid-control P-i-N transistor proposed by the invention and the characteristics of grid control PNPN transistor are: on the one hand, source electrode material with narrow band gap makes transistorized drive current rise; On the other hand, the use of umbilicate type raceway groove had both increased the increase that drive current has also suppressed leakage current; Simultaneously, the gate medium of ferroelectric material makes the subthreshold voltage amplitude of oscillation become littler, has improved the switching speed of device.Therefore, grid-control P-i-N transistor proposed by the invention and grid control PNPN transistor also can suppress the increase of the leakage current and the subthreshold value amplitude of oscillation when improving drive current, are specially adapted to the particularly manufacturing of low-power consumption and high-speed chip of integrated circuit (IC) chip.
Further, the invention allows for the manufacture method of above-mentioned grid-control P-i-N transistor and grid control PNPN transistor, comprise the steps:
Semiconductor substrate with first kind of doping type is provided;
Deposit ground floor photoresist;
Mask exposure makes the figure that need mix in the drain region by lithography;
Carry out ion and inject, form the drain region of second kind of doping type;
The ground floor photoresist lift off;
Deposit ground floor insulation film and second layer photoresist;
The mask exposure etching exposes substrate, and etched substrate forms the recess channel zone of device;
Second layer photoresist and ground floor insulation film are peeled off;
Form second layer insulation film, ferroelectric material layer, ground floor conductive film and the 3rd layer photoetching glue successively;
The mask exposure etching forms the grid structure of device;
The 3rd layer photoetching glue is peeled off;
Deposit forms three-layer insulated film and the 4th layer photoetching glue;
Mask exposure makes the figure that needs to form the source region by lithography;
The 3rd layer, second layer insulation film are carried out etching and expose silicon substrate;
The reactive ion etching silicon substrate;
The 4th layer photoetching glue is peeled off;
Continuation is carried out isotropic etching to silicon substrate;
Form epitaxial loayer by epitaxy technique;
The 3rd layer of etching, second layer insulation film form grid curb wall and expose the drain region;
The 4th layer of insulation film of deposit and layer 5 photoresist;
The mask exposure etching forms contact hole;
The layer 5 photoresist lift off;
Deposit second layer conductive film forms electrode.
Described Semiconductor substrate is monocrystalline silicon, polysilicon or is the silicon (SOI) on the insulator.Described ground floor, the 3rd layer, the 4th layer insulation film are SiO 2, Si 3N 4It perhaps is the insulating material that mixes mutually between them.Described second layer insulation film is SiO 2, one deck in the high k material or two-layer.Described ferroelectric material layer is bipolymer P (VDF-TrFE), the strontium bismuth tantalate SBT(SrBi of vinylidene fluoride and trifluoro-ethylene 2Ta 2O 9) or be PZT lead zirconate titanate (PbZr xTi 1-xO 2).Described ground floor conductive film is polysilicon, tungsten metal, titanium nitride, tantalum nitride or metal silicide, perhaps is several mixture among them.Described second layer conductive film is metallic aluminium, tungsten or is other metallic conduction material.Described first kind of doping type is the n type; Second kind of doping type p type; Perhaps, described first kind of doping type is the p type; Second kind of doping type n type.
It should be noted that, in the transistorized preparation process, if when carrying out epitaxy technique, only form when having the SiGe source region of first kind of doping type, SiGe source region, substrate zone and drain region constitute a p-i-n or n-i-p structure, and Zhi Bei transistor is described grid-control P-i-N transistor like this.As when carrying out epitaxy technique, form SiGe source region with first kind of doping type and SiGe depletion region simultaneously with second kind of doping type, then SiGe source region, SiGe depletion region, substrate zone and drain region can constitute a p-n-p-n knot or n-p-n-p junction structure, and Zhi Bei transistor is described grid control PNPN transistor like this.
One aspect of the present invention, the use of source electrode material with narrow band gap makes transistorized drive current rise; On the other hand, the use of umbilicate type raceway groove has suppressed the increase of leakage current; Simultaneously, the gate medium of ferroelectric material makes the subthreshold voltage amplitude of oscillation become littler, has improved the switching speed of device.Be the present invention when improving drive current, also can suppress the increase of the leakage current and the subthreshold value amplitude of oscillation.
Description of drawings
Fig. 1 for prior art a kind of sectional view that uses the semiconductor field effect transistor of ferroelectric material.
Fig. 2 is the sectional view of the transistorized embodiment of grid-control P-i-N provided by the invention.
Fig. 3 a to Fig. 3 g is an embodiment process chart of the transistorized manufacture method of the P-i-N of grid-control as shown in Figure 2 provided by the invention.
Fig. 4 a to Fig. 4 c is an embodiment process chart of the manufacture method of grid control PNPN transistor provided by the invention.
Embodiment
Below with reference to accompanying drawings illustrative embodiments of the present invention is elaborated.In the drawings, for convenience of description, amplified the thickness in layer and zone, shown in size do not represent actual size.Reference diagram is the schematic diagram of idealized embodiment of the present invention, and embodiment shown in the present should not be considered to only limit to the given shape in zone shown in the figure, but comprises resulting shape, the deviation that causes such as manufacturing.For example the curve that obtains of etching has crooked or mellow and full characteristics usually, but in embodiments of the present invention, all represents with rectangle, and the expression among the figure is schematically, but this should not be considered to limit the scope of the invention.Simultaneously in the following description, employed term substrate can be understood as and comprises the just Semiconductor substrate in processes, may comprise other prepared thin layer thereon.
Embodiment 1: grid-control P-i-N transistor
Fig. 2 is the transistorized embodiment of grid-control P-i-N provided by the present invention, and it is the sectional view along this device channel length direction.This grid-control P-i-N transistor comprises a substrate zone, a source region, a drain region and a gate stack district.Substrate zone 200a, 200b are the silicon layer that contains light dope n type or p type, or are insulating oxide, and substrate zone 200c is the silicon layer that contains light dope n type or p type.The SiGe material of low energy gap width is adopted in source region 212, and the doping type in source region 212 is opposite with the doping type in drain region 202 usually, and identical with the doping type of substrate zone 200c.The gate stack district comprises insulating barrier 206, ferroelectric material layer 207, conductor layer 208 and conductor layer 209, and insulating barrier 206 is SiO 2, one deck in the high k material or two-layer, ferroelectric material layer 207 is preferably P (VDF-TrFE), conductor layer 208 is a metal level, the polysilicon of conductor layer 209 for mixing.The abutment wall 210 in gate stack district is an insulator, such as being Si 3N 4, they are with other conductor layer insulation of grid region conductor layer and described device.Insulating barrier 213 is passivation layers of this device, and they separate described device and other device, and protects described device not to be subjected to the influence of external environment.Conductor layer the 214,215, the 216th, metal material is respectively as the electrode in this device source region, grid region and drain region.
Semiconductor device disclosed in this invention can be by a lot of method manufacturings, the following stated be an embodiment of the transistorized manufacture method of grid-control P-i-N as shown in Figure 2 disclosed in this invention.
Although these figure are not the actual size that reflects device of entirely accurate, their zones that still has been complete reflection and form mutual alignment between the structure, particularly form between the structure up and down and neighbouring relations.
At first, deposit one deck photoresist 201 on the Semiconductor substrate that provides, then mask, expose, make by lithography the figure that need mix in the drain region, then carry out n type foreign ion and inject formation drain region 202, shown in Fig. 3 a, wherein, substrate 200a and 200b are the silicon layer that contains light dope n type or p type impurity, or are insulating oxide; Substrate 200c is the silicon layer of light dope p type impurity.
Next, divest photoresist 201, the film of deposit layer of silicon dioxide again 203, the deposit photoresist 204 then, last mask, exposure, etching form the recess channel zone 205 of device, and shown in Fig. 3 b, wherein silica membrane 203 is as hard mask, be in order to etch the lateral length in recess channel zone and recess channel zone more accurately, the lithographic method that etching process adopts dry etching to combine with wet etching.
Next, divest photoresist 204 earlier, etch away silica membrane 203 again, form one deck insulation film 206 then, insulation film 206 comprises the silica membrane of one deck heat growth and the high k material layer that one deck deposit forms.Next deposit one deck ferroelectric material layer 207, ferroelectric material is preferably P (VDF-TrFE).Next, form layer of metal layer 208 and one deck polysilicon membrane 209 successively, deposit one deck photoresist again, mask, exposure, etching form the grid structure of device then, and the structure behind the stripping photoresist is shown in Fig. 3 c.Metal level 208 is Al, TiN or is TaN.
Next, deposit one deck Si 3N 4The photoresist that film 210 and one deck are new, then mask, expose, make by lithography the figure that need to form the source region, then to Si 3N 4Film 210 and insulation film 206 carry out etching and expose silicon substrate, again by the reactive ion etching silicon substrate, silicon substrate are carried out the zone that isotropic etching is formed for forming the source region after divesting photoresist, and structure is shown in Fig. 3 d.
Next, form the SiGe source region 212 that one deck has p type doping type by epitaxy technique, its structure is shown in Fig. 3 e.
Next, etching Si 3N 4Film 210 and insulation film 206 form complete grid region sidewall structure, and expose drain region 202, shown in Fig. 3 f.
At last, deposit one deck insulation film 213, insulating material can or be a silicon nitride for silica.Deposit one deck photoresist again, mask, exposure, etching form contact hole then.After divesting photoresist, the deposit layer of metal can be aluminium or tungsten, and etching forms electrode 214,215 and 216 then, and its structure is shown in Fig. 3 g.
Embodiment 2: grid control PNPN transistor
Employing and the leading portion manufacturing process (Fig. 3 a to Fig. 3 d) that grid-control P-i-N transistor is identical as mentioned above, at first form the semiconductor structure shown in Fig. 4 a, wherein, substrate zone 300a, 300b are the silicon layer that contains light dope n type or p type, or be insulating oxide, substrate zone 300c is the silicon layer that contains light dope n type or p type.Shown in 301 be n type drain region.Shown in 302 for comprising the insulation film of a layer of silicon dioxide and a floor height k material layer.Shown in 303 be ferroelectric material layer P (VDF-TrFE).Shown in 304 be metal level.Shown in 305 polysilicons for mixing.Shown in 306 be Si 3N 4Film.
Next, by epitaxy technique, form SiGe depletion region 307 and SiGe source region 308 successively, shown in Fig. 4 b.
At last, etching Si 3N 4Film forms grid curb wall, and etching insulation film 302 exposes drain region 301, and the deposit insulation film 309 then, and insulating material can or be a silicon nitride for silica.Deposit one deck photoresist again, the method by mask, exposure, etching forms contact hole then.After divesting photoresist, the deposit layer of metal can be aluminium or tungsten, and etching forms electrode 310,311 and 312 then, and the final grid control PNPN transistor structure that forms is shown in Fig. 4 c.
As mentioned above, under the situation that does not depart from spirit and scope of the invention, can also constitute many very embodiment of big difference that have.Should be appreciated that except as defined by the appended claims, the invention is not restricted at the instantiation described in the specification.

Claims (16)

1.一种使用铁电材料的凹陷沟道型晶体管，包括使用SiGe源极的凹陷沟道型栅控P-i-N晶体管和栅控PNPN晶体管，其特征在于：1. A recessed channel type transistor using ferroelectric material, comprising a recessed channel type gate-controlled P-i-N transistor and a gate-controlled PNPN transistor using a SiGe source electrode, characterized in that: 所述的栅控P-i-N晶体管至少包括：The gate-controlled P-i-N transistor at least includes: 一个具有第一种掺杂类型的半导体衬底；a semiconductor substrate having a first doping type; 在所述半导体衬底上形成的具有第二种掺杂类型的漏区；a drain region having a second doping type formed on the semiconductor substrate; 在所述半导体衬底上形成的具有第一种掺杂类型的SiGe源区；a SiGe source region having a first doping type formed on the semiconductor substrate; 位于所述漏区与所述源区之间形成的凹陷沟道区域；a recessed channel region formed between the drain region and the source region; 在所述凹陷沟道区域之上形成的覆盖整个凹陷沟道区域的绝缘薄膜；an insulating film covering the entire recessed channel region formed over the recessed channel region; 在所述凹陷沟道区域之上形成的覆盖所述绝缘薄膜的铁电材料层；a layer of ferroelectric material covering the insulating film formed over the recessed channel region; 在所述凹陷沟道区域之上形成的覆盖所述铁电材料层的导电层；a conductive layer overlying the layer of ferroelectric material formed over the recessed channel region; 所述的栅控PNPN晶体管至少包括：The gate-controlled PNPN transistor at least includes: 一个具有第一种掺杂类型的半导体衬底；a semiconductor substrate having a first doping type; 在所述半导体衬底上形成的具有第二种掺杂类型的漏区；a drain region having a second doping type formed on the semiconductor substrate; 在所述半导体衬底内靠近所述漏区的一侧形成的一个凹陷型沟道区域；a recessed channel region formed in the semiconductor substrate on a side close to the drain region; 在所述半导体衬底上所述凹陷沟道区域的非漏区侧形成的具有第一种掺杂类型的SiGe源区；a SiGe source region having a first doping type formed on the non-drain region side of the recessed channel region on the semiconductor substrate; 在所述半导体衬底上所述SiGe源区之下形成的具有第二种掺杂类型的SiGe耗尽区；a SiGe depletion region having a second doping type formed under the SiGe source region on the semiconductor substrate; 在所述凹陷沟道区域之上形成的覆盖整个凹陷沟道区域的绝缘薄膜；an insulating film covering the entire recessed channel region formed over the recessed channel region; 在所述凹陷沟道区域之上形成的覆盖所述绝缘薄膜的铁电材料层；a layer of ferroelectric material covering the insulating film formed over the recessed channel region; 在所述凹陷沟道区域之上形成的覆盖所述铁电材料层的导电层。A conductive layer overlying the layer of ferroelectric material is formed over the recessed channel region. 2.根据权利要求1所述的使用铁电材料的凹陷沟道型晶体管，其特征在于，所述的半导体衬底为单晶硅、多晶硅或者为绝缘体上的硅。2 . The recessed channel transistor using ferroelectric material according to claim 1 , wherein the semiconductor substrate is single crystal silicon, polycrystalline silicon or silicon on insulator. 3.根据权利要求1所述的使用铁电材料的凹陷沟道型晶体管，其特征在于，所述的绝缘薄膜为SiO2、高k材料中的一层或两层。3 . The recessed channel transistor using ferroelectric material according to claim 1 , wherein the insulating film is one or two layers of SiO 2 and high-k material. 4 . 4.根据权利要求1所述的使用铁电材料的凹陷沟道型晶体管，其特征在于，所述的铁电材料层为偏二氟乙烯与三氟乙烯的二元共聚物、钽酸锶铋或者为锆钛酸铅。4. The recessed channel transistor using a ferroelectric material according to claim 1, wherein the ferroelectric material layer is a binary copolymer of vinylidene fluoride and vinyl trifluoride, strontium bismuth tantalate Or lead zirconate titanate. 5.根据权利要求1所述的使用铁电材料的凹陷沟道型晶体管，其特征在于，所述的导电层为多晶硅、钨金属、氮化钛、氮化钽或金属硅化物，或者为它们之中几种的混合物。5. The recessed channel transistor using ferroelectric material according to claim 1, wherein the conductive layer is polysilicon, tungsten metal, titanium nitride, tantalum nitride or metal silicide, or is their A mixture of several of them. 6.根据权利要求1所述的使用铁电材料的凹陷沟道型晶体管，其特征在于，所述的第一种掺杂类型为p型，第二种掺杂类型为n型；或者所述的第一种掺杂类型为n型，第二种掺杂类型为p型。6. The recessed channel transistor using a ferroelectric material according to claim 1, wherein the first doping type is p-type, and the second doping type is n-type; or the The first doping type is n-type, and the second doping type is p-type. 7.一种半导体场效应晶体管的制造方法，其特征在于具体步骤包括：7. A method for manufacturing a semiconductor field effect transistor, characterized in that the specific steps include: 提供一个具有第一种掺杂类型的半导体衬底；providing a semiconductor substrate having a first doping type; 进行离子注入，形成第二种掺杂类型的漏区；performing ion implantation to form a drain region of the second doping type; 淀积第一层绝缘薄膜；Depositing the first layer of insulating film; 刻蚀所述第一层绝缘薄膜与半导体衬底形成器件的凹陷沟道区域；Etching the first insulating film and the semiconductor substrate to form a recessed channel region of the device; 剥除剩余的第一层绝缘薄膜；Peel off the remaining first layer of insulating film; 依次形成第二层绝缘薄膜、铁电材料层、第一层导电薄膜；Form the second layer of insulating film, ferroelectric material layer, and the first layer of conductive film in sequence; 掩膜曝光刻蚀形成器件的栅极结构；Mask exposure etching to form the gate structure of the device; 淀积第三层绝缘薄膜；Depositing a third layer of insulating film; 掩膜曝光刻蚀暴露出硅衬底；Mask exposure etching exposes the silicon substrate; 反应离子刻蚀硅衬底；Reactive ion etching of silicon substrates; 继续对硅衬底进行各向同性刻蚀；Continue to perform isotropic etching on the silicon substrate; 通过外延工艺形成外延层；forming an epitaxial layer by an epitaxial process; 刻蚀第三层、第二层绝缘薄膜形成栅极侧墙，并暴露出漏区；Etching the third layer and the second layer of insulating film to form gate sidewalls and expose the drain region; 淀积第四层绝缘薄膜；Depositing a fourth layer of insulating film; 刻蚀第四层绝缘薄膜形成接触孔；Etching the fourth insulating film to form a contact hole; 淀积第二层导电薄膜形成电极。A second layer of conductive film is deposited to form electrodes. 8.根据权利要求7所述的制造方法，其特征在于，所述的半导体衬底为单晶硅、多晶硅或者为绝缘体上的硅。8. The manufacturing method according to claim 7, wherein the semiconductor substrate is single crystal silicon, polycrystalline silicon or silicon on insulator. 9.根据权利要求7所述的制造方法，其特征在于，所述的第一层、第三层、第四层绝缘薄膜为SiO2、Si3N4或者为它们之间相混合的绝缘材料。9. The manufacturing method according to claim 7, characterized in that, the insulating films of the first layer, the third layer, and the fourth layer are SiO 2 , Si 3 N 4 or insulating materials mixed therebetween . 10.根据权利要求7所述的制造方法，其特征在于，所述的第二层绝缘薄膜为SiO2、高k材料中的一层或两层。10 . The manufacturing method according to claim 7 , wherein the second insulating film is one or two layers of SiO 2 and high-k materials. 11 . 11.根据权利要求7所述的制造方法，其特征在于，所述的铁电材料层为偏二氟乙烯与三氟乙烯的二元共聚物、钽酸锶铋或者为锆钛酸铅。11. The manufacturing method according to claim 7, wherein the ferroelectric material layer is a binary copolymer of vinylidene fluoride and trifluoroethylene, strontium bismuth tantalate or lead zirconate titanate. 12.根据权利要求7所述的制造方法，其特征在于，所述的第一层导电薄膜为多晶硅、钨金属、氮化钛、氮化钽或金属硅化物，或者为它们之中几种的混合物。12. The manufacturing method according to claim 7, characterized in that, the first layer of conductive film is polysilicon, tungsten metal, titanium nitride, tantalum nitride or metal silicide, or several of them mixture. 13.根据权利要求7所述的制造方法，其特征在于，所述的第二层导电薄膜为金属铝或金属钨。13. The manufacturing method according to claim 7, characterized in that, the second conductive film is metal aluminum or metal tungsten. 14.根据权利要求7所述的制造方法，其特征在于，所述的外延层仅具有第一种掺杂类型的SiGe源区，则制得如权利要求1所述的栅控P-i-N晶体管。14. The manufacturing method according to claim 7, wherein the epitaxial layer only has the SiGe source region of the first doping type, and the gate-controlled P-i-N transistor as claimed in claim 1 is manufactured. 15.根据权利要求7所述的制造方法，其特征在于，所述的外延层包含具有第一种掺杂类型的SiGe源区和具有第二种掺杂类型的SiGe耗尽区，则制得如权利要求1所述的栅控PNPN晶体管。15. The manufacturing method according to claim 7, wherein the epitaxial layer comprises a SiGe source region with the first doping type and a SiGe depletion region with the second doping type, then the obtained The gate-controlled PNPN transistor as claimed in claim 1. 16.根据权利要求7所述的制造方法，其特征在于，所述的第一种掺杂类型为n型，第二种掺杂类型p型；或者，所述的第一种掺杂类型为p型，第二种掺杂类型n型。16. The manufacturing method according to claim 7, wherein the first doping type is n-type, and the second doping type is p-type; or, the first doping type is p-type, the second doping type n-type.
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