CN101916754B - Via hole and via hole forming method and via hole filling method - Google Patents

Abstract

An electronic or micromechanical device has a first surface (11) and a second surface (12) and a via extending through the device from the first surface to the second surface. The through-hole includes an integrally formed first portion (84, 86), second portion (82), and third portion (88). The first portion (84, 86) extends from the first surface (11) to the second surface (12). The second portion (82) extends over a portion of the first surface (11) of the device. A third portion (88) extends over a portion of the second surface (12) of the device. Preferably, the first portion includes first and second features, the second feature extending across the active region of the device and being narrower in width than the first feature. Also, a method of forming and filling the via is disclosed.

Description

Via hole and via hole forming method and via hole filling method

【Technical field】

The present invention relates to a through hole, a method for forming the through hole and a method for filling the through hole, in particular but not limited to a through silicon via (TSV).

【Background technique】

Electronic devices, especially portable devices such as mobile phones, are becoming more and more miniaturized, but at the same time can provide more and more functions. There is a need to integrate multi-function chips without increasing the size of the device and keep it small physical dimension. In a 2D structure, increasing the number of electronic components will inevitably increase the size, which cannot achieve these goals. Therefore, 3D packaging is increasingly used in order to provide more functionality and higher component density, but with a smaller appearance. size.

In a 3D structure, electronic components, such as semiconductor chips with various active IC devices, may be multilayer stacked structures. Traditionally, wire bonding (such as U.S. Patent 6,933,172) is used to establish electrical interconnections between chips, but wire bonding requires large in-plane size and out-of-plane size. -of-plane size), inconsistent with the goal of maximizing component density. To electrically connect components in different layers, through-silicon via (TSV) technology can be used to provide electrical interconnection and provide mechanical support. In TSV technology, a through hole is made on a silicon chip with different active IC devices or other devices, and the through hole is filled with metal such as copper, gold, tungsten, solder, or a highly doped Semiconductor materials such as polysilicon. Thus, TSVs are able to connect bond pads on the top surface of the component to bond pads on the bottom surface of the component. Therefore, a plurality of elements having such through holes are laminated and bonded together. Also importantly, the electrical paths of the electronics can be shortened, resulting in faster operation.

Although TSVs are frequently applied to electronic components, they can also be applied to micromechanical components such as MEMS devices.

Figures 1(a) to (g) show the steps of a conventional method of forming a TSV for a NAND flash wafer.

In the step of Figure 1(a), an electronic device (in this example a memory wafer) is provided. The wafer has a first "upper" surface 11 and a second "lower" surface 12 opposite the first surface. The wafer comprises a silicon region 20 in the upper part of the wafer and an active region 30 in the lower part of the wafer. The active area includes a pad 40 . More specifically, in the depicted example, active region 40 includes a plurality of electrical traces and/or conductive lines embedded in an isolation layer (e.g., silicon oxide) between silicon region 20 and pad 40. within 34. In the depicted example, active region 30 includes a plurality of dielectric lines 32, polysilicon lines 36, and M4 lines 38 embedded in silicon oxide spacer 34 between silicon layer 20 and bonding pad 40 . The pad is formed of metal and has a plurality of protrusions 39 which protrude upward into the silicon oxide region. The protruding portions 39 can have a particular configuration, in the example described these upward protruding portions are T-shaped, the intersection of the T being at the distal end of the pad.

1(b) to (f) describe a method of forming a via hole. In the step of FIG. 1( b ), a layer of photoresist layer 50 is added to protect device components not to be etched, and a part of the silicon layer 20 and a part of the polysilicon layer 32 are removed by etching. In the step of FIG. 1(c), a part of the spacer layer 34 is removed by etching. In the step of FIG. 1( d ), a part of the barrier metal layer M4 is removed by etching. In the step of FIG. 1(e), a part of the silicon oxide isolation layer is removed by etching. As shown in Figure 1(b) to (e), different layers are removed in different etching steps. Since the material removed is different, different etching processes are required. Furthermore, in each step, the etch width is almost the same, so that the vias have an almost uniform width. The fully formed via 60 is shown in Figure 1(e). It extends from the top surface 11 of the device down to the pad 40 and has a uniform width or diameter. However, via 60 does not extend through pad 40 .

In the step of FIG. 1( f ), a spacer layer 70 comprising a dielectric material is deposited inside the via 60 . The isolation layer 70 covers the inner sidewalls of the via holes and covers the top surface 11 of the silicon layer 20 . In the step of FIG. 1(g), electroplating is performed to fill the vias with metal 82, 84, which may typically be copper. Metal layers 82, 84 are solid and form a T-shape. It includes a vertical portion 84 within the via and a horizontal or “intersection” portion 82 extending above the top surface 11 of the device. The bottom of the vertical portion of plated metal 84 is mechanically and electrically connected to pad 40, but is not integrally formed with the pad. That is, the via does not extend through the pad 40 and does not reach the second surface 12 of the device. Although both the pad 40 and the plating layers 82, 84 are made of copper, they are not integral. They are separate components, separate components with different grain structures formed by different fabrication methods (since pad 40 is not formed by electroplating).

Forming TSVs using the above method is a time-consuming process because etching needs to be performed in several different steps. Also, some etching steps should be performed in different chambers or after evacuating the room to avoid contamination. This increases the complexity and time required for the method, thereby increasing manufacturing costs. Furthermore, the methods described above may not always securely attach the plating layers 82, 84 to the pad or via sidewalls. Thus, problems can arise if stress is applied to the device during fabrication or use. Therefore, it is desirable to find a faster and more cost-effective method of forming vias that also preserves the mechanical integrity of the device.

【Overview of Invention】

A first aspect of the present invention is to provide an electronic or micromechanical device having first and second surfaces and a through hole extending through the device from the first surface to the second surface, the through hole typically being Type I. The Type I feature of the via helps to fasten the via to the device.

Preferably, the via comprises an integrally formed layer of conductive material (eg metal). On top of the via, above the second surface of the device, there may be another conductive layer, and there may be a barrier layer between the via and the further conductive layer. The top and bottom of the I-type (or another conductive layer) can form electrical contacts for connecting the device to another device above or below the device. Solder can be added on top of the contacts.

A second aspect of the present invention is to provide an electronic or micromechanical device having first and second surfaces and a through hole extending through the device from the first surface to the second surface, the through hole comprising an integral shaped first, second and third portions, the first portion extending from the first surface to the second surface, the second portion extending over a portion of the first surface of the device, and the third portion extending over a portion of the second surface of the device superior. This configuration helps to fasten the via to the device.

Thus, the via includes an integrally formed conductive layer. On top of the via, above the first portion of the via, there may be another conductive layer, and there may be a barrier layer between the via and the further conductive layer.

The second and first portions of the via (or another conductive layer) may form electrical contacts for connecting the device to another device above or below the device. Solder can be added on top of the contacts.

The vias may also include one or more barrier layers, filler layers, sputtered metal layers, and dielectric layers, each extending through the inactive region and at least a portion of the active region of the device.

A third aspect of the present invention is to provide a method of forming a via extending through an electronic or micromechanical device having a first surface and a second surface, the method comprising: forming a via extending from the first surface a surface extending through the device to a second surface; electroplating to add an integrally formed metal layer extending from said first surface through said via to said second surface; said integrally formed metal layer A portion extending over the first surface of the device portion and a portion extending over the second surface of the device portion are included.

A fourth aspect of the present invention is to provide an electronic or micromechanical device having first and second surfaces and a through hole extending through the device from the first surface to the second surface, wherein the device has a non- An active layer and an active layer, wherein a first portion of the via extends through the inactive layer, a second portion of the via extends mainly through the active layer, and the width of the first portion of the via is wider than that of the second portion of the via. This helps reduce damage to the active layer of the device since the second portion of the via is narrower.

The first and/or second portion of the through-hole may be tapered with a drop width in the direction from the first surface of the device to the second surface of the device. This facilitates the use of bottom-up plating during fabrication of the device.

In a fifth aspect, the present invention provides a method of forming a via extending through an electronic or micromechanical device, the method comprising: forming a first portion of the via by etching; and forming a second portion of the via by laser drilling. two parts. Since there is only one etch step and the laser is only used for the second step, but it does not have to fully punch through the device, the process is fairly quick. Preferably, the width of the second removed portion is narrower than that of the first portion.

Preferably, the device has first and second opposing surfaces, and preferably, the via extends through the device from the first surface to the second surface. In particular, preferably, the via extends through the active area of the device, which may include a bond pad.

A sixth aspect of the present invention is to provide a stacked assembly comprising a first device mounted on top of a second device, at least one of said first and second devices being in accordance with the first, second or fourth aspects of the invention device, or a device manufactured in accordance with the third or fifth aspect of the present invention.

【Description of drawings】

1(a) to (g) show the steps of a conventional method of forming a TSV.

2( a ) to ( d ) are schematic structural diagrams of through holes according to the embodiment of the present invention.

Figure 3 shows a via in detail.

Figures 4(a) to (d) show cross-sectional views of lower portions of vias in various embodiments of the present invention.

5 to 19 show the steps of the method of forming the via hole of FIG. 3; and

Figure 20 shows a pair of stacked devices with vias according to one embodiment of the present invention.

【Detailed description of the invention】

2( a ) to ( d ) are schematic structural diagrams of through holes according to the embodiment of the present invention. Vias extend through one substrate. The substrate can be an electronic device or a mechanical device. For example, the device may be a memory chip, a processor, or a MEMs device, but the invention is not limited to these examples. The substrate typically contains silicon.

The vias extend through the substrate from a first surface 11 to an opposite second surface 12 . Vias are usually Type I. It comprises a metal layer with a first part 84, 86, a second part 82 and a third part 88 integrally formed by electroplating. The second portion 82 extends to cover the first surface 11 of the substrate. The first portion 84, 86 extends through the substrate and the third portion 88 extends above the second surface of the substrate. This provides mechanical integrity of the structure as the three parts of the through hole are integrally formed as one part. Since the plated parts of the through holes are integrally formed together, they have almost the same grain size (grain size), which is contrary to the structure of FIG. 1, although the pad 40 and the via 84 are made of the same material, they are not integrally formed, and the pad and the via 84 have different internal structures and grain sizes. In comparison, the structure in FIG. 1( g ) is not strong enough because the pad 40 may separate from the via 84 .

In Figure 2(a)-(d) and Figure 3, the "I-shape" of the via makes the via tightly connected to the substrate and pad. Since the second and third portions of the via are on opposite sides of the substrate and are integrally formed with the first portion of the via, the mechanical integrity of the structure is enhanced.

All three parts of the via are a metal layer, which is usually copper because copper is low cost and conducts electricity well. However, the present invention is not limited to copper and any suitable metal may be used. For example, gold and tungsten are possible substitutes, or others will be apparent to those skilled in the art.

The first portion 84 , 86 of the via extends through the device from the first surface 11 to the second surface 12 . The first part of the via consists of two parts. The first member 84 is wider than the second member 86 . Wider means that the first part has a larger diameter or a larger cross-sectional area (in a direction perpendicular to the vertical length of the through hole extending from the first surface 11 to the second surface 12 ). From the width in the direction from left to right in FIG. 2( a ), a size comparison between the two parts can be seen. The first feature 84 extends through the inactive region 20 of the device, while the second feature 86 extends primarily through the active region 30 of the device. The active area may include a pad. Since the cross-sectional area of the second member 86 extending through the active area is relatively smaller than the cross-sectional area of the first member 84, damage to the active area 30 is minimized.

One or both of the first and second parts may be tapered. Preferably, the first part 84 is tapered, being wider (has a larger cross-sectional area) at the end near the first surface 11 than at the end near the active region 30 . Preferably, the second member 86 is tapered, being narrower (lower cross-sectional area) at the end near the second surface 12 than at the end near the inactive region 20 .

In FIGS. 2( d ) and 3 , as described above, the first member 84 and the second member 86 are tapered. This tapered shape has two main advantages in the fabrication process. A first advantage is that the bottom of the via (closer to the surface 12 ) can be filled more quickly when electroplating because less metal is required. This facilitates a bottom-up plating process. A second advantage is that larger openings at the junction between the active and inactive layers and sloped via sidewalls in region 30 can enhance the uniformity of the sputtered thin film metal 120 .

Such a taper is not required and other configurations are possible in which neither or only one of the first and second parts is tapered. Refer to Figures 2(a) to 2(c). In Figure 2(a), neither part is tapered. In Figure 2(b), the second member 86 is tapered. In Figure 2(c), the first member 84 is tapered.

Preferably, the via comprises a layer of plated metal surrounding a polymer filler. This metal-polymer-metal structure helps to compensate for the coefficient of thermal expansion of the substrate inactive region 20 (typically formed from silicon) and the plated metal layer (typically formed from copper). Typically, the coefficient of thermal expansion of the plated metal is much greater than the coefficient of thermal expansion of the inactive region 20 . Simple fillers help reduce problems caused by differences in coefficient of thermal expansion, first by reducing the number of plating layers, and second by having an intermediate coefficient of thermal expansion of its own. In addition, the filler layer has a certain degree of resilience. Thus, if the plating expands due to temperature changes, this expansion can be accommodated by "squeezing" the filler layer. In this way, additional stress that could lead to cracking or damage to the inactive and active layers of the device can be minimized or avoided.

FIG. 3 shows a schematic diagram of a detailed structure of a through hole of the present invention in detail. The vias extend through a device substrate from the first surface 11 to the second surface 12 . The device includes an inactive silicon layer 20 and an active layer 30 . The active layer 30 includes a bonding pad 40 and a silicon oxide isolation layer 34 between the bonding pad 40 and the inactive layer 20 . A number of traces, conductive paths, and other structures are embedded therein and extend through isolation layer 34 . In the depicted example, these traces include dielectric lines 32 , polysilicon lines 36 and M4 lines 38 . A plurality of structures 39 protrude from pad 40 . These various structures in the active layer can be used to transmit electrical signals from the pad to a logic gate or other parts of the device. This structure can form an ESD (electrostatic discharge) protection structure.

The via includes a first, wider portion extending through the inactive layer, and a second, narrower portion extending through the active layer. Since the second part is narrower, it causes little damage to the various structures in the active layer.

The various layers of the via will now be described from the outside to the inside. The via has an outer polymer layer 100 , a barrier layer 110 , a sputtered metal (eg copper) layer 120 , a plated (eg copper) layer 84 and an inner polymer layer 140 . Each layer has a first feature extending through the inactive area of the device and a second narrower feature extending through the active area of the device. In the example described, the first and second parts are tapered, but this is not required and may be non-tapered or only partially tapered as shown in Figures 2(a) to (c).

The vias are generally Type I, and the plating has a first portion 84, 86, a second portion 82 and a third portion 88, as described above. These parts are integrally formed. The upper surface 11 of the device is covered with a feature 95 comprising a barrier layer 95a, a sputtered metal layer 95b, a plating layer 95c and solder 95d.

Preferably, the second part of the first portion of the through hole 86 comprises a single "pillar" extending through the active area. As shown in Fig. 3 and Fig. 4(a), Fig. 4(a) is a cross section along line A-A of Fig. 3 . For ease of description, the cross-section shows only the plated portion of the via 86 and the active area 30 . As shown in Fig. 4(a), preferably, the through hole has a circular cross-section. However, cross-sections of different shapes are also possible, as shown in Fig. 4(c) or (d). Alternatively, there may be multiple "pillars" extending down through the active area, as shown at 86a to 86d in Figure 4(b).

A method of forming via holes will now be described.

Figure 5 shows the electronic device wafer prior to via formation. It includes the same components as previously described and uses the same reference numbers. In the example described, the device is a memory wafer, but the method can also be applied to processors, other electronic and micromechanical devices.

In FIGS. 6 and 7, the via holes are formed in two steps. In the first step, as shown in FIG. 6, a part of the inactive layer is removed by an etching method such as RIE (Reactive Ion Etching). Only one etching process is required. Preferably, the through hole is tapered, being wider at the top (closer to the first surface 11 ), although this is not required. In FIG. 7, the second portion of the via is formed by laser drilling. That is, the active area is drilled with a laser. The size of the second portion of the through hole is determined by the size of the adjustable laser beam that drills the hole. As a result, the via (comprising the first portion 60a and the second portion 60b ) extends through the device from the first surface 11 to the second surface 12 . A photoresist 101 is added to the second surface 12 of the device to protect the surface of the bond pad 40 .

In the step of FIG. 8, an insulating layer 100 is deposited on the inner sidewalls of the via holes. The insulating layer may comprise a polymer material. In FIG. 9, a thin metal layer comprising a barrier layer 110 and a sputtered layer 120 is deposited inside the via. In Figure 10, an electroplating layer is added. A bottom-up electroplating process is used. Generally, "bottom-up" plating means that the deposition rate of the plated metal at the bottom of the via (closer to the surface 12 ) will be faster than the upper portion of the via. Thus, the part near surface 12 (active area) is first closed by the plated metal, while the part near surface 11 may remain open after electroplating. Compared to other plating methods such as conformal plating or top-down plating methods, the bottom-up process has the advantage that voids are less likely to form in the through-holes. Furthermore, in this example, no special chemistry is required at the top to induce bottom-up plating or to suppress plating, and the second portion 60b of the via is narrower than the first portion 60a, naturally using a bottom-up plating process because The "bottom" part fills more quickly. Electroplating forms an electroplated layer, which is generally I-type, comprising integrally formed first parts 84 , 86 , second parts 82 and third parts 88 . The second part extends over the first surface 11 of the device, the first part extends through the device, and the third part extends over the second surface 12 of the device.

In FIG. 11 , a filler is added to form an "inner" polymer layer 140 . Thus, the via has a metal-polymer-metal structure because the inner polymer layer is surrounded by the plated metal layer.

In FIG. 12 , a barrier layer 95 a and sputtered metal layer 95 b are added to the first surface 11 . In FIG. 13 , a layer of photoresist 102 is spin-coated onto the first and second surfaces 11 , 12 . In Figure 14, another electroplated layer 95c is added on top of the sputtered metal layer 95b. In FIG. 15, solder 95d is added on top of plating 95c. In FIG. 16 the photoresist is removed from the first surface 11 . In FIG. 17, unwanted portions of the upper thin metal layer (to the sides of the vias) are etched away. In FIG. 18 , the photoresist is removed from the second surface 12 . In FIG. 19, on top of the first surface 11, solder is filled around the thin metal layers 95a-c.

Accordingly, the device 20, 30 has a through via (TSV) extending through it. The third part 88 of the first plating layer and the other plating layer 95c of the vias can be used as electrical contacts for connecting the device to another device above or below the device 20 , 30 . Typically solder 95d will be applied to the other plating layer, and solder 250 may also be applied to the third component 88 to facilitate electrical connection. Figure 20 shows two stacked devices.

The first device has an inactive layer 200a and an active layer 200b. The second device has an inactive layer 300a and an active layer 300b. A first via 210 extends through the left side of the first device and connects to a second via 220 which extends through the left side of the second device. The third via 230 extends through the right side of the first device (laterally spaced from the first via 210 ). The third via 230 connects to the fourth via 240, which extends through the right side of the second device.

Although the stack configuration of Figure 20 has only two devices, many more devices can be stacked on top of it. Additionally, although both devices shown in FIG. 20 have the vias that characterize the embodiment of FIG. 3, this is not required. The vias may have features of other embodiments or combinations thereof. Also, although it is preferred that both devices have one or more vias of the present invention, it is possible for one of the devices to have vias of the prior art type, or no vias at all, but only for electrical surface features. for connecting to the vias of the first device.

The drawings and the methods and devices described above are only preferred embodiments and should not be construed as limiting the invention. Modifications and equivalents to the specific structures, materials and methods described will be apparent to those skilled in the art and are intended to be within the scope of the invention as defined by the appended claims.

Claims (20)

1. electronics or micro mechanical device; First and second surface and through holes are arranged; This through hole extends through this device to second surface from first surface; This through hole comprises first, second and third part, and first extends to second surface from first surface, and second portion extends a part of first surface that covers this device; Third part extend to cover a part of second surface of this device, said first, second be electrodeposited coating with third part through electroplating technology integrally formed through hole together.

2. device according to claim 1, wherein another electrodeposited coating is formed on the first surface top of this device.

3. device according to claim 2 wherein provides a barrier layer between said first electrodeposited coating and said another electrodeposited coating.

4. device according to claim 1, wherein the first of through hole comprises first parts and second parts, the cross-sectional area of first parts is bigger than the cross-sectional area of second parts.

5. device according to claim 4, wherein first parts are tapers.

6. device according to claim 4, wherein second parts are tapers.

7. device according to claim 1, wherein through hole comprises the polymer filler that is centered on by electroplated metal layer.

8. device according to claim 1, wherein this device is layered on the top or the below of second device or substrate, and is electrically connected to second device through through hole.

9. method that forms through hole, this through hole extends through an electronics or micro mechanical device, and this device has first surface and second surface, and this method comprises: form a through hole, this through hole extends through this device to second surface from first surface; Electroplate to add an integrally formed together metal level, it extends through said through hole to said second surface from said first surface; Said integrally formed together metal level comprises a part of extending the said first surface of this device portions of covering and a part of extending the said second surface of this device portions of covering.

10. method according to claim 9 comprises and adds a polymeric layer in metal level, is centered on by metal level.

11. method according to claim 9, wherein electroplate be through one the end of from and on technology carry out, wherein sealed sooner than part by plated metal near first surface near the part of second surface.

12. method according to claim 9, wherein this method also comprise the said device of lamination second top device or below step, make that said device and said second device are electrically connected through through hole.

13. electronics or micro mechanical device; First and second surface and through holes are arranged, and this through hole extends through this device to second surface from first surface, and this through hole comprises first, second and third part; First extends to second surface from first surface; Wherein this device has a non-active layer and an active layer, and wherein first parts of first extend through non-active layer, and second parts of first extend through active layer; The width of first parts is wideer than the width of second parts; Second portion extend to cover a part of first surface of this device, and third part is extended a part of second surface that covers this device, said first, second be electrodeposition of metals with third part through electroplating technology integrally formed through hole together.

14. device according to claim 13, wherein through hole comprises a polymeric layer that is centered on by electrodeposition of metals, and said polymer and electrodeposited coating all extend through the activity and the non-active layer of this device.

15. a method that forms through hole, this through hole extend through an electronics or micro mechanical device, this device has first surface and second surface, and this method comprises: through the first of etching formation through hole, form the second portion of through hole through laser drill; This through hole extends through this device to second surface from first surface; Electroplate to add an integrally formed together metal level, it extends through said through hole to said second surface from said first surface; Said integrally formed together metal level comprises a part of extending the said first surface of this device portions of covering and a part of extending the said second surface of this device portions of covering.

16. according to the method for claim 15, wherein the second portion of through hole extends through the active region of part at least of device.

17. according to the method for claim 16, wherein the active region of this device comprises a bonding welding pad.

18. according to the method for claim 15, wherein the width of the second portion of through hole is littler than the width of the first of through hole.

19., also comprise step according to the method for claim 15: electroplate with fill or a partially filled conductive metal layer in through hole.

20. the method according to claim 19 also comprises: add a polymeric layer that is centered on by electroplated metal layer.

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