CN101916214A - Memory device and memory control method - Google Patents

Abstract

The invention provides a memory device with a shared standby decision mechanism and a memory control method. The memory device includes an address receiver, a command controller, a row address generator, a column address generator, and a shared spare determination circuit. The memory control method comprises the following steps: receiving address information and command information, and generating a latch-free address, a row latch signal or a column latch signal, and a row latch address or a column latch address; and a backup decision step; and accessing the data of the memory according to the normal circuit of the row or the column or the backup circuit of the row or the column determined by the backup. The invention adopts a shared backup decision circuit, only one backup decision circuit is needed to replace two backup decision circuits (row and column backup decision circuits) in the prior art, and the production cost can be greatly saved.

Description

Memory device and memory control method

technical field

The present invention relates to a memory device, in particular to a memory device with a shared redundancy decision mechanism.

Background technique

The redundancy determination mechanism of the existing memory device 10 , as shown in FIG. 1A , requires two sets of redundancy determination circuits. One group is the column (RoW) decision circuit Decl, and one group is the row (Column) decision circuit Dec2.

The column decision circuit Dec1 includes an address receiver 101, a column address generator 104, a column redundancy decision circuit 106, a normal word line controller 108, a normal word line NWL, a backup word line controller 109, and Redundant word line RWL. The row decision circuit Dec2 includes a command receiver 102, a command controller 103, a row address generator 105, a row backup decision circuit 107, a normal bit switch controller 110, a normal bit switch NBS, a backup bit Switch controller 111, backup bit switch RBS.

Please refer to FIG. 1A and FIG. 1B at the same time. When the existing memory device 10 is in operation, the address receiver 101 receives the external address information XADD, generates an internal address information ADD, and outputs the internal address information ADD to the column address generator 104 or row address generator 105 . The command receiver 102 receives the external command XCMD and generates the internal command CMD, and the command controller 103 determines how to generate the column latch control signal RLAT or the row latch control signal CLAT according to the internal command CMD to control the column address generator 104 Or the row address generator 105 to generate a latched column address ADD_ROW or a row latched address ADD_COL. As shown in FIG. 1B , from the time t1 when the external address information XADD is processed to the time t2 when the latch address ADD_ROW or ADD_COL is determined, the existing memory device 10 takes a total time T1 .

According to the design of the prior art, the column or row backup decision circuit 106 or 107 must receive the column or row latch address ADD_ROW or ADD_COL output by the column address generator 104 or the row address generator 105 at time t2 before it can At the time t3, according to the column or row latch address ADD_ROW or ADD_COL, it is decided to enable (Enable) (set to logic 1) or disable (Disable) the column backup enable signal RHIT or the row backup enable signal CHIT generated by it at time t3. ) (set to logic 0) to start the normal circuit (Normal circuit) part or start the backup circuit (Redundancy circuit) part. Therefore, as shown in FIG. 1B , the column or row redundancy decision circuit 106 or 107 of the conventional memory device 10 needs to spend a length of time T2 when making a redundancy decision.

It should be noted that even if the latched column or row address ADD_ROW or ADD_COL is transmitted to the word line controller 108, 109 or transmitted to the bit switch before the column redundancy enable signal RHIT or the row redundancy enable signal CHIT is generated The controllers 110 and 111, but the data of the existing memory device 10 still need to wait for the column or row redundancy decision circuit 106 or 107 to complete the determination of the normal circuit and the backup circuit before starting to access. In this way, time will be wasted and the processing speed will be greatly reduced.

Contents of the invention

In view of the above problems, one of the objectives of the present invention is to provide a memory device with a mechanism for fast shared redundancy decision.

One of the objectives of the present invention is to provide a memory device, which only uses one spare decision circuit to replace the existing two column and row spare decision circuits, and achieves the effect of saving production cost.

An embodiment of the present invention provides a memory device, including an address receiver, a command receiver, a command controller, a column address generator, a row address generator and a shared spare decision circuit. The address receiver receives and converts an external address information to generate an internal address information; the command receiver receives and converts an external command to generate an internal command; the command controller generates a column latch control signal or generates an internal command according to the internal command The row latch control signal; the column address generator receives internal address information, and determines how to convert the internal address according to the column latch signal to generate a latch column (Row) address; the row address generator receives the internal address information, and according to the row The latch signal determines how to convert the internal address to generate a latch row (Column) address; and the shared redundancy (Redundancy) decision circuit receives the internal address information, and generates a column redundancy start signal according to the internal address information and the column latch control signal, Or generate a row backup start signal according to the internal address information and the row latch control signal.

Wherein, when the column redundancy activation signal or the row redundancy activation signal generated by the shared redundancy determination circuit is at the first voltage level, the memory device activates a normal word line circuit corresponding to the column latch address, or activates the corresponding row latch A normal bit switch circuit of the address; and when the column redundancy enabling signal or the row redundancy enabling signal generated by the shared redundancy determination circuit is at the second voltage level, the memory device activates a redundancy word of the corresponding column latch address element line circuit, or a backup bit switch circuit that activates the corresponding row latch address.

Another embodiment of the present invention provides a memory device including a memory circuit and a shared redundancy determination circuit. The memory circuit receives an address information and a command information, generates a non-latched (non-latched) address, a row of latch signals or a row of latch signals, and a row of latch addresses or a row of latch addresses; and shared redundancy decision The circuit, according to the non-latch address and the column latch signal or the row latch signal, outputs to the normal circuit of the column or row of the storage unit of the memory device at the column latch address or the row latch address, or the backup circuit of the column or row Beforehand, it is decided in advance to activate the normal circuit of the column or row, or the backup circuit of the column or row.

Another embodiment of the present invention provides a memory control method, which includes the following steps: first, the information generation step receives an address information and a command information, and generates a non-latched address and a row of latches signal or a row latch signal, and a column latch address or a row latch address; then, for the backup decision step, according to the non-latch address and the column latch signal or the row latch signal, at the column latch address or the row latch Before the lock address is output to the normal circuit of the column or row of the storage unit of the memory device, or the backup circuit of the column or row, it is determined in advance to start the normal circuit of the column or row, or the backup circuit of the column or row; The fetching step is to access the data of the memory according to the normal circuit of the column or row or the backup circuit of the column or row according to the redundancy decision.

The memory device and the control method of the embodiment of the present invention are carried out by using the non-latched internal address converted from the external address information and the internal command including the fuse information converted from the external command before the column or row latch address. Compare and judge. In this way, the decision of the redundancy mechanism of the memory device of the embodiment of the present invention can be quickly prepared before the row or column latch address information is transferred to the word line controller or the bit switch controller of the subsequent circuit. The memory device can immediately start data access after the latched column or row address information is ready, without spending extra time waiting for the row or row backup start signal to be generated. Furthermore, since the memory device of the embodiment of the present invention adopts a shared spare decision circuit, only one spare decision circuit can be used to replace two spare decision circuits (column and row spare decision circuits) in the prior art. , which can greatly save production costs.

Description of drawings

FIG. 1A shows a schematic diagram of a conventional memory device;

FIG. 1B shows a waveform diagram of the operation of the memory device of FIG. 1A;

FIG. 2A shows a schematic diagram of a memory device according to an embodiment of the present invention;

FIG. 2B shows a waveform diagram of the operation of the memory device of FIG. 2A;

FIG. 3 shows a flowchart of a memory control method according to an embodiment of the invention.

Explanation of reference numerals: 10, 20 - memory device; 101, 201, 102, 202 - receiver; 103, 203, 108, 208, 109, 209, 110, 210, 111, 211 - controller; 104, 204, 105, 205-address generator; Decl, Dec2, 106, 107, Srd-reserve decision circuit; 208', 210'-normal circuit; 209', 211'-reserve circuit; 20a-memory circuit; 20b-follow-up circuit.

Detailed ways

The memory device according to the embodiment of the present invention will be described in detail below with reference to the figures.

FIG. 2A shows a memory device with a fast shared redundancy decision mechanism according to an embodiment of the present invention. The memory device 20 includes a memory circuit 20a and a subsequent circuit 20b.

The memory circuit 20a includes an address receiver (Address receiver) 201, a command receiver (Command receiver) 202, a command controller (Command controller) 203, a column address generator (RoW address generator) 204, a row address generator (Column address generator) 205, and a shared redundancy decision circuit (Shared redundancy decision circuit) Srd.

The address receiver 201 receives and converts an external address information XADD to generate an internal address information ADD.

The command receiver 201 receives and converts an external command XCMD to generate an internal command CMD.

The command controller 203 generates a column latch control signal RLAT or generates a row latch control signal CLAT according to an internal command CMD.

The row address generator 204 receives the internal address information ADD, and determines how to convert the internal address according to the row latch signal RLAT to generate a latched row address ADD_ROW.

The row address generator 205 receives the internal address information ADD, and determines how to convert the internal address to generate a latched column address ADD_COL according to the row latch control signal CLAT.

The shared redundancy determination circuit Srd receives the internal address information ADD, and generates a row redundancy activation signal RHIT according to the state of the internal address information ADD and the row latch control signal RLAT, or generates a column redundancy activation signal RHIT according to the internal address information ADD and the row latch control signal CLAT. One line of backup start signal CHIT. It should be noted that, in an embodiment of the present invention, the shared redundancy determination circuit Srd can perform column and row redundancy determination operations in time-sharing, and generate column redundancy enabling signals and row redundancy enabling signals RHIT, CHIT in time division. In another embodiment, the shared redundancy determination circuit Srd performs column and row redundancy determination actions according to a preset order, and generates the column redundancy enable signal and the row redundancy enable signal RHIT, CHIT according to the preset sequence. Of course, in an embodiment developed in the future, the shared redundancy determination circuit can also substantially simultaneously perform column and row redundancy determination operations, and substantially simultaneously generate column redundancy activation signals and row redundancy activation signals RHIT, CHIT.

Wherein, when the column redundancy activation signal RHIT generated by the shared redundancy determination circuit Srd is at the first voltage level (such as a low voltage level or logic 0), the memory device 20 activates a normal word line corresponding to the column latch address ADD_ROW Circuit 208 ′; when the row redundancy enable signal CHIT generated by the shared redundancy determination circuit Srd is at the first voltage level, the memory device 20 activates a normal bit switch circuit 210 ′ corresponding to the row latch address ADD_COL.

And when the column redundancy activation signal RHIT generated by the shared redundancy determination circuit Srd is at the second voltage level (such as a high voltage level or logic 1), the memory device 20 activates a redundancy word line corresponding to the column latch address ADD_ROW Circuit 209 ′; when the row redundancy enable signal CHIT generated by the shared redundancy determination circuit Srd is at the second voltage level, the memory device 20 activates a redundancy bit switch circuit 211 ′ corresponding to the row latch address ADD_COL. It should be noted that after the shared redundancy determination circuit Srd performs the redundancy determination operation and activates subsequent circuits, the activated circuits can perform data access operations on the storage unit (not shown) of the memory device 20 .

The subsequent circuit 20b includes a normal word line circuit 208', a spare word line circuit 209', a normal bit switch circuit 210', and a spare bit switch circuit 211'.

The normal word line circuit 208' includes a plurality of normal word lines (Normal word line) NWL and at least one normal word line controller 208 (Normal word line controller) 208. The at least one normal word line NWL is coupled to a plurality of storage cells (not shown) of the memory device 20 . The normal word line controller 208 receives the row latch address ADD_ROW, and determines whether to activate the normal word line NWL corresponding to the row latch address ADD_ROW according to the state of the row backup enable signal RHIT for data access.

The redundant word line circuit 209' includes a plurality of redundant word lines (Redundancy word line) RWL and at least one redundant word line controller 209 (Redundancy word line controller) 209. The at least one spare word line RWL is coupled to a plurality of storage units (not shown) of the memory device 20 . The spare word line controller 209 receives the row latch address ADD_ROW, and determines whether to activate the spare word line RWL corresponding to the row latch address ADD_ROW according to the state of the row spare enable signal RHIT for data access.

The normal bit switch circuit 210' includes a plurality of normal bit switch (Normal bit switch) NBS and at least one normal bit switch controller (Normal bit switch controller) 210. The at least one normal bit switch NBS is coupled to a plurality of storage units (not shown) of the memory device 20 . The normal bit switch controller receives the row latch address ADD_COL, and determines whether to activate the normal bit switch NBS corresponding to the row latch address ADD_COL according to the state of the row backup enabling signal CHIT for data access.

The redundant bit switch circuit 211' includes a plurality of redundant bit switches (Redundancy bit switch) RBS and at least one redundant bit switch controller (Redundancy bit switch controller) 211. The plurality of spare bit switches RBS are coupled to a plurality of storage units (not shown) of the memory device 20 . The spare bit switch controller 211 receives the row latch address ADD_COL, and determines whether to activate the spare bit switch RBS corresponding to the row latch address ADD_COL according to the state of the row spare enable signal CHIT for data access.

It should be noted that the fast shared redundancy determination mechanism of the memory device 20 in the embodiment of the present invention is used to determine whether the startup is normal according to the currently received external address information XADD and the external command XCMD including fuse (Fuse) information. A word line or bit switch, or a word line or bit switch that enables redundancy. If the external address XADD currently received by the memory device 20 is judged by the backup mechanism, it corresponds to the backup circuit (the backup word line circuit 209′ or the backup bit switch circuit 211′), rather than the normal circuit (the normal word line circuit 211′). When the element line circuit 208' or the normal bit switch circuit 210'), it means that the currently received external address XADD is substantially equal to the address of the fuse. The reason is that the normal storage unit at this address has been verified as a damaged storage unit in advance, and the normal storage unit at this address must be replaced with a spare storage unit.

The principle and operation of the memory device according to the embodiment of the present invention will be described in detail below with reference to FIG. 2A and FIG. 2B .

First, when the memory device 20 of the embodiment of the present invention is in operation, the address receiver 201 receives the external address information XADD (as a synchronous address signal), and converts the external address information XADD into an internal address information ADD, and converts the internal address The information ADD is output to the shared redundancy decision circuit Srd, the column address generator 204 and the row address generator 205 . The command receiver 202 receives the external command XCMD and generates an internal command CMD, and the command controller 203 generates a column latch control signal RLAT or a row latch control signal CLAT according to the internal command CMD to control the column address generator 204, or The row address generator 105 is used to generate the column latch address ADD_ROW or the row latch address ADD_COL. As shown in FIG. 2B , from the time t1 when the external address information XADD is processed to the time t2 when the latch address ADD_ROW or ADD_COL is determined, the memory device 20 according to the embodiment of the present invention takes a predetermined length of time T1 .

It should be noted that when the column or row address generators 204, 205 receive the column latch control signal RLAT or the row latch control signal CLAT (or substantially the same time), such as time t1, the shared redundancy decision circuit Srd also receives The column latch control signal RLAT or the row latch control signal CLAT, and according to the above-mentioned internal address information ADD and the column latch control signal RLAT generates the column backup activation signal RHIT at time t1', or according to the internal address information ADD and the row latch The control signal RLAT generates a backup start signal CHIT at time t1' to determine whether the current address needs to use the normal circuit or the backup circuit. Afterwards, the memory device 20 can start to access the data of the memory. Therefore, as shown in FIG. 2B , the shared redundancy determination circuit Srd of the memory device 20 of the embodiment of the present invention only needs to spend a total of time T3 (T3 is less than the preset time length T1) from the start of the redundancy determination to the completion of the determination action. , and complete within a preset time length T1. In this way, if the length of the preset time T1 is properly designed, the shared redundancy decision circuit Srd can send the column or row redundancy start signal before the column latch address ADD_ROW or the row latch address ADD_COL is sent to the subsequent circuit 20b. RHIT or CHIT is sent to the follow-up circuit 20b, and when the column latch address ADD_ROW or row latch address ADD_COL is processed and delivered to the follow-up circuit 20b, the normal circuit part or backup determined by the backup start signal RHIT or CHIT can be started immediately circuit part. In this way, the problem in the prior art that it takes an additional time T2 to wait for the column or row redundancy decision circuits 106 and 107 to process the column or row latch addresses ADD_ROW and ADD_COL to generate the column or row redundancy activation signal RHIT or CHIT can be solved.

FIG. 3 shows a memory control method according to an embodiment of the present invention, which includes the following steps:

Step S302: start.

Step S304: an information generating step, receiving an address information and a command information, generating a non-latched (non-latched) address, a row of latch signals or a row of latch signals, and a row of latch addresses or a row of latch addresses; and

Step S306: A backup decision step, according to the non-latch address and the column latch signal or the row latch signal, at the column latch address or the row latch address, output to the normal circuit of the column or row of the storage unit of the memory device, or the column Before the backup circuit of the column or row, it is determined in advance to activate the normal circuit of the column or row, or the backup circuit of the column or row.

Step S308 : a memory access step, accessing data of the memory according to the normal circuit of the column or row or the backup circuit of the column or row determined by the redundancy.

Step S310: end.

It should be noted that in one embodiment of the above-mentioned memory control method, the redundancy determination step performs the column and row redundancy determination actions at the same time; in another embodiment, the redundancy determination step performs the column and row redundancy determination actions in time-sharing; another In one embodiment, the redundancy determination step is to perform column and row redundancy determination actions according to a preset order.

In the memory device and method of the embodiment of the present invention, before the column or row latch address, the non-latched internal address converted by the external address information is compared with the internal command including the fuse information converted by the external command. with judgment. In this way, the decision of the redundancy mechanism of the memory device of the embodiment of the present invention can be quickly prepared before the row or column latch address information is transferred to the word line controller or the bit switch controller of the subsequent circuit. The memory device can immediately start data access after the latched column or row address information is ready, without spending extra time waiting for the row or row backup activation signal RHIT or CHIT signal to be generated. Furthermore, since the memory device of the embodiment of the present invention adopts a shared spare decision circuit, only one spare decision circuit can be used to replace two spare decision circuits (column and row spare decision circuits) in the prior art, And can greatly save production costs.

Although the present invention has been described above with examples, the scope of the present invention is not limited thereto. Those in the industry can make various modifications or changes as long as they do not depart from the gist of the present invention.

Claims (22)

1. a storage arrangement is characterized in that, includes:

One address receivers receives and changes an external address information, to produce a home address information;

One command receiver receives and changes an external command, to produce a built-in command;

One instruction control unit according to this built-in command, produces row breech lock control signal or produces row breech lock control signal;

One column address generator receives this home address information, and how to change this home address to produce a breech lock column address according to this row latch-up signal decision;

Delegation's address generator receives this home address information, and how to change this home address to produce a latched row address according to this row latch-up signal decision; And

Shared back receives this home address information, produces a row redundant enabling signal or produces delegation's redundant enabling signal according to this home address information and this row breech lock control signal according to this home address information and this row breech lock control signal;

Wherein, the row redundant enabling signal that produces when this shared redundant decision-making circuit is when maybe this row redundant enabling signal is first voltage level, and this storage arrangement starts mutually a normal character line circuit that should the row latch lock address or starts phase should go a normal bit on-off circuit of latch lock address; And the row redundant enabling signal that produces when this shared redundant decision-making circuit is when maybe this row redundant enabling signal is second voltage level, and this storage arrangement starts mutually a redundant character line circuit that should the row latch lock address or starts should go a redundant bit on-off circuit of latch lock address mutually.

2. storage arrangement as claimed in claim 1 is characterized in that, the time that this shared redundant decision-making circuit produces this row redundant enabling signal early than or equal the time that this column address generator produces this row latch lock address in fact.

3. storage arrangement as claimed in claim 1 is characterized in that, the time that this shared redundant decision-making circuit produces this row redundant enabling signal early than or equal the time that this row address generator produces this row latch lock address in fact.

4. storage arrangement as claimed in claim 1, it is characterized in that, receive this external address information from this address receivers and produce this row latch lock address up to this column address generator and need expend a Preset Time, and this address receivers receives this external address information and produces the spent time of this row redundant enabling signal less than this Preset Time up to this shared redundant decision-making circuit certainly.

5. storage arrangement as claimed in claim 1, it is characterized in that, receive this external address information from this address receivers and produce this row latch lock address up to this row address generator and need expend a Preset Time, and this address receivers receives this external address information and produces the spent time of this row redundant enabling signal less than this Preset Time up to this shared redundant decision-making circuit certainly.

6. storage arrangement as claimed in claim 1 is characterized in that, this first voltage level is low-voltage position standard or logical zero.

7. storage arrangement as claimed in claim 1 is characterized in that, this second voltage level is high voltage level or logical one.

8. storage arrangement as claimed in claim 1 is characterized in that, this shared redundant decision-making circuit is listed as the redundant decision action with row in fact simultaneously, produces this row redundant enabling signal and this row redundant enabling signal in fact simultaneously.

9. storage arrangement as claimed in claim 1 is characterized in that, this shared redundant decision-making circuit timesharing is listed as the redundant decision action with row, and timesharing produces this row redundant enabling signal and this row redundant enabling signal.

10. storage arrangement as claimed in claim 1 is characterized in that, this shared redundant decision-making circuit is listed as with the redundant decision of row according to a preset order and moves, and produces this row redundant enabling signal and this row redundant enabling signal according to this preset order.

11. storage arrangement as claimed in claim 1 is characterized in that, this normal character line circuit includes:

Many normal character lines couple a plurality of storage elements of this storage arrangement; And

At least one normal character lane controller receives this row latch lock address, and whether decision starts to this normal character line that should the row latch lock address, to carry out data access according to the state of this row redundant enabling signal.

12. storage arrangement as claimed in claim 1 is characterized in that, this redundant character line circuit includes:

Many redundant character lines couple a plurality of storage elements of this storage arrangement; And

At least one redundant character lane controller receives this row latch lock address, and whether decision starts to this redundant character line that should the row latch lock address, to carry out data access according to the state of this row redundant enabling signal.

13. storage arrangement as claimed in claim 1 is characterized in that, this normal bit on-off circuit includes:

A plurality of normal bit switches couple a plurality of storage elements of this storage arrangement; And

At least one normal bit on-off controller receives this row latch lock address, and whether decision starts to going this normal bit switch of latch lock address, to carry out data access according to the state of this row redundant enabling signal.

14. storage arrangement as claimed in claim 1 is characterized in that, this redundant bit on-off circuit includes:

A plurality of redundant bit switches couple a plurality of storage elements of this storage arrangement; And

At least one redundant bit on-off controller receives this row latch lock address, and whether decision starts to going this redundant bit switch of latch lock address, to carry out data access according to the state of this row redundant enabling signal.

15. a storage arrangement is characterized in that, includes:

One memory circuitry receives an address information and an instruction information, produces a no latch lock address, a row latch-up signal or delegation's latch-up signal and a row latch lock address or delegation's latch lock address; And

Shared back, according to this no latch lock address and this row latch-up signal this row latch-up signal maybe, before maybe this row latch lock address exported the redundant circuit of the normal circuit of column or row of storage arrangement storage element or column or row to, decision in advance started the normal circuit of these column or row or the redundant circuit of these column or row in this row latch lock address.

16. storage arrangement as claimed in claim 15 is characterized in that, this shared redundant decision-making circuit is listed as the redundant decision action with row in fact simultaneously.

17. storage arrangement as claimed in claim 15 is characterized in that, this shared redundant decision-making circuit timesharing is listed as the redundant decision action with row.

18. storage arrangement as claimed in claim 15 is characterized in that, this shared redundant decision-making circuit is listed as with the redundant decision of row according to a preset order and moves.

19. a memory control methods is characterized in that, includes:

Receive an address information and an instruction information, produce a no latch lock address, a row latch-up signal or delegation's latch-up signal and a row latch lock address or delegation's latch lock address; And

The redundant deciding step, according to this no latch lock address and this row latch-up signal this row latch-up signal maybe, before maybe this row latch lock address exported the redundant circuit of the normal circuit of column or row of storage arrangement storage element or column or row to, decision in advance started the normal circuit of these column or row or the redundant circuit of these column or row in this row latch lock address; And

The data of coming this storer of access according to the redundant circuit of the normal circuit of this column or row of redundant decision or these column or row.

20. memory control methods as claimed in claim 19 is characterized in that, this redundant deciding step is listed as the redundant decision action with row in fact simultaneously.

21. memory control methods as claimed in claim 19 is characterized in that, this redundant deciding step timesharing is listed as the redundant decision action with row.

22. memory control methods as claimed in claim 19 is characterized in that, this redundant deciding step is listed as with the redundant decision of row according to a preset order and moves.

Images