CN101907902B - frequency tree distribution method - Google Patents
frequency tree distribution method Download PDFInfo
- Publication number
- CN101907902B CN101907902B CN2009101078106A CN200910107810A CN101907902B CN 101907902 B CN101907902 B CN 101907902B CN 2009101078106 A CN2009101078106 A CN 2009101078106A CN 200910107810 A CN200910107810 A CN 200910107810A CN 101907902 B CN101907902 B CN 101907902B
- Authority
- CN
- China
- Prior art keywords
- input
- interface
- frequency
- dimension
- frequency tree
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 238000000034 method Methods 0.000 title claims abstract description 67
- 238000006243 chemical reaction Methods 0.000 claims abstract description 54
- 239000000872 buffer Substances 0.000 claims description 30
- 238000012360 testing method Methods 0.000 claims description 21
- 230000005611 electricity Effects 0.000 claims description 4
- 238000010586 diagram Methods 0.000 description 28
- 238000012545 processing Methods 0.000 description 17
- 230000001360 synchronised effect Effects 0.000 description 15
- 238000013461 design Methods 0.000 description 5
- 230000000694 effects Effects 0.000 description 4
- 239000002184 metal Substances 0.000 description 4
- 230000005540 biological transmission Effects 0.000 description 3
- 239000003990 capacitor Substances 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- 238000004891 communication Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 230000007613 environmental effect Effects 0.000 description 2
- 101100113692 Caenorhabditis elegans clk-2 gene Proteins 0.000 description 1
- 101150085102 Clk3 gene Proteins 0.000 description 1
- 230000000712 assembly Effects 0.000 description 1
- 238000000429 assembly Methods 0.000 description 1
- 238000004364 calculation method Methods 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 238000012546 transfer Methods 0.000 description 1
- 230000001960 triggered effect Effects 0.000 description 1
Images
Landscapes
- Design And Manufacture Of Integrated Circuits (AREA)
Abstract
The invention relates to a frequency tree distribution method. The frequency tree distribution method is applicable to an input/output interface of an integrated circuit and used for producing a frequency tree for the input/output interface. The frequency tree distribution method includes the following steps of: deciding conversion ratio; converting two-dimensional interface arrangement of the input/output interface into equivalent one-dimensional interface arrangement according to the conversion ratio; generating one-dimensional frequency tree distribution according to the equivalent one-dimensional interface arrangement; reversely converting the one-dimensional frequency tree distribution corresponding to the equivalent one-dimensional interface arrangement into two-dimensional frequency tree distribution corresponding to the two-dimensional interface arrangement according to the conversion ratio; and generating the frequency tree according to the two-dimensional frequency tree distribution.
Description
Technical field
The present invention relates to a kind of frequency tree distribution method, be specifically related to a kind of corresponding integrated circuit (integratedcircuit, frequency tree (clock tree) location mode that IO interface IC) (I/O interface) produces.
Background technology
Along with the development of semiconductor and electronics and information industry, various integrated circuit packages are widely used in various application scenarios such as communication, signal Processing, computing judgement.In deep-sub-micrometer processing procedure now, dynamical integrated circuit carries out calculation process at a terrific speed, and carries out signal exchange and communication through IO interface and other assembly.
See also Fig. 1, Fig. 1 is the synoptic diagram of the IO interface 10 of integrated circuit in the prior art.As shown in Figure 1, IO interface 10 comprises a plurality of input and output pins 100.Wherein, each input and output pin 100 has a frequency triggering input 1000 respectively.Input and output pin 100 triggers (clock trigger) according to the frequency that receives and carries out the reception or the transmission of data-signal.
In practical application; The input and output pin 100 of IO interface 10 is according to the difference of its signal properties and signal connection object; Possibly need to adopt different frequencies, in Fig. 1, frequency signal Clk corresponds to the input and output pin 100 that indicates Data; Frequency signal Clk2 corresponds to the input and output pin 100 that indicates Data2, and frequency signal Clk3 corresponds to the input and output pin 100 that indicates Data3.That is to say that the frequency that frequency signal Clk need be electrically connected to the input and output pin 100 that indicates Data triggers input, to drive and to control the signal transmitting and receiving of these input and output pins 100.
Please consult Fig. 2 in the lump, Fig. 2 is the frequency signal Clk of integrated circuit in the prior art and the synoptic diagram of IO interface 10 annexations.As shown in Figure 2, among Fig. 2 be with frequency signal Clk respectively through many independently circuit be connected to each the input and output pin 100 that need use frequency signal Clk (indicate Data) respectively.Though such frequency distribution mode is design easily; But it is in fact as shown in Figure 2; Its length of each section circuit between the input of input and output pin and frequency is different; To cause the input and output pin will have a frequency departure to each other, so can't reach the effect of (synchronized) receiving and transmitting data signals synchronously.On the other hand, a large amount of separate lines is set will produces unnecessary manufacturing cost, and on the actual track layout because of insufficient space, also infeasible.
The more common practice is at present, cooperates IO interface that one frequency tree is set, and utilizes frequency tree frequency to be triggered each input and output pin that is sent to IO interface respectively.The design of frequency tree need be considered balance, time deviation, the coiling rule of chip itself, the line characteristic various factorss such as (line length, driving force, revolution rates) of load value.In addition, IO interface is generally two-dimensional arrangements (like the U font among Fig. 1), but not more simple line spread, it is more difficult to make in the design that frequency tree distributes.
On the other hand; At a high speed IO interface now; For example: SSTL2 interface (DDR2), SSTL3 interface (DDR3), SATA (Serial Advanced Technology Attachment) interface, PCIe interface etc., its transmission speed constantly promotes, and the requirement of frequency signal is also improved constantly.In order to ensure the quality of transmission, each input and output pin of IO interface needs frequency triggering accurately, can receive and dispatch synchronously with the data-signal of guaranteeing IO interface.
In order to address the above problem, the present invention proposes a kind of frequency tree distribution method, is used for the frequency tree of IO interface with generation, and it can reach the frequency equilibrium of high speed IO interface, to address the above problem.
Summary of the invention
The object of the present invention is to provide a kind of frequency tree distribution method, be applicable to the IO interface of integrated circuit, be used for the frequency tree of IO interface in order to generation, IO interface has two-dimentional interface arrangement (for example U font or L font etc.).
According to a specific embodiment, frequency tree distribution method comprises the following step:
The decision conversion ratio; Convert the two-dimentional interface arrangement of IO interface into equivalent one-dimensional interface arrangement (a for example straight line) according to conversion ratio; Producing the one dimension frequency tree according to equivalent one-dimensional interface arrangement distributes; According to conversion ratio, the one dimension frequency tree distribution reversal of corresponding equivalent one-dimensional interface arrangement is converted into the two-dimentional frequency tree distribution of corresponding two-dimentional interface arrangement; And according to two-dimentional frequency tree distribution generation frequency tree.
Wherein, conversion ratio can decide according to line electricity resistance, line capacitance value and the coiling rule of integrated circuit.In this embodiment, IO interface has a plurality of input and output pins, and frequency tree is in order to provide synchronous frequency signal to input and output pin.Utilize the frequency tree of balance to distribute, reduce the frequency departure of IO interface.
According to another specific embodiment of the present invention, frequency tree distribution method comprises the following step:
The decision conversion ratio; Convert the two-dimentional interface arrangement of IO interface into equivalent one-dimensional interface arrangement according to conversion ratio; Producing the one dimension frequency tree according to equivalent one-dimensional interface arrangement distributes; According to conversion ratio, the one dimension frequency tree distribution reversal of corresponding equivalent one-dimensional interface arrangement is converted into the two-dimentional frequency tree distribution of corresponding two-dimentional interface arrangement; Produce frequency tree according to two-dimentional frequency tree distribution; And be connected in series delay-level in being provided with between frequency tree and the IO interface.
In this embodiment, IO interface has a plurality of input and output pins, and the serial connection delay-level cooperates frequency tree in order to controllable asynchronous frequencies signal to these a plurality of input and output pins to be provided.Utilize the frequency tree of balance to distribute and add controllable serial connection delay-level, under the situation of the frequency departure of may command IO interface, and the power supply spring noise when reducing IO interface and switching simultaneously.That is to say that the IO interface that frequency tree distribution method of the present invention can corresponding two-dimensional arrangements produces frequency tree, and utilize frequency tree to produce the required frequency signal of IO interface.
Another object of the present invention is to provide a kind of frequency tree to produce system, frequency tree produces system and is used for the frequency tree of IO interface in order to generation, and IO interface is arranged on the integrated circuit and has two-dimentional interface and arranges.
According to a specific embodiment, frequency tree generation system comprises processing module.Processing module decision conversion ratio also converts the two-dimentional interface arrangement of IO interface into equivalent one-dimensional interface arrangement according to conversion ratio; Producing the one dimension frequency tree according to equivalent one-dimensional interface arrangement distributes; According to conversion ratio the two-dimentional frequency tree that the one dimension frequency tree distribution reversal of corresponding equivalent one-dimensional interface arrangement converts corresponding two-dimentional interface arrangement into is distributed, and distribute according to two-dimentional frequency tree and to produce frequency tree.
Another object of the present invention is to provide a kind of frenquency signal circuit, the frenquency signal circuit is in order to the IO interface of corresponding integrated circuit, and IO interface has a plurality of input and output pins.
According to a specific embodiment, the frenquency signal circuit comprises frequency tree and serial connection delay-level.Frequency tree is in order to provide synchronous frequency signal.The serial connection delay-level is coupled between frequency tree and a plurality of input and output pin, and the serial connection delay-level is in order to convert synchronous frequency signal into controllable asynchronous frequencies signal and to be sent to a plurality of input and output pins.
That is to say that the IO interface that frequency tree distribution method of the present invention can corresponding two-dimensional arrangements produces frequency tree, and utilize frequency tree to produce the required frequency signal of IO interface.Can further be understood by following detailed Description Of The Invention and accompanying drawing about advantage of the present invention and spirit.
Description of drawings
To combine accompanying drawing and embodiment that the present invention is described further below, in the accompanying drawing:
Fig. 1 is the synoptic diagram of the IO interface of integrated circuit in the prior art;
Fig. 2 is the frequency signal of integrated circuit in the prior art and the synoptic diagram of IO interface annexation;
Fig. 3 is the process flow diagram according to the first specific embodiment medium frequency tree distribution method of the present invention;
Fig. 4 is the synoptic diagram of the two-dimentional interface arrangement of IO interface in first specific embodiment;
Fig. 5 A is the synoptic diagram of conversion ratio equivalent one-dimensional interface arrangement when being 2 times;
Fig. 5 B is the synoptic diagram of conversion ratio equivalent one-dimensional interface arrangement when being 0.5 times;
Fig. 5 C is the synoptic diagram of conversion ratio equivalent one-dimensional interface arrangement when being 1 times;
Fig. 6 is the synoptic diagram that the one dimension frequency tree of corresponding equivalent one-dimensional interface arrangement distributes;
Fig. 7 is that the one dimension frequency tree distributes and the synoptic diagram of the relay buffer device of further inserting among Fig. 6;
Fig. 8 is that the one dimension frequency tree distributes and the synoptic diagram of the terminator further inserted among Fig. 7;
Fig. 9 is that one dimension frequency tree distribution reversal converts the synoptic diagram that two-dimentional frequency tree distributes among Fig. 8;
Figure 10 is the synoptic diagram that two-dimentional frequency tree distributes among Fig. 9;
Figure 11 is the process flow diagram according to the second specific embodiment medium frequency tree distribution method of the present invention;
Figure 12 is the synoptic diagram of the delay-level in second specific embodiment;
Figure 13 is a synoptic diagram of setting the generation system according to the 3rd specific embodiment medium frequency of the present invention.
[primary clustering symbol description]
10,30,30 ', 30 ", 50: IO interface
100: input and output pin 1000: frequency triggers input
3: integrated circuit
301: the first input and output pin groups
302: the second input and output pin groups
302e: the equivalent second input and output pin group
303: the three input and output pin groups
303e: equivalence the 3rd input and output pin group
32: the one dimension frequency tree distributes 3 20: the relay buffer device
322a: the first relay buffer device 322b: the second relay buffer device
324: terminator 34: two-dimentional frequency tree distributes
56: the serial connection delay-level
7: frequency tree produces system 70: processing module
72: test module
S100～S120, S200～S222: step
Embodiment
In general, the integrated circuit of present stage, in order to transmit maximum data simultaneously and to avoid signal interference problem to each other, its IO interface is mostly around being arranged at the integrated circuit edge, and the IO interface that forms two dimension distributes.Yet when considering the stationary problem of high-frequency signal, IO interface needs a desirable frequency tree so that frequency signal accurately to be provided.In fact, corresponding two-dimensional arrangements, the frequency tree of the balance of input and output pin design that differs of distance has certain degree of difficulty separately.
See also Fig. 3 and Fig. 4, Fig. 3 is the process flow diagram according to the first specific embodiment medium frequency tree distribution method of the present invention.Fig. 4 is the synoptic diagram of the two-dimentional interface arrangement (two-dimensional arrangement) of IO interface 30 in first specific embodiment.
As shown in Figure 4, in this embodiment, comprise the first input and output pin group 301, the second input and output pin group 302 and the 3rd input and output pin group 303 with the IO interface 30 of this two dimension interface arrangement.Each self-contained a plurality of input and output pin of each input and output pin group.
Wherein, the first input and output pin group 301 is that horizontally the second input and output pin group 302 and the 3rd input and output pin group 303 are homeotropic alignment.And the second input and output pin group 302 and the 3rd input and output pin group 303 lay respectively at the both sides of the first input and output pin group 301.Therefore, the second input and output pin group 302, the first input and output pin group 301 and the 3rd input and output pin group 303 are arranged in regular turn, form the two-dimentional interface arrangement of U font.
In another specific embodiment, IO interface of the present invention also can be the second input and output pin group that comprises first horizontal input and output pin group and homeotropic alignment.The second input and output pin group and the first input and output pin group form the two-dimentional interface arrangement of L font.In first specific embodiment, be to arrange with U font among Fig. 4 to illustrate, but the present invention is not as limit.
As shown in Figure 3, frequency tree distribution method of the present invention is execution in step S100 at first, decision conversion ratio (conversionrate).Then, execution in step S102 according to the conversion ratio among the step S100, converts the two-dimentional interface arrangement of IO interface 30 into equivalent one-dimensional interface arrangement (equivalentone-dimensional arrangement).
Wherein, the two-dimentional interface arrangement among the above-mentioned steps S102 is please consulted Fig. 5 A to Fig. 5 C in the lump to the one-dimensional interface arrangement conversion, and Fig. 5 A to Fig. 5 C is respectively the synoptic diagram of equivalent one-dimensional interface arrangement under the different switching ratio.
With Fig. 5 A is example, and it shows the equivalent one-dimensional interface arrangement that conversion ratio is a twice.In this embodiment; Step S102 is according to conversion ratio; The second input and output pin group 302 and the 3rd input and output pin group 303 with homeotropic alignment; Its width is multiplied by conversion ratio (2 times) respectively, with form the equivalent second input and output pin group 302e and the equivalence the 3rd input and output pin group 303e, and with the equivalent second input and output pin group 302e and the equivalence the 3rd input and output pin group 303e with horizontal mode; Arrange to form the equivalent one-dimensional interface both sides that are arranged in the first input and output pin group 301 respectively, shown in Fig. 5 A.
On the other hand, Fig. 5 B be conversion ratio be 0.5 times equivalent one-dimensional interface arrangement IO interface 30 ', be the IO interface 30 of 1 times equivalent one-dimensional interface arrangement and Fig. 5 C is a conversion ratio ".
Set but the line electricity resistance of wherein above-mentioned conversion ratio reference integrated circuit 3, line capacitance value and coiling are regular.Wherein, the thickness of line wire layer is different on the line electricity resistance reaction procedure, and the spacing between two adjacent lines is different on the line capacitance value reaction procedure, and the coiling rule is the share standard of minimum widith and minimum spacing in the circuit processing procedure.The example of below takeing on the processing procedure describes the present invention, but not as limit.If adopt in the metallic circuit processing procedure the 5th metal level (M5) as the horizontal alignment layer and adopt that top metal level (MT) is as the horizontal path layer in the metallic circuit processing procedure, then the numerical value of conversion ratio is about 0.95 times.If adopt in the metallic circuit processing procedure the 3rd metal level (M3) as the horizontal alignment layer and adopt that the 4th metal level (MT) layer is as the horizontal path layer in the metallic circuit processing procedure, then the numerical value of conversion ratio is about 1 times.
Then, execution in step S104 produces the one dimension frequency tree according to equivalent one-dimensional interface arrangement and distributes.Please consult Fig. 6 in the lump, Fig. 6 is the synoptic diagram of the one dimension frequency tree distribution 32 of corresponding equivalent one-dimensional interface arrangement.In this embodiment, one dimension frequency tree distribution 32 can adopt binary tree (binary tree) mode of balance to arrange like the equivalent one-dimensional interface among Fig. 5 A with corresponding.As shown in Figure 6, arrange at the equivalent one-dimensional interface can be divided into eight unit intervals, and one dimension frequency tree distribution 32 comprises a plurality of nodes of arranging with the binary tree mode.As shown in Figure 6, it is four layers (every layers 1,2,4,8 nodes) that these nodes are divided into balance binary tree mode, and the node of the bottom corresponds to eight unit intervals respectively.In this embodiment, each node place can be respectively arranged with relay buffer device (repeater buffer) 320.Relay buffer device 320 can be in order to the frequency signal of enhanced flow warp, and then avoids frequency signal in the process of transmitting, and is not enough or receive capacity effect to influence distortion because of revolution rate (slew rate).
What need explanation is; One dimension frequency tree produced according to the present invention distributes 32; Mode produces because it utilizes balanced tree (balance tree), that is to say Zi input place of the node of top layer line length to output place of the node of the bottom with and relay buffer device 320 numbers of process all identical.The line length of unique different portions in the frequency signal bang path, the node that the bottom only the arranged input and output pin in its corresponding unit interval, however line length of this part is less than the size of unit interval.Distribute like one dimension frequency tree among Fig. 6, being divided into is four layers, and the bottom is eight nodes, but the present invention is not as limit.In another embodiment, the bottom can be 16 nodes with corresponding 16 littler unit intervals.That is to say,, can make this a part of line length gap little to the synchronism that does not influence frequency signal through the design of unit interval.
Please consult Fig. 7 in the lump, Fig. 7 is that the one dimension frequency tree distributes 32 and the synoptic diagram of the relay buffer device of further inserting among Fig. 6.After the one dimension frequency tree distributed 32 generations, frequency tree distribution method of the present invention is execution in step S106 further, the extra first paired relay buffer device 322a and the second relay buffer device 322b (as shown in Figure 7) of inserting in the distribution 32 of one dimension frequency tree.The first relay buffer device 322a and the second relay buffer device 322b are arranged between two nodes respectively and position relatively (opposite) each other.Extra relay buffer device is set in couples can avoids the long distorted signals phenomenon of line length, and do not influence the synchronism of frequency signal.In the practical application, can be according to line length or the more how paired relay buffer device of signal demand setting, do not exceed with two among Fig. 7 in relative position in the distribution 32 of one dimension frequency tree.
On the other hand, frequency tree distribution method of the present invention is execution in step S108 further, please consults Fig. 8 in the lump, and Fig. 8 is that the one dimension frequency tree distributes 32 and the synoptic diagram of the terminator (dummyload) further inserted among Fig. 7.Step S108 is performed in this embodiment, in one dimension frequency tree distribution 32, further inserts the load value (as shown in Figure 8) of terminator 324 with the different unit intervals of balance.Wherein, terminator 324 is the input and output pin differences that promote for the different unit intervals of balance domestic demand, and the terminator 324 of corresponding different unit intervals can have different equivalent load values.
On the other hand, in another specific embodiment, if by chance there is not any input and output pin that needs promotion under any relay buffer device, then the relay buffer device can directly replace with terminator.For example, do not comprise the input and output pin that any needs promote in the unit interval fully if having, then the corresponding relay buffer device in this unit interval can be removed and with the terminator replacement of equivalent load value.
That is to say, its corresponding equivalent one-dimensional interface arrangement of one dimension frequency tree distribution that the present invention produces, and can guarantee that frequency signal is synchronous, do not receive the time delay (delay time) or the line length influence of relay buffer device.In addition, also can further strengthen the counterbalance effect of frequency tree through inserting the pairing load value of each relay buffer device of terminator balance.
Then, according to first specific embodiment of the present invention, frequency tree distribution method execution in step S110 of the present invention please consults Fig. 9 in the lump, and Fig. 9 is that one dimension frequency tree 32 reverse conversion that distribute are distribute 34 synoptic diagram of two-dimentional frequency tree among Fig. 8.According to the conversion ratio of previous setting, but frequency tree distribution method reverse conversion equivalent one-dimensional interface arrangement of the present invention is replied original two-dimentional interface arrangement (as shown in Figure 4).In this simultaneously, step S110 distributes 32 according to the one dimension frequency tree of the corresponding equivalent one-dimensional interface arrangement of conversion ratio reverse conversion, and then produces the two-dimentional frequency tree distribution 34 of corresponding two-dimentional interface arrangement.
Therefore, frequency tree distribution method of the present invention produces corresponding two-dimentional interface arrangement and can guarantee that the synchronous two-dimentional frequency tree of frequency signal distributes 34.
Please consult Figure 10 in the lump, Figure 10 is the synoptic diagram of two-dimentional frequency tree distribution 34 among Fig. 9.Then, in this embodiment, frequency tree distribution method of the present invention is execution in step S112 further, in order to cooperate the needs on the processing procedure, two-dimentional frequency tree is distributed relay buffer device and circuit in 34 near IO interface 30 (shown in figure 10).The further execution in step S114 of frequency tree distribution method of the present invention, around two-dimentional frequency tree distributes relay buffer device in 34, bury underground mute impact damper (dummy load) and decoupling capacitor (decoupling capacitor, de-cap).In practical application, the relay buffer device in the two-dimentional frequency tree distribution 34 possibly receive fabrication errors or such environmental effects, and frequency signal is caused interference.In this embodiment, mute impact damper of burying underground among the step S114 and decoupling capacitor can be in order to reduce fabrication errors or Effect of Environmental, and the frequency tree that frequency tree distribution method of the present invention is produced is more stable.
Then, execution in step S116, distributing according to two-dimentional frequency tree 34 produces frequency tree and is formed on the integrated circuit 3, with the stable synchronous frequency signal of IO interface that integrated circuit 3 is provided 30.
In this embodiment, last, the further execution in step S118 of frequency tree distribution method of the present invention, whether frequency departure (clock skew) and the retardation rate (latency) of test frequency tree meet testing standard.If the test result of the frequency tree that produces meets testing standard, then accomplish producing synchronous frequency tree distribution.On the other hand; If test result is not passed through; Further execution in step S120 then, and applies mechanically adjusted conversion ratio and carries out above-mentioned steps (step S102 is to step S116) again with the adjustment conversion ratio according to test result and circuit characteristic; To produce frequency tree again, reach the frequency requirement standard of expection up to the frequency tree that produces.
Description by above-mentioned specific embodiment can be known; Frequency tree distribution method of the present invention is compared prior art; Can produce expediently and can guarantee the frequency tree that frequency signal is synchronous, with the demand of corresponding IO interface through the conversion of the equivalence between equivalent one-dimensional interface arrangement and the two-dimentional interface arrangement.But frequency tree distribution method of the present invention also not only exceeds to produce synchronous frequency signal.
In practical application; When the input and output signal of IO interface is put switching at one time; Can produce power supply spring (power bouncing) noise, especially in the communicating circuit of high frequency now, such noise has remarkable influence to the usefulness and the stability of circuit.In second specific embodiment of the present invention; The frequency tree of the balance that frequency tree distribution method can produce based on said method; The further delay-level that can control voluntarily by the deviser of adding; To the input and output pin, and then solve power supply spring problem with asynchronous (non-synchronized) frequency signal of producing may command (controllable).
See also Figure 11 and Figure 12, Figure 11 is the process flow diagram according to the second specific embodiment medium frequency tree distribution method of the present invention.Figure 12 is the synoptic diagram of the serial connection delay-level (cascading delaystage) 56 in second specific embodiment.Be that with the maximum difference of first specific embodiment after the frequency tree completion, further execution in step S222 is provided with the controllable delay-level 56 that is connected in series between frequency tree and IO interface 50 in the present embodiment.
In this embodiment, the serial connection delay-level 56 a plurality of assemblies with certain frequency delay capable of using are connected in series and form.Shown in figure 12, serial connection delay-level 56 can comprise two impact dampers, because of the frequency of impact damper postpones for controllable, can select for use driving force low but frequency postpones little impact damper at this this two impact dampers.Therefore; Can be through serial connection delay-level 56 with the frenquency signal of frequency tree generation; Offer IO interface 50 with asynchronous mode; Therefore have a controllable small gap between the received frequency signal of each input and output pin, and then avoid the power supply spring problem of receiving and transmitting signal simultaneously.In the practical application, the number of buffers that serial connection delay-level 56 comprises receives the input and output pin of actual correspondence and decides, and does not exceed with two among Figure 12.
In sum, frequency tree distribution method of the present invention can provide synchronous frequency signal or the controllable asynchronous frequencies signal IO interface to two-dimensional arrangements.
See also Figure 13.Figure 13 is a synoptic diagram of setting generation system 7 according to the 3rd specific embodiment medium frequency of the present invention.According to the 3rd specific embodiment of the present invention, frequency tree of the present invention produces system 7 and can be used to produce the frequency tree that is used for IO interface, and in practical application, IO interface can be arranged on the integrated circuit and have two-dimentional interface and arrange.
Shown in figure 13, frequency tree produces system 7 and comprises processing module 70 and test module 72.Test module 72 electrically connects with processing module 70.Processing module 70 decision conversion ratios also convert the two-dimentional interface arrangement of IO interface into equivalent one-dimensional interface arrangement according to conversion ratio; Producing the one dimension frequency tree according to equivalent one-dimensional interface arrangement distributes; According to conversion ratio the two-dimentional frequency tree that the one dimension frequency tree distribution reversal of corresponding equivalent one-dimensional interface arrangement converts corresponding two-dimentional interface arrangement into is distributed, and distribute according to two-dimentional frequency tree and to produce frequency tree.
Subsequently, whether the frequency departure and the retardation rate of the frequency tree that test module 72 can produce in order to test processes module 70 meet testing standard, if the frequency departure and the retardation rate of frequency tree do not meet testing standard, and test module 72 repayment processing modules 70.Thus, processing module 70 can be adjusted conversion ratio according to this, and the conversion ratio of applying mechanically through adjustment produces frequency tree again.Wherein, About the transfer principle between the flow process details of above-mentioned generation frequency tree and one dimension, the two-dimentional interface arrangement; Please consult Fig. 3 to Figure 10 and aforesaid first specific embodiment in the lump, roughly the same in its principle of work and hardware construction and the previous embodiment, so do not give unnecessary details in addition at this.
In another specific embodiment of the present invention, the present invention also discloses a kind of frenquency signal circuit, and this frenquency signal circuit is in order to the IO interface of corresponding integrated circuit, and IO interface can have a plurality of input and output pins.In this embodiment, the frenquency signal circuit comprises frequency tree and serial connection delay-level.The frequency tree here can be the frequency tree based on the frequency equilibrium that frequency tree distribution method produced in the present invention's first specific embodiment.In the frenquency signal circuit of this embodiment, frequency tree is in order to provide synchronous frequency signal.The serial connection delay-level is coupled between frequency tree and a plurality of input and output pin, and the serial connection delay-level is in order to convert synchronous frequency signal into controllable asynchronous frequencies signal and to be sent to a plurality of input and output pins.Can consult aforesaid first and second specific embodiment of Fig. 3 to Figure 13 and the present invention in the lump, to understand the inside principle and the structure of frequency tree and serial connection delay-level.
Therefore, frequency tree distribution method of the present invention, frequency tree produce system and frenquency signal circuit, and synchronous frequency signal or the controllable asynchronous frequencies signal IO interface to two-dimensional arrangements can be provided.
Through the detailed description of above optimum specific embodiment, be to hope to know more to describe characteristic of the present invention and spirit, and be not to come scope of the present invention is limited with the above-mentioned optimum specific embodiment that is disclosed.On the contrary, its objective is that hope can contain in the category of claim of being arranged in of various changes and tool equality institute of the present invention desire application.
Claims (12)
1. frequency tree distribution method; Be applicable to an IO interface of an integrated circuit; A frequency tree that is used for this IO interface in order to generation; This IO interface is a two-dimentional interface arrangement, and it comprises the first dimension interface and the second dimension interface, and this frequency tree distribution method comprises the following step:
A line electricity resistance, a line capacitance value and a coiling rule decision according to this integrated circuit
One conversion ratio;
The width of the second dimension interface is multiplied by this conversion ratio, forms the equivalent second dimension interface, and the equivalent second dimension interface and the first dimension interface are arranged continuously, to form an equivalent one dimension
Interface arrangement;
Utilize the mode of balance binary tree, the one dimension frequency tree that produces this equivalence one-dimensional interface arrangement distributes;
According to this conversion ratio; The reverse conversion equivalent one-dimensional interface arrangement is recovered original two-dimentional interface arrangement; Simultaneously; The one dimension frequency tree of the corresponding equivalent one-dimensional interface arrangement of reverse conversion, and then produce the two-dimentional frequency tree of corresponding two-dimentional interface arrangement, this two dimension frequency tree is in order to provide a plurality of input and output pins of synchronizing frequency signal to this IO interface.
2. frequency tree distribution method according to claim 1; It is characterized in that; Wherein comprise one second input and output pin group of one first horizontal input and output pin group and homeotropic alignment with this IO interface of this two dimension interface arrangement of two-dimensional approach arrangement, this second input and output pin group and this first input and output pin group form a L font.
3. frequency tree distribution method according to claim 2 is characterized in that, wherein according to this conversion ratio the step that this two dimension interface arrangement of this IO interface converts this equivalence one-dimensional interface arrangement into is further comprised:
Convert this second input and output pin group of homeotropic alignment into horizontal equivalent second an input and output pin group according to this conversion ratio; And
Should the equivalence second input and output pin group and this first input and output pin group arrange continuously should the equivalence one-dimensional interface arrangement to form.
4. frequency tree distribution method according to claim 1; It is characterized in that; Wherein this IO interface with this two dimension interface arrangement comprises one first input and output pin group, one second input and output pin group and one the 3rd input and output pin group; This first input and output pin group is horizontal; This second input and output pin group and the 3rd input and output pin group are homeotropic alignment and the both sides that lay respectively at this first input and output pin group, and this second input and output pin group, this first input and output pin group and the 3rd input and output pin group form a U font in regular turn.
5. frequency tree distribution method according to claim 4 is characterized in that, wherein according to this conversion ratio the step that this two dimension interface arrangement of this IO interface converts this equivalence one-dimensional interface arrangement into is further comprised:
Convert this second input and output pin group of homeotropic alignment and the 3rd input and output pin group into horizontal equivalent second an input and output pin group and an equivalence the 3rd input and output pin group respectively according to this conversion ratio; And
This equivalence second input and output pin group and the both sides that should equivalence the 3rd input and output pin group be arranged in this first input and output pin group respectively should be arranged at equivalence one dimension interface to form.
6. frequency tree distribution method according to claim 1 is characterized in that, wherein produces in the step of this one dimension frequency tree distribution according to this equivalence one-dimensional interface arrangement, and this one dimension frequency tree of its generation distributes and comprises a plurality of nodes of arranging with the binary tree mode.
7. frequency tree distribution method according to claim 6 is characterized in that, wherein these a plurality of nodes each be respectively arranged with a relay buffer device.
8. frequency tree distribution method according to claim 7 is characterized in that, the step that wherein distributes according to this this one dimension frequency tree of equivalence one-dimensional interface arrangement generation further comprises the following step:
In this one dimension frequency tree distributes, insert one first relay buffer device, this first relay buffer device is between two that are arranged in these a plurality of nodes; And
In this one dimension frequency tree distributes, insert one second relay buffer device, this second relay buffer device be between two that are arranged in these a plurality of nodes and the position relative with this first relay buffer device.
9. frequency tree distribution method according to claim 1 is characterized in that, the step that wherein distributes according to this this one dimension frequency tree of equivalence one-dimensional interface arrangement generation further comprises the following step:
, this one dimension frequency tree inserts at least one terminator in distributing.
10. frequency tree distribution method according to claim 1 is characterized in that, the step that produces two-dimentional frequency tree further comprises the following step:
Whether a frequency departure and a retardation rate of testing this two dimension frequency tree meet a testing standard;
And
When the test result in the step of this frequency departure and this retardation rate of this two dimension frequency tree of test when not meeting this testing standard; Adjust this conversion ratio; And carry out switch process again to the step that produces this two dimension frequency tree according to this adjustment back conversion ratio; Meet this testing standard up to this test result, wherein:
Switch process: convert this two dimension interface arrangement of this IO interface into this equivalence one-dimensional interface arrangement according to this conversion ratio.
11. frequency tree distribution method according to claim 1 is characterized in that, wherein produce in the step of this two dimension frequency tree should the two dimension frequency tree completion be set after, further comprise the following step:
Between this two dimension frequency tree and this IO interface, be provided with one and be connected in series delay-level.
12. frequency tree distribution method according to claim 11; It is characterized in that; Wherein this IO interface has a plurality of input and output pins, this serial connection delay-level cooperate should the two dimension frequency tree in order to a controllable asynchronous frequencies signal to these a plurality of input and output pins to be provided.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2009101078106A CN101907902B (en) | 2009-06-02 | 2009-06-02 | frequency tree distribution method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2009101078106A CN101907902B (en) | 2009-06-02 | 2009-06-02 | frequency tree distribution method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN101907902A CN101907902A (en) | 2010-12-08 |
| CN101907902B true CN101907902B (en) | 2012-10-31 |
Family
ID=43263380
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2009101078106A Expired - Fee Related CN101907902B (en) | 2009-06-02 | 2009-06-02 | frequency tree distribution method |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN101907902B (en) |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101146109A (en) * | 2006-09-15 | 2008-03-19 | 国际商业机器公司 | Time synchronization system, time synchronization device and method for providing time synchronization device |
-
2009
- 2009-06-02 CN CN2009101078106A patent/CN101907902B/en not_active Expired - Fee Related
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101146109A (en) * | 2006-09-15 | 2008-03-19 | 国际商业机器公司 | Time synchronization system, time synchronization device and method for providing time synchronization device |
Also Published As
| Publication number | Publication date |
|---|---|
| CN101907902A (en) | 2010-12-08 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN102023942B (en) | SPI (Serial Peripheral Interface) peripheral access device and method | |
| CN101496367B (en) | Alignment and deviation correction method and transmitter for serial interconnection multiple channels | |
| CN101198942B (en) | Chip and systems with variable link widths | |
| CN113792520B (en) | Layout wiring method, device, synchronous circuit and integrated circuit chip | |
| TWI391809B (en) | Clock tree distributing method | |
| CN104424154A (en) | Universal Spi (serial Peripheral Interface) | |
| CN103500148A (en) | Device and method for enabling master control card to read type of service line card | |
| CN102981116B (en) | Dedicated integrated circuit checking device and method | |
| CN103092795A (en) | Interface circuit, signal transmission method and communication system | |
| CN101300558A (en) | Multiported memory with ports mapped to bank sets | |
| US20180275714A1 (en) | Inductive coupling for data communication in a double data rate memory system | |
| US8332680B2 (en) | Methods and systems for operating memory in two modes | |
| CN101907902B (en) | frequency tree distribution method | |
| CN103257309B (en) | Ddr series pcb plate timing compensation method, system and terminal | |
| CN105404352B (en) | It is a kind of to check clock tree synthesis result bottleneck so as to the method for improving comprehensive quality | |
| CN100461134C (en) | Controller of external storing device and address change method based on same | |
| CN105827276A (en) | Crosstalk cancellation realization method and local terminal access device | |
| CN101315547B (en) | Control system based on multiple FPGA | |
| CN211956461U (en) | Serial data communication circuit and system | |
| CN111506529B (en) | High-speed SPI instruction response circuit applied to FLASH | |
| CN1926799B (en) | Circuit comprising mutually asynchronous circuit modules | |
| CN104115086B (en) | The non-linear termination of input/output architecture on packaging part | |
| CN218850770U (en) | One-to-many UART communication device | |
| EP2040381A1 (en) | Semiconductor integrated circuit and layout technique thereof | |
| CN116522829B (en) | Clock tree structure, clock tree design method and integrated circuit |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20121031 Termination date: 20190602 |
|
| CF01 | Termination of patent right due to non-payment of annual fee |