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CN101894810A - Composite underfill, semiconductor package and method of forming the same - Google Patents

Composite underfill, semiconductor package and method of forming the same Download PDF

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Publication number
CN101894810A
CN101894810A CN2010101855051A CN201010185505A CN101894810A CN 101894810 A CN101894810 A CN 101894810A CN 2010101855051 A CN2010101855051 A CN 2010101855051A CN 201010185505 A CN201010185505 A CN 201010185505A CN 101894810 A CN101894810 A CN 101894810A
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China
Prior art keywords
primer
nanostructure
compound
semiconductor
carrier
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Pending
Application number
CN2010101855051A
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Chinese (zh)
Inventor
张惠林
林志隆
章勋明
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Taiwan Semiconductor Manufacturing Co TSMC Ltd
Original Assignee
Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Publication date
Priority claimed from US12/714,209 external-priority patent/US20100295173A1/en
Application filed by Taiwan Semiconductor Manufacturing Co TSMC Ltd filed Critical Taiwan Semiconductor Manufacturing Co TSMC Ltd
Publication of CN101894810A publication Critical patent/CN101894810A/en
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/29198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/29199—Material of the matrix
    • H01L2224/2929—Material of the matrix with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/29198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/29298—Fillers
    • H01L2224/29299—Base material
    • H01L2224/293—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/29338—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/29339—Silver [Ag] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/29198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/29298—Fillers
    • H01L2224/29299—Base material
    • H01L2224/293—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/29363—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/29384—Tungsten [W] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/29198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/29298—Fillers
    • H01L2224/29299—Base material
    • H01L2224/29393—Base material with a principal constituent of the material being a solid not provided for in groups H01L2224/293 - H01L2224/29391, e.g. allotropes of carbon, fullerene, graphite, carbon-nanotubes, diamond
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)

Abstract

The invention discloses a composite primer, a semiconductor package and a forming method thereof. Embodiments of the present invention take advantage of the physical properties of nanostructures by using them in a composite underfill. One embodiment of the composite underfill includes an epoxy substrate coated between a substrate and a semiconductor chip and a suspension of nanostructures distributed within the epoxy substrate. In another embodiment, a semiconductor package includes a semiconductor chip and a carrier, wherein the semiconductor chip is connected to the carrier, and a plurality of nanostructures disposed in an epoxy matrix are disposed between the carrier and the semiconductor chip. In other embodiments, a method of forming a semiconductor package includes forming a composite underfill. The invention has better thermal expansion coefficient matching condition, higher glass transition temperature of the primer, better heat integration, less holes and precipitation condition in the primer, higher moisture resistance, better electrostatic discharge protection condition and higher strength and elasticity.

Description

Compound primer, semiconductor packages thing and forming method thereof
Technical field
The present invention relates to the primer (underfill) in the semiconductor packages thing (semiconductor package), relate in particular to the formation method of a kind of compound primer (composite underfill), semiconductor packages thing and semiconductor packages thing.
Background technology
Generally in flip-chip (flip chip) technology, in using primer (underfill) between semiconductor chip (semiconductor chip) and the carrier (carrier) and increasing the reliability of encapsulant by reducing the stress on the solder bump (solder bump).Yet, can also improve primer to encourage the function of known primer.
Flip-chip assembly (flip chip assembly) comprises and being positioned at as directly electrically connecting situation towards one of (promptly cover) semiconductor chip (chip) or nude film (die) down on the carrier of ceramic substrate or circuit board that it has used the conductive projection weld pad on the chip (conductive bump bond pads) and has reached.Flip-chip assembly is attached on the carrier and is coated with adhesive primer between chip and carrier by the chip that on the convex pads (bump bond pad) of chip solder bump (solder bump) is set, will be formed with solder bump usually.Known primer for example is the UA28 of 3730 and the Namics of Hitachi.
The projection of flip-chip assembly has multiple function, but it still may produce fault because of stress.In above-mentioned functions, projection has formed from chip to the conductive path that is used to install chip.These projections have also constituted the machinery of the segment chip on the substrate situation have been installed.Unfortunately, projection easily breaks based on stress problem usually, and above-mentioned stress comprises the stress that does not match thermal expansion between chip and carrier substrate situation causes.When heat energy changes generation, above-mentioned remarkable thermal expansion coefficient difference will produce stress in the structure place.Figure 1A has shown in being installed on chip 2 on the carrier 4 by solder bump 8 under the thermal equilibrium state.Chip 2 ' when Figure 1B has then shown a temperature that is heated above thermal equilibrium state, carrier 4 ' and projection 8 '.This moment chip 2 ' the length Δ l that expanded FC, carrier 4 ' the length Δ l that then expanded CDifference between above-mentioned two length has produced to cause on projection 8 ' breaks or the stress of other problems.
Solution results from a scheme of problem that thermal expansion coefficient difference causes for using epoxy resin primer (epoxy underfill) to insert the gap between chip and substrate.Fig. 2 A has shown and has been incorporated between chip 2 and the carrier 4 and around the primer 6 of projection 8.Primer has helped the dispersion of stress and has protected solder bump.But sometimes primer has a high thermal expansion coefficient (coefficient of thermalexpansion, CTE), it has produced the thermal expansion situation of do not match (mismatch) between chip and primer.The situation that so do not match has produced more stress in encapsulant, and it has caused failure problems.Said circumstances is shown in Fig. 2 B, and wherein primer 6 " according to expanding than the higher ratio of other elements in the encapsulant.Primer 6 " may be in chip 2 " and carrier 4 " between produce explosion (bubble out) and caused chip 2 " break (cracking) or desorption (delamination).In addition, primer 6 " an inflatable height Δ hu and in projection 8 " locate to have produced more heavily stressed.
Along with the extensive use of low dielectric constant dielectric materials in chip, form awkward for the protection of projection and low dielectric constant dielectric materials.Protect frangible projection to need high-intensity primer.Yet dielectric layer with low dielectric constant but may be subjected to the infringement into the high strength primer, and problems such as generation desorption.In order to protect the low-k dielectric film layer, primer preferably have low glass transition temperature (glass transitiontemperature, Tg).The primer of low glass transition temperature produces softening in low relatively temperature.When the temperature of chip rose, the modulus of primer (modulus) just reduced, and made the stress that puts on low dielectric constant dielectric materials be minimized.Yet based on this low modulus, the primer of low glass transition temperature just reduces for the protection that solder bump provided, and makes solder bump face and may cause the situation of breaking of (open circuit) of opening circuit.Amplification situation 10 in Fig. 3 shown when primer 6 has a high glass transition temperature, be positioned at chip 2 dielectric layer with low dielectric constant break 12.Amplify situation 14 and then shown when primer 6 has low glass transition temperature, in a projection 8, break 16.
Low dielectric constant dielectric materials can be failed to conduct the leave caused thermal fatigue of heat energy (thermal fatique) of chip because of primer and be produced and break.In addition, low dielectric constant dielectric materials also can be broken because of foregoing the generation based on unmatched thermal coefficient of expansion.
Based on hole (void) or precipitation (settling) problem, known primer is not continuously effective in dispersive stress with protection solder bump aspect.Sometimes, owing to be positioned at spacing (pitch) problem of the solder bump on the convex pads, contiguous solder bump place can form hole in primer.When the spacing of the joint between projection and the chip was too small, the particulate (particle) in the primer may fill up this space too greatly, has therefore just produced hole.18 of amplification situations in Fig. 4 have shown the example of a hole 20 of the weld pad (not shown) that is adjacent to projection 8 and chip 2.Hole will stop primer to scatter stress and can cause the reduction of encapsulant in the hole place.In addition, in primer, sneak into particulate sometimes just like silicon dioxide.When these particulates produce precipitation or form uneven suspension situation in primer in sclerosis (curring) process, primer so will weaken.22 of amplification situations in Fig. 4 have shown the precipitation situation of the particulate 24 in the primer 6.
In addition, known primer does not have good moisture-resistant gas (moisture resistance) characteristic usually.When the penetrable primer of moisture, between solder bump, will form and electrically connect and cause short circuit (short circuit) problem.Short circuit has caused the fault of whole encapsulant.
Therefore, just need a kind of preferable primer, to overcome above-mentioned known problem.
Summary of the invention
In view of this, utilized the physical characteristic of nanostructure in the embodiments of the invention and made the primer that comprises nanostructure, to solve or to have avoided the problems referred to above or other problems and reached technological merit.
According to an embodiment, the invention provides a kind of compound primer, comprising:
One epoxy resin base material is coated between a substrate and the semiconductor chip; And a suspended matter of nanostructure, be scattered in this epoxy resin base material.
According to another embodiment, the invention provides a kind of semiconductor packages thing, comprising:
The semiconductor nude film; One substrate, wherein this semiconductor die is electrically coupled to this substrate by solder bump; And a compound primer, it comprises the nanostructure that intersperses among in the resin, wherein this compound primer is arranged between this semiconductor die and this substrate and around this solder bump.
According to another embodiment, the invention provides a kind of semiconductor packages thing, comprising:
The semiconductor nude film; One carrier, wherein this semiconductor die is connected on this carrier; And a compound primer, comprise being distributed in a plurality of nanostructures that are positioned at the epoxy resin between this carrier and this semiconductor die.
According to another embodiment, the invention provides a kind of formation method of semiconductor packages thing, comprising:
On the semiconductor chip, form a plurality of solder bumps; Connect a described a plurality of solder bump and a carrier; Coating comprises a compound primer of nanostructure; And this compound primer of sclerosis.
The advantage of embodiments of the invention is to have between semiconductor chip and the primer hole less in the high glass transition of preferable matched coefficients of thermal expansion situation, primer, preferable heat integration, primer and precipitation situation, higher moisture-resistant gas characteristic, preferable electrostatic discharge (ESD) protection situation and higher intensity and elasticity.
For above-mentioned purpose of the present invention, feature and advantage can be become apparent, a preferred embodiment cited below particularly, and cooperate appended accompanying drawing, be described in detail below:
Description of drawings
Figure 1A has shown a flip-chip assembly that does not have the primer that is in thermal equilibrium state;
Figure 1B is shown as the flip-chip assembly with the primer that is in thermal equilibrium state;
Fig. 2 A is the flip-chip assembly with the primer that is in thermal equilibrium state;
Fig. 2 B is a flip-chip assembly that has through the primer of thermal expansion;
Fig. 3 has shown in a flip-chip assembly in the situation of breaking of breaking situation and having the projection of soft primer of the chip with hard primer;
Fig. 4 has shown the hole situation of the joint of projection and chip in a flip-chip assembly and the solids precipitation situation in the primer;
Fig. 5 is a chart, has shown the glass transition temperature (Tg) of the primer of the nanostructure that is used to comprise variable concentrations;
Fig. 6 has shown the flip-chip assembly with primer that comprises nanotube; And
Fig. 7 is a form, has summed up the physical property of the primer of the nanotube that comprises variable concentrations.
Wherein, description of reference numerals is as follows:
2,2 ', 2 "～chip/flip-chip;
4,4 ', 4 "～carrier;
6,6 ', 6 "～primer;
8,8 ', 8 "～solder bump/projection;
10,14～amplification situation;
16～break;
20～hole;
18,22～amplification situation;
30～compound primer;
32～nanotube;
34～amplification situation;
Δ l FCThe expansion length of～chip;
Δ l CThe expansion length of～carrier;
Δ h uThe expansion height of～primer.
Embodiment
The present invention will by following about compound primer in the flip chip technology (fct) embodiment and be illustrated.The present invention also is applicable to the application scenarios of any primer, for example in the wafer-level package thing (chip scalepackage, CSP) or ball grid array (ball grid array BGA) waits application.
Nanotube (nanotube), nanofiber (nanofiber) or nano particle (nanoparticles) are generally the metamers, metameric colors (allotropes) of carbon, but it can comprise carbon, carbonitride, fire sand (silicon carbonnitride), tungsten or silver.Nanotube has honeycomb crystal lattice (honeycomb crystallattice) shape that is positioned at cylinder.Nanotube has an about 100nm or a diameter still less usually.Nanofiber is similar in appearance to nanotube, except it has diameter greater than 100nm.Nanoparticle is the single molecule of compound.In hereinafter only in having mentioned the nanostructure that comprises nanotube, nanofiber and/or nanoparticle.In addition, be understandable that nanotube or nanofiber comprise the nanotube or the nanofiber of various forms, comprise that armchair shape (armchair), zigzag (zig-zag) reach the nanotube of palm shape (chiral) and the nanotube and the nanofiber of nanofiber and solid wall (single-walled) or compound wall (multi-walled).
Nanostructure with specific physical has been carried out ardent and continual research in its material application facet.Nanostructure has surprising intensity and tensile properties.In addition, nanostructure has very high thermal conductivity (thermal conductivity).In addition, nanostructure has the electric characteristics similar in appearance to semi-conducting material, and it has the electric characteristics similar in appearance to metal in some situation.
Desire is utilized the characteristic of nanostructure in the embodiments of the invention, and forms the compound primer that comprises known epoxy resin base material (epoxy matrix) and nanostructure.The epoxy resin base material is generally in epoxide resin material and is coated with another material.Nanostructure in the epoxy resin base material can be a suspended matter, and can make nanostructure substantially be distributed in equably in the epoxy resin base material, though but its partly precipitated still.So compound primer can have a preferable performance compared to known primer, it is by having preferable thermal coefficient of expansion and higher glass transition temperature, preferable heat integration, hole in the primer and the minimizing of precipitation, and the preferable resistant property of environment is reached to external world.
Compound primer can comprise the nanostructure of arbitrary concentration, but more particularly, compound primer has the nanostructure of about 0.5～10 percentage by weight (concentration by weight).In other words, nanostructure and epoxy resin have 1: 199～1: 9 part by weight.Preferably, primer has the nanostructure concentration of 0.5 percentage by weight.
When using nanotube in the nanostructure, nanotube can be any known structure, but preferably uses the nanotube of compound wall rather than the nanotube of use solid wall, and this is because nanotube of compound wall has the approaching electric characteristics that is similar to semi-conducting material.The supplier of commercial nanotube for example is ShenzhenNanotech Port Company Ltd.
Mix nanotube and known primer and can form a compound primer, it has the do not match relatively low thermel expansion coefficient of situation of the thermal expansion that can reduce between primer and the chip.Along with the higher concentrations of nanotubes in the primer, nanostructure can be contributed more to form the primer of tool low thermal coefficient of expansion.Therefore, the compound primer with nanotube of high concentration has low thermal coefficient of expansion usually compared to the compound primer of the nanotube with low concentration.
In addition, nanotube has the high glass transition of the whole glass transition temperature that can increase compound primer.Fig. 5 has shown the glass transition temperature of the compound primer of the nanotube that has comprised about 0%, 0.5%, 1%, 2%, 3% nanometer concentration.The discontinuous place that adopts arrow to show in each line segment has shown glass transition temperature (Tg).When not having nanotube in primer, glass transition temperature is about 113 ℃.When compound primer had 0.5% nanostructure concentration, glass transition temperature was about 201 ℃.In nanostructure concentration is that 1% o'clock glass transition temperature is about 217 ℃, is that 2% o'clock glass transition temperature is about 248 ℃, and 3% o'clock glass transition temperature is about 233 ℃.The increase of glass transition temperature makes the intensity of primer increase to can to protect the preferable intensity of solder bump.Though the increase in glass transition temperature has still influenced low dielectric constant dielectric materials negatively, yet above-mentioned effect can be by the improvement of technology and is reduced.
The interpolation situation of nanostructure has formed whole higher heat integration in primer.Usually, nanostructure has the thermal conductivity for 3000W/mk.But above-mentioned thermal conductivity make nanostructure also dissipation come from chip heat energy and and then the thermal fatigue that helps to prevent low dielectric constant dielectric materials with break situation.
Nanostructure can fill in hole and can not form precipitation in primer usually.The diameter of nanostructure make compound primer can fill between between projection crawl space and near the chip place of bump bond.As previously mentioned, nanotube has the size that is about 100nm usually.In addition, known primer has the particulate that general diameter is about 5 microns, but nanotube has the diameter of about 100nm usually.Nanotube make nanostructure can fill up the space that general known primer can't be inserted than minor diameter.In addition, above-mentioned reduced size can make the compound primer with nanostructure be applicable to the application of the encapsulant of reduced size, and for example N22 or technology are still less used.In addition, but the physical characteristic of nanostructure makes the nanostructure covalency be engaged in epoxy resin, thereby avoids the precipitation of nanostructure.By having stoped hole and precipitation to form, encapsulant and primer can more be strengthened by more known primer.Fig. 6 has shown the prevention situation of hole and precipitation.Compound primer 30 is between flip-chip 2 and carrier 4 and around projection 8.Amplify situation 34 and shown the interior nanotube 32 of base material that is suspended in compound primer 30.
Be mixed in nanostructure in the primer and can increase the moisture barrier rate (moisture resistivity) of primer.It is hydrophobic that nanostructure is generally.So can avoid the compound primer of penetration of moisture and cause the electrical failure situations of encapsulant.
The another feature of mixing nanostructure in primer is the minimizing of static discharge failure situations (electrostaticdischarge failure), and it is because nanostructure has been improved conductance.But the preferable electrical property feature of nanostructure has made the nanostructure release electrostatic, thereby has minimized any influence for chip.
In addition, for compound primer, nanostructure provides preferable mechanical strength (mechanicalstrength) and elasticity (elasticity) usually.Summed up the part character of the primer of nanostructure concentration in Fig. 7 with the compound wall nanotube that comprises 0%, 0.5%, 1%, 2% and 3% concentration.
Primer is reached with adopting ultrasonic waves (ultrasonic force) mixing of nanotube.Above-mentioned ultrasonic waves has the performance between 100 rev/mins to 5500 rev/mins.And above-mentioned ultrasonic waves can adopt a rotary coating machine (spin coating machine) or a ultrasonic waves board (ultrasonic too1) and implement.The commercial product of rotary coating board is the Chemalux board for being produced by Chemat Science and Technology Ltd. for example, and the commercial product of supersonic speed board for example is the B2B board of Chinasource company.
After carrier substrate and flip-chip chip join, can adopt as the processes well known of capillary (capillarity) technology so that compound primer to be provided, but compound primer also can directly provide to the carrier substrate before substrate and flip-chip chip join.After being coated with compound primer, can adopt known technology sclerosis primer and it is transformed into a solid material, for example be by hot mode, particularly under 75 ℃～200 ℃ temperature.
Though the present invention discloses as above with preferred embodiment; right its is not in order to limit the present invention; any those of ordinary skills; without departing from the spirit and scope of the present invention; when can doing to change and retouching, so protection scope of the present invention is as the criterion when looking appended the scope that claim defined.

Claims (16)

1. compound primer comprises:
One epoxy resin base material is coated between a substrate and the semiconductor chip; And
One suspended matter of nanostructure is scattered in this epoxy resin base material.
2. compound primer as claimed in claim 1, wherein this nanostructure accounts for 0.5～10 percentage by weight of this compound primer.
3. compound primer as claimed in claim 1, wherein this nanostructure comprises carbon, carbonitride, fire sand, tungsten or silver.
4. compound primer as claimed in claim 1, wherein this nanostructure comprises the nanotube of compound wall.
5. semiconductor packages thing comprises:
The semiconductor nude film;
One substrate, wherein this semiconductor die is electrically coupled to this substrate by solder bump; And
One compound primer, it comprises the nanostructure that intersperses among in the resin, wherein this compound primer is arranged between this semiconductor die and this substrate and around this solder bump.
6. semiconductor packages thing as claimed in claim 5, wherein this nanostructure comprises carbon, carbonitride, fire sand, tungsten or silver.
7. semiconductor packages thing as claimed in claim 5, wherein this nanostructure comprises the nanotube of compound wall.
8. semiconductor packages thing as claimed in claim 5, wherein this nanostructure and this epoxy resin have the weight ratio between 1: 199～1: 9.
9. semiconductor packages thing comprises:
The semiconductor nude film;
One carrier, wherein this semiconductor die is connected on this carrier; And
One compound primer comprises being distributed in a plurality of nanostructures that are positioned at the epoxy resin between this carrier and this semiconductor die.
10. semiconductor packages thing as claimed in claim 9, wherein said a plurality of nanostructures account for 0.5～10% percentage by weight of this compound primer.
11. semiconductor packages thing as claimed in claim 9, wherein said a plurality of nanostructures are the nanotube of a plurality of compound walls.
12. the formation method of a semiconductor packages thing comprises:
On the semiconductor chip, form a plurality of solder bumps;
Connect a described a plurality of solder bump and a carrier;
Coating comprises a compound primer of nanostructure; And
This compound primer hardens.
13. the formation method of semiconductor packages thing as claimed in claim 12, wherein the nanostructure of this compound primer accounts for this compound primer 0.5～10% percentage by weight.
14. the formation method of semiconductor packages thing as claimed in claim 12, wherein this compound primer of coating comprises:
Before connecting described a plurality of solder bumps and this carrier, directly this compound primer of coating is on substrate.
15. the formation method of semiconductor packages thing as claimed in claim 12, wherein this compound primer of coating comprises:
After connecting described a plurality of solder bumps and this carrier, be coated with this compound primer between this semiconductor chip and this carrier and around described a plurality of solder bumps.
16. the formation method of semiconductor packages thing as claimed in claim 12, wherein this compound primer of sclerosis comprises:
Heat this compound primer to a temperature between 75～200 ℃.
CN2010101855051A 2009-05-21 2010-05-21 Composite underfill, semiconductor package and method of forming the same Pending CN101894810A (en)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US18030009P 2009-05-21 2009-05-21
US61/180,300 2009-05-21
US12/714,209 2010-02-26
US12/714,209 US20100295173A1 (en) 2009-05-21 2010-02-26 Composite Underfill and Semiconductor Package

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Citations (4)

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Publication number Priority date Publication date Assignee Title
US20050269719A1 (en) * 2004-06-04 2005-12-08 Hack Jonathan A Integrated circuit device
CN1737557A (en) * 2005-07-01 2006-02-22 中国科学院长春应用化学研究所 The method of packaging electrochemical working electrode by nano material toughened epoxy resin
US20060103029A1 (en) * 2004-11-12 2006-05-18 Delphi Technologies, Inc. Flip chip system with organic/inorganic hybrid underfill composition
US20060166003A1 (en) * 2003-06-16 2006-07-27 William Marsh Rice University Fabrication of carbon nanotube reinforced epoxy polymer composites using functionalized carbon nanotubes

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20060166003A1 (en) * 2003-06-16 2006-07-27 William Marsh Rice University Fabrication of carbon nanotube reinforced epoxy polymer composites using functionalized carbon nanotubes
US20050269719A1 (en) * 2004-06-04 2005-12-08 Hack Jonathan A Integrated circuit device
US20060103029A1 (en) * 2004-11-12 2006-05-18 Delphi Technologies, Inc. Flip chip system with organic/inorganic hybrid underfill composition
CN1737557A (en) * 2005-07-01 2006-02-22 中国科学院长春应用化学研究所 The method of packaging electrochemical working electrode by nano material toughened epoxy resin

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Application publication date: 20101124