CN101894583A - Memory unit capable of saving circuit area - Google Patents

Abstract

The invention relates to a memory unit for saving circuit area, which is formed by coupling a first transistor with a reading line and controlled by a character line, a second transistor with a third transistor controlled by a bit line, a fourth transistor with a fourth transistor controlled by a character line, wherein the second transistor is coupled between the first transistor and a power supply terminal, and the third transistor is coupled with the second transistor and controlled by a bit line. Thus, the memory cell can be formed by using four transistors, so as to achieve the purpose of saving circuit area.

Description

Memory cells that save circuit area

technical field

The invention relates to a memory unit, in particular to a memory unit which saves circuit area.

Background technique

With the development of multi-core system single chip, more and more memory will be integrated in the system chip to help the calculation of each core, so the memory will occupy most of the area on the chip in the future, and it will affect the performance of the system chip A very important factor, and will consume a lot of energy; therefore, how to effectively reduce the area of the memory and its power consumption must become a very important topic.

Please refer to FIG. 1 , which is a circuit diagram of a memory cell in the prior art. As shown in the figure, the memory unit in the prior art includes a first inverter 10', a second inverter 20' and an access port 30'. The input terminal of the first inverter 10' is coupled to the output terminal of the second inverter 20'; the output terminal of the first inverter 10' is coupled to the input terminal of the second inverter 20', and the access port 30 'Coupled to the second inverter 20' and a bit line (Bitline, BL), and coupled to a word line (Wordline, WL), this access port 30' is an N-type metal oxide half field effect Transistor (NMOS), so when the bit line is high potential, the access port 30' is opened, there will be a threshold voltage across the access port 30', so that the effective voltage of the bit line voltage to the memory cell is reduced; therefore, Please also refer to FIG. 2, which is a circuit diagram of another memory cell of the prior art. As shown in the figure, the access port 30' is replaced by a P-type metal oxide semiconductor field effect transistor (PMOS), so when the bit line is When the potential is high, after the access port 30' is opened, the voltage of the bit line will be transmitted to the storage device without loss.

Generally, when the bit line reads and writes the logic value "1" in the single-ended memory cell, the bit line will be kept at the high level (High) first, and the word line will be turned on. In this way, the single-ended memory cell cannot Know how the bitlines and wordlines behave whether you are reading or writing a logic value "1". Therefore, the memory cell is designed to write data or read data according to the bit lines of different levels. When the memory cell is read, the bit line must be changed to a voltage level slightly lower than the voltage level, so as to The data stored in the first inverter 10' and the second inverter 20' are read through the access port 30'; when the memory cell is written, the bit line must be changed to a high voltage level to pass The access port 30' writes into the memory unit formed by the first inverter 10' and the second inverter 20'.

Furthermore, please refer to FIG. 3 , which is a circuit diagram of a memory unit in the prior art. As shown in the figure, the memory unit 40' of the prior art includes a first transistor 42', a third inverter 44', a second transistor 46' and a fourth inverter 48'. One end of the first transistor 42' is coupled to a data line D and is controlled by a word line W, the input end of the third inverter 44' is coupled to the other end of the first transistor 42', and the second transistor 46' One end is coupled to the output end of the third inverter 44' and is controlled by the word line W, and the input end of the fourth inverter 48' is coupled to the other end of the second transistor 46 and the output of the third inverter 44' terminal, and the output terminal of the fourth inverter 48' is coupled to the input terminals of the first transistor 42' and the third inverter 44'. Wherein, the third inverter 44' includes a third transistor 440' and a fourth transistor 442', and the fourth inverter 48' includes a fifth transistor 480' and a sixth transistor 482'. Since the structure of the inverter is well known to those skilled in the art, it will not be further described here.

Continuing from the above, when the memory cell 40' in FIG. 3 is not writing data, the signal on the word line W is a low-level signal, so that the first transistor 42' and the second transistor 44' are turned off (cut off). When, because the third inverter 44' is connected with the input terminal of the two output terminals in the fourth inverter 48', the data of the N1 end of the third inverter 44' is connected with the data of the N2 end of the fourth inverter 48' The data are mutually inversely locked. If the memory unit 40' wants to write data, that is, when the memory unit 40' writes data "1", the signal on the word line W is a high level signal (ie "1"), so that the first transistor 42' and the second The second transistor 46' is turned on, the signal on the data line D is "1", and the signal on the bit line DB is "0". When the memory unit 40' writes data, the signal on the word line W will change to a low level signal, and the first transistor 42' and the second transistor 44' will lock the data.

However, with the generational evolution of technological products, the storage demand for memory units is getting higher and higher, and the competitive pressure on price and unit capacity is also increasing. Therefore, storage units with a smaller unit area of memory units are also It is becoming more and more important, so using fewer transistors to make memory cells is also one of the goals that the industry is aiming for.

Therefore, how to propose a novel memory unit that saves circuit area, which uses fewer transistors to form a memory unit, so as to solve the above-mentioned problems.

Contents of the invention

The object of the present invention is to provide a memory unit that saves circuit area, which uses four transistors to form a memory unit, so as to achieve the purpose of saving circuit area.

In order to achieve the above-mentioned purpose, the present invention is a memory unit that saves circuit area, and it comprises:

a first transistor coupled to a read line and controlled by a word line;

a second transistor coupled between the first transistor and a power supply terminal;

a third transistor, coupled to the second transistor and controlled by a bit line, the third transistor controls the second transistor to be turned on/off; and

A fourth transistor is coupled to the third transistor and a writing line, and is controlled by the word line.

In the present invention, further include:

A fifth transistor is coupled to the read line and a power supply terminal, and is controlled by a read signal.

In the present invention, the fifth transistor is a P-type field effect transistor.

In the present invention, further include:

A fifth transistor is coupled to the read line and a low power terminal, and is controlled by a read signal.

In the present invention, the fifth transistor is an N-type field effect transistor.

In the present invention, the word line and the bit line turn on the first transistor, the third transistor and the fourth transistor to write data between the second switch and the third switch.

In the present invention, the word line turns on the first switch to read the data stored between the second transistor and the third transistor.

In the present invention, it is coupled to a control circuit, and the control circuit is coupled to the word line, the bit line, the read line and the write line to control the memory unit to write data or read data.

In the present invention, wherein the control circuit includes:

a row of decoders, coupled to the word line, to control the memory cell on/off;

a row of decoders, coupled to the bit line, the read line and the write line; and

A control unit, coupled to the row decoder and the row decoder, and generates a control signal, and sends the control signal to the row decoder and the row decoder to control the memory unit to read or write data.

In the present invention, the first transistor, the second transistor, the third transistor and the fourth transistor are N-type field effect transistors.

In the present invention, the bases of the first transistor, the second transistor, the third transistor and the fourth transistor are coupled to the power terminal.

The invention has beneficial effects: the invention can form a memory unit by using four transistors, so as to save the circuit area.

Description of drawings

Fig. 1 is the circuit diagram of the memory cell of prior art;

FIG. 2 is a circuit diagram of another memory cell of the prior art;

Fig. 3 is a circuit diagram of another memory cell of the prior art;

Fig. 4 is the circuit diagram of the memory unit of a preferred embodiment of the present invention;

FIG. 5A is a schematic diagram of the action of writing data into a memory unit according to a preferred embodiment of the present invention;

FIG. 5B is a timing diagram of FIG. 4A in a preferred embodiment of the present invention;

FIG. 6A is a schematic diagram of the action of reading data by the memory unit in another preferred embodiment of the present invention;

FIG. 6B is a timing diagram of FIG. 5A in a preferred embodiment of the present invention;

7A is a circuit diagram of a memory unit of another preferred embodiment of the present invention;

FIG. 7B is a timing diagram of FIG. 7A in a preferred embodiment of the present invention;

8 is a circuit diagram of a chip array memory unit according to a preferred embodiment of the present invention;

FIG. 9A is a circuit diagram of a memory unit of another preferred embodiment of the present invention;

FIG. 9B is a timing diagram of FIG. 9A in a preferred embodiment of the present invention;

10A is a circuit diagram of a memory cell of another preferred embodiment of the present invention; and

FIG. 10B is a timing diagram of FIG. 9A according to a preferred embodiment of the present invention.

[Description of drawing number comparison]

current technology:

10' first inverter 20' second inverter

30' access port 40' memory unit

42' first transistor 44' third inverter

440' third transistor 442' fourth transistor

46' second transistor 48' fourth inverter

480' fifth transistor 482' sixth transistor

this invention:

1 memory unit 10 first transistor

12 second transistor 13 sixth transistor

14 third transistor 16 fourth transistor

18 fifth transistor 20 control circuit

22-column decoder 24-row decoder

26 control units 3 memory units

30 seventh transistor 32 eighth transistor

33 Twelfth Transistor 34 Ninth Transistor

36 tenth transistor 38 eleventh transistor

Detailed ways

In order to have a further understanding and understanding of the structural features of the present invention and the achieved effects, the preferred embodiments and accompanying drawings are used for a detailed description, as follows:

Please refer to FIG. 4 , which is a circuit diagram of a memory unit according to a preferred embodiment of the present invention. As shown in the figure, the memory unit 1 of the present invention which saves circuit area includes a first transistor 10 , a second transistor 12 , a third transistor 14 and a fourth transistor 16 . The first transistor 10 is coupled to a read line DR and controlled by a word line W, the second transistor 12 is coupled to the first transistor 10 and a low power supply terminal VSS, and the third transistor 14 is coupled to the second transistor 12 , and is controlled by the bit line B, the third transistor 14 controls the second transistor 12 to turn on/off, and the fourth transistor 16 is coupled to the third transistor 14 and a write line DW, and is controlled by the word line W. In this way, the present invention can form the memory unit 1 by using four transistors, so as to save the circuit area. Wherein, the first transistor 10 , the second transistor 12 , the third transistor 14 and the fourth transistor 16 are N-type field effect transistors (NMOS). How the memory unit 1 of the present invention reads or writes data will be described below, so this part will not be described here.

Moreover, the memory unit 1 which saves circuit area of the present invention further includes a control circuit 20 . The control circuit 20 is coupled to the word line W, the bit line B, the read line DR and the write line DW to control the memory unit 1 to write data or read data. The following describes how the control circuit 20 controls the memory unit 1 to write data or read data.

Please refer to FIG. 5A and FIG. 5B together, which are a schematic diagram and a timing diagram of the operation of writing data into the memory unit according to a preferred embodiment of the present invention. As shown in the figure, if the memory cell 1 is to write data, the control circuit 20 will conduct the word line W and the bit line B, even if the signals of the word line W and the bit line B are high-level signals, the first The transistor 10, the third transistor 14 and the fourth transistor 16 are turned on. At this time, the control circuit 20 will transmit a stored data on the write line DW to the storage terminal SD between the second transistor 20 and the third transistor 14, so as to Complete data storage.

Please refer to FIG. 6A and FIG. 6B together, which are a schematic diagram and a timing diagram of the memory unit 1 reading data in a preferred embodiment of the present invention. As shown in the figure, the memory unit 1 which saves circuit area of the present invention further includes a fifth transistor 18 . The fifth transistor 18 is coupled to the read line DR and a power terminal VDD, and is controlled by a read signal XPC. In this embodiment, the fifth transistor 18 is a P-type field effect transistor (PMOS). Of course, it can also be an N-type field effect transistor (NMOS), but its control method is opposite to that described in this embodiment, which is well known to those who have ordinary knowledge in this technical field, so it will not be repeated here. When the memory unit 1 is to read data, the control circuit 20 sends the read signal XPC to the fifth transistor 18, so that the fifth transistor 18 is turned on and the signal on the read line DR is a high level signal (that is, a digital signal "1"), that is, the control circuit 20 generates the reading signal XPC of the low-level signal, and transmits the reading signal XPC of the low-level signal to the fifth transistor 18, and turns on the fifth transistor 18 to make the power terminal VDD Provide a high-level signal, and send the high-level signal to the read line DR, so that the signal on the read line DR changes to a high-level signal (that is, a digital signal "1"). After that, the control circuit 20 turns on the word line W, that is, the signal on the word line W is changed to a high-level signal, but the bit line B is not turned on. At this time, the signal at the storage terminal SD (that is, the storage data stored in the memory cell) is passed through the second transistor 12 and The first transistor 10 transmits the stored data to the control circuit 20 to complete the reading of the data.

When the stored data at the storage end SD is a digital signal "1", the signal at the reading end DR will change to a low-level signal (that is, a digital signal "0"); when the stored data at the storage end SD is a digital signal When "0", the signal at the reading terminal DR will remain as a high-level signal (that is, a digital signal "1"), so that the memory unit 1 of the present invention can read the stored data at the storage terminal SD.

Please refer to FIG. 7A and FIG. 7B together, which are a circuit diagram and a timing diagram of a memory unit according to another preferred embodiment of the present invention. As shown in the figure, the difference between this embodiment and the embodiment of FIG. 4 is that the control circuit 20 of this embodiment includes a read/write terminal DR/DW, which integrates the read terminal DR and the write terminal DW, The number of pins of the control circuit 20 is reduced, thereby saving the area of the control circuit 20 and further reducing the cost. Furthermore, a sixth transistor 13 in this embodiment replaces the second transistor 12, and the sixth transistor 13 is a P-type field effect transistor (PMOS). In this embodiment, how the memory unit 1 reads and writes data, as shown in FIG. 7B , is similar to the above-mentioned data writing and reading shown in FIG. 5B and FIG. 6B , and this technical field has Generally, knowledgeable persons can easily know the timing diagram shown in FIG. 7B from the timing diagrams of FIG. 5B and FIG. 6B . Therefore, the applicant does not describe the timing diagram of FIG. 7B in detail here.

Please also refer to FIG. 8 , which is a circuit diagram of a chip array memory unit 1 according to a preferred embodiment of the present invention. As shown in the figure, the control circuit 20 in the memory unit 1 which saves circuit area of the present invention includes a column decoder 22 , a row decoder 24 and a control unit 26 . This embodiment uses a plurality of memory units. The column decoder 22 is coupled to the word line W to control the on/off of the memory cells 1, that is, the column decoder 22 is coupled to the word line W of the memory cells 1 to control the word line W to be turned on. / cut off to control the on/off of the memory unit 1. The row decoder 24 is coupled to the bit line B, the read line DR, and the write line DW, and controls the bit line B, the read line DR, and the write line DW to be turned on/off, and cooperates to control the word line W to be turned on/off. Turn off to control the memory unit 1 to write or read data. The control unit 26 is coupled to the column decoder 22 and the row decoder 24, and generates a control signal, and sends the control signal to the column decoder 22 and the row decoder 24 to control the memory unit 1 to read or write enter.

In addition, the control signals generated by the control unit 26 in this embodiment include a write signal WP, a write data XDI, a read signal XPC, a read data DRO and a bit line control signal BP. When the memory unit 1 intends to write data, the control unit 26 first generates and sends the write signal WP to the multiple row decoding unit 240 of the row decoder 24, and then decodes the write data XDI through these rows The unit 240 is transferred to the memory units 1 . When the memory unit 1 intends to read data, the control unit 26 first generates and sends the read signal XPC to the row decoding units 240 of the row decoder 24, and the row decoding units 240 follow the read signal XPC The read data DRO of the memory units 1 is read, and the read data DRO is returned to the control unit 26 . Wherein, the control unit 26 generates and transmits the bit line control signal BP to the row decoding units 240 of the row decoder 24 to control the bit line B of the memory cells 1 to be turned on/off.

Please refer to FIG. 9A and FIG. 9B together, which are a circuit diagram and a timing diagram of a memory unit according to another preferred embodiment of the present invention. As shown in the figure, the difference between this embodiment and the embodiment of FIG. 3 is that a seventh transistor 30, an eighth transistor 32, a ninth transistor 34, and a tenth transistor 36 of this embodiment are P-type transistors. field effect transistor. However, the method of controlling the seventh transistor 30, the eighth transistor 32, the ninth transistor 34 and the tenth transistor 36 for the memory unit 3 of this embodiment to read and write data is opposite to that of the fourth B diagram and FIG. 5B. The control methods are roughly the same, so no more praise here. In addition, this embodiment includes an eleventh transistor 38 for controlling the memory unit 3 to read data, which can be a P-type field effect transistor or an N-type field effect transistor.

In addition, please refer to FIG. 10A and FIG. 10B , which are a circuit diagram and a timing diagram of a memory unit according to another preferred embodiment of the present invention. As shown in the figure, the difference between this embodiment and the embodiment of FIG. 9A is that the control circuit 20 of this embodiment includes a read/write terminal DR/DW, which integrates the read terminal DR and the write terminal DW. The number of pins of the control circuit 20 is reduced, thereby saving the area of the control circuit 20 and further reducing the cost. Moreover, a twelfth transistor 33 in this embodiment replaces the eighth transistor 32, and the twelfth transistor 33 is an N-type field effect transistor (NMOS). In this embodiment, how the memory unit 3 reads and writes data, as shown in FIG. 10B , is similar to the above-mentioned data writing and reading shown in FIG. 9B , and those with ordinary knowledge in the technical field It is easy to know the timing diagram shown in FIG. 10B from the timing diagram of FIG. 9B , therefore, the applicant does not describe in detail the timing diagram of FIG. 10B here.

In summary, the memory unit of the present invention which saves circuit area has a first transistor coupled to a read line and controlled by a word line, a second transistor coupled to the connection between the first transistor and a power supply terminal. Between, a third transistor is coupled to the second transistor and is controlled by a bit line, the third transistor controls the second transistor to be turned on/off, a fourth transistor is coupled to the third transistor and a write line, and Controlled by character lines. In this way, the present invention uses four transistors to form a memory unit to achieve the purpose of saving circuit area.

In summary, it is only a preferred embodiment of the present invention, and is not intended to limit the implementation scope of the present invention. All equivalent changes and Modifications should be included within the scope of the claims of the present invention.

Claims (11)

1. A memory unit that saves circuit area, is characterized in that, it comprises: a first transistor coupled to a read line and controlled by a word line; a second transistor coupled between the first transistor and a power supply terminal; a third transistor, coupled to the second transistor and controlled by a bit line, the third transistor controls the second transistor to be turned on/off; and A fourth transistor is coupled to the third transistor and a writing line, and is controlled by the word line. 2. The memory unit according to claim 1, further comprising: A fifth transistor is coupled to the read line and a power supply terminal, and is controlled by a read signal. 3. The memory unit according to claim 2, wherein the fifth transistor is a P-type field effect transistor. 4. The memory unit according to claim 1, further comprising: A fifth transistor is coupled to the read line and a low power terminal, and is controlled by a read signal. 5. The memory unit according to claim 4, wherein the fifth transistor is an N-type field effect transistor. 6. The memory cell according to claim 1, wherein the word line and the bit line are connected to the first transistor, the third transistor and the fourth transistor to write data into the second between the switch and the third switch. 7. The memory cell according to claim 1, wherein the word line turns on the first switch to read data stored between the second transistor and the third transistor. 8. The memory unit according to claim 1, wherein it is coupled to a control circuit, the control circuit is coupled to the word line, the bit line, the read line and the write line to control the memory unit Write data or read data. 9. The memory unit according to claim 8, wherein the control circuit comprises: a row of decoders, coupled to the word line, to control the memory cell on/off; a row of decoders, coupled to the bit line, the read line and the write line; and A control unit, coupled to the row decoder and the row decoder, and generates a control signal, and sends the control signal to the row decoder and the row decoder to control the memory unit to read or write data. 10. The memory unit according to claim 1, wherein the first transistor, the second transistor, the third transistor and the fourth transistor are N-type field effect transistors. 11. The memory unit according to claim 10, wherein the bases of the first transistor, the second transistor, the third transistor and the fourth transistor are coupled to the power terminal.

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