CN101893774A - Liquid crystal display panel and method for manufacturing the same - Google Patents
Liquid crystal display panel and method for manufacturing the same Download PDFInfo
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- CN101893774A CN101893774A CN2009100573017A CN200910057301A CN101893774A CN 101893774 A CN101893774 A CN 101893774A CN 2009100573017 A CN2009100573017 A CN 2009100573017A CN 200910057301 A CN200910057301 A CN 200910057301A CN 101893774 A CN101893774 A CN 101893774A
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Abstract
The present invention relates to a liquid crystal display panel, and a method of manufacturing the liquid crystal display panel, the liquid crystal display panel including: the liquid crystal display panel comprises an upper substrate, a lower substrate opposite to the upper substrate, and a data line, a scanning line, a pixel electrode, a thin film transistor, a common electrode, a storage capacitor and a shading strip which are arranged on the lower substrate, wherein the grid electrode of the thin film transistor is connected with the scanning line, the source electrode of the thin film transistor is connected with the data line, the drain electrode of the thin film transistor is connected with the pixel electrode, and the storage capacitor is formed by the pixel electrode and the common electrode. And, the liquid crystal display panel has higher contrast and aperture ratio.
Description
Technical field
The present invention relates to a kind of display panels, and be particularly related to a kind of display panels of high-contrast.
Background technology
In recent years, along with the increase to mobile message medium demand, research can substitute the frivolous portable LCD LCD that has cathode-ray tube CRT now energetically.The most frequently used is twisted-nematic phase (TN) liquid crystal display pattern, and after its energising, liquid crystal molecule is distorted under effect of electric field, promptly controls passing through of light by the arrangement of control liquid crystal molecule.The shortcoming of this TN LCD display panel is that the visual angle is very narrow, and this is that anisotropy by liquid crystal molecule causes, though can remedy the narrow defective in visual angle by the optical compensation mode, must expend certain cost.Given this a kind of coplane conversion type display panels IPS (In plane switching) of wide viewing angle display mode has been proposed.
Please also refer to Fig. 1 and Fig. 2, Figure 1 shows that the coplane conversion type liquid crystal display panel pixel structure figure of prior art, Figure 2 shows that among Fig. 1 cross section structure figure along II-II ' direction.The coplane conversion type liquid crystal display panel pixel structure of prior art comprises: controlling grid scan line 112, the thin film transistor (TFT) (not shown), described thin film transistor (TFT) is made of the source electrode 115a of semiconductor layer 114, thin film transistor (TFT), the drain electrode 115b of thin film transistor (TFT), data line 115 is connected with the source electrode 115a of thin film transistor (TFT), described data line 115 is used for providing voltage to pixel electrode 117, and described pixel capacitors 117 is connected with the drain electrode 115b of thin film transistor (TFT).Pixel electrode 117 is transparent material ITO, can increase aperture opening ratio or aperture ratio with respect to other opaque metal electrodes.Described dot structure also comprises: public electrode wire 124,125, and public electrode wire 125 and described sweep trace 112 are commaterial, described public electrode wire 124 is a commaterial with described pixel electrode 117.Further, described dot structure also comprises contact hole (perhaps through hole) 181,182,183, and described pixel electrode 117 links to each other with drain electrode 115b by contact hole 181, and described public electrode wire 124 passes through contact hole 182 and links to each other with described public electrode wire 125.
The memory capacitance that is used for preserving electric charge in the prior art is a single layer structure, its cross section structure as shown in Figure 2, wherein the memory capacitance lower electrode of this single layer structure is 190, with data line metal 115 be with a kind of metal, it links to each other with the drain electrode 115b of thin film transistor switch (TFT), also promptly provides drain voltage.Upper electrode 191 provides common electric voltage for the transparency conducting layer ITO as public electrode.The insulating medium 116 of memory capacitance, silicon nitride for example is between upper/lower electrode.
In Fig. 1, the pixel electrode 117 of coplane conversion type display panels is transparent material ITO, though can increase aperture opening ratio or aperture ratio with respect to other opaque metal electrodes, but when display panels is operated in the black picture of normal white mode, can not show black completely, reason is when giving described pixel electrode 117 and described public electrode 124 making alives, fail to form horizontal component of electric field directly over the described pixel electrode 117, liquid crystal molecule directly over causing can not rotate and light leak, thereby the poor contrast of screen, the quality that influence shows.
This memory capacitance is designed to single layer structure, needing increases aperture opening ratio by increasing the value of memory capacitance, but the value of increase memory capacitance need increase the area of lighttight memory capacitance, the space that increases aperture opening ratio is still very little, that is to say that aperture opening ratio can not further improve.10 zones among Fig. 1, because public electrode wire 125 is with one deck metal with the sweep trace metal of a last pixel, in the time of the technology etching, consider etching deviation, prevent short circuit between the sweep trace metal of a public electrode wire 125 and a last pixel, must keep the space length of 4-6 μ m between the two, will make aperture opening ratio reduce like this, thereby the brightness that influence shows descends display quality.
Summary of the invention
In order to solve the technical matters of prior art poor contrast, the present invention proposes a kind of display panels with high-contrast.
5. display panels, described display panels comprises:
Upper substrate;
Infrabasal plate is oppositely arranged with described upper substrate;
Liquid crystal layer, between described upper substrate and described infrabasal plate, the liquid crystal molecule in the described liquid crystal layer rotates in the plane that is parallel to described upper substrate or described infrabasal plate;
Be formed with a plurality of pixels that data line and sweep trace by cross arrangement surround on the described infrabasal plate;
Each described pixel comprises: pixel electrode, public electrode, first memory capacitance and thin film transistor (TFT), wherein, the top crown of described first memory capacitance is connected with one of described pixel electrode or described public electrode, bottom crown is connected with in described pixel electrode or the described public electrode another, the grid of described thin film transistor (TFT) is connected with described sweep trace, the source electrode of described thin film transistor (TFT) is connected with described data line, and the drain electrode of described thin film transistor (TFT) is connected with described pixel electrode;
It is characterized in that each described pixel also comprises shading strip, described shading strip and described pixel electrode and/or described public electrode have overlapping.
Optionally, described shading strip is connected with described drain electrode or described shading strip is connected with described public electrode.
Optionally, described shading strip be positioned at described pixel electrode and/or described public electrode directly over or under.
Optionally, described shading strip is described pixel electrode and/or described public electrode.
Optionally, affiliated display panels also comprises second memory capacitance that is formed by described pixel electrode and described public electrode.
Optionally, described public electrode is formed by transparent conductive material.
Optionally, the material of the material of described pixel electrode and described public electrode is identical.
Optionally, described display panels also comprises shield bars, and described shield bars and the projection of described public electrode on infrabasal plate have overlapping.
Optionally, described display panels also comprises the expansion electrode, and described expansion electrode is connected with described pixel electrode.
Optionally, described expansion electrode is connected by via hole with described pixel electrode, and perhaps described expansion electrode directly is formed on the described pixel electrode.
Optionally, described shield bars is connected with described public electrode and/or described shading strip.
Optionally, described shading strip and described sweep trace are formed by same conductive layer.
Optionally, described shield bars and described shading strip are formed by same conductive layer.
Optionally, described shading strip and described data line are formed by same conductive layer.
Optionally, described shield bars and described shading strip are formed by same conductive layer.
Optionally, described display panels also comprises bus, and described bus and the projection of described pixel electrode on infrabasal plate have overlapping.
Optionally, described bus is connected with described pixel electrode.
Optionally, the display mode of described display panels is coplane conversion type or edge field pattern display mode.
Display panels of the present invention is by being provided with shading strip, blocks the light directly over described pixel electrode and/or the public electrode, and the black picture that display panels is shown is more black, thereby has increased the contrast of display panels.
31. a display panels, described display panels comprises:
Upper substrate;
Infrabasal plate is oppositely arranged with described upper substrate;
Liquid crystal layer, between described upper substrate and described infrabasal plate, the liquid crystal molecule in the described liquid crystal layer rotates in the plane that is parallel to described upper substrate or described infrabasal plate;
Be formed with a plurality of pixels that data line and sweep trace by cross arrangement surround on the described infrabasal plate;
Each described pixel comprises: pixel electrode, public electrode, first memory capacitance and thin film transistor (TFT), wherein, the top crown of described first memory capacitance is connected with one of described pixel electrode or described public electrode, bottom crown is connected with in described pixel electrode or the described public electrode another, the grid of described thin film transistor (TFT) is connected with described sweep trace, the source electrode of described thin film transistor (TFT) is connected with described data line, and the drain electrode of described thin film transistor (TFT) is connected with described pixel electrode;
It is characterized in that described pixel electrode is formed by the conductive layer of the grid that forms described thin film transistor (TFT) or source/drain electrode.
A kind of manufacture method of display panels, the manufacture method of described display panels comprises step at least:
On infrabasal plate, form grid conducting layer, and the described grid conducting layer of etching;
Form gate insulator, and semiconductor island;
Formation source/drain electrode conductive layer, and the described source of etching/drain electrode conductive layer;
Form transparency conducting layer, and the described transparency conducting layer of etching;
It is characterized in that, also comprise: form the shading strip layer, and the described shading strip layer of etching.
Optionally, described formation shading strip layer and described formation grid conducting layer are same step.
Optionally, described formation shading strip layer and described formation source/drain electrode conductive layer are same step.
Optionally, described manufacture method also comprises the formation pixel electrode layer, and described formation pixel electrode layer and described formation grid conducting layer are same step.
Optionally, described manufacture method also comprises the formation pixel electrode layer, and described formation pixel electrode layer and described formation source/drain electrode conductive layer are same step.
Optionally, described manufacture method also comprises the expansion electrode layer that forms shading strip, and the expansion electrode layer of described formation shading strip and described formation transparency conducting layer are same step.
Optionally, described manufacture method also comprises and forms the shield bars layer.
Optionally, described formation shield bars layer and described formation grid conducting layer are same step.
Optionally, described formation shield bars layer and described formation source/drain electrode conductive layer are same step.
Optionally, described manufacture method also comprises the formation common electrode layer, and described formation common electrode layer and described formation transparency conducting layer are same step.
Optionally, described manufacture method also comprises the formation pixel electrode layer, and described formation pixel electrode layer and described formation common electrode layer are same step.
The manufacture method simple possible of display panels of the present invention can be made the display panels with high-contrast.
Description of drawings
Figure 1 shows that the coplane conversion type liquid crystal display panel pixel structure figure of prior art.
Figure 2 shows that among Fig. 1 cross section structure figure along II-II ' direction.
Fig. 3 is the planar structure synoptic diagram of the single pixel of infrabasal plate of the display panels of first embodiment of the invention.
Fig. 3 A is that first memory capacitance 107 described in Fig. 3 is along the sectional view of A1-A2 direction.
Fig. 3 B is the sectional view of described second memory capacitance along the B1-B2 direction.
Fig. 3 C is described public electrode 105 and described shield bars 102 schematic cross-section along the C1-C2 direction.
Fig. 4 is the planar structure synoptic diagram of the single pixel of infrabasal plate of the display panels of second embodiment of the invention.
Fig. 4 A is the schematic cross-section of second memory capacitance along direction B1-B2.
Fig. 5 is the planar structure synoptic diagram of the single pixel of infrabasal plate of the display panels of third embodiment of the invention.
Fig. 6 is the planar structure synoptic diagram of the single pixel of infrabasal plate of the display panels of fourth embodiment of the invention.
Fig. 6 A is the schematic cross-section of described first memory capacitance 107 along the A1-A2 direction.
Fig. 7 is the planar structure synoptic diagram of the single pixel of infrabasal plate of the display panels of fifth embodiment of the invention.
Fig. 7 A be among Fig. 7 pixel electrode 104 places along a kind of schematic cross-section of A1-A2 direction.
Fig. 8 is another structural representation of planar structure of the single pixel of infrabasal plate of display panels.
Fig. 8 A is the schematic cross-sections of 104 places of pixel electrode described in Fig. 8 along the A1-A2 direction.
Fig. 9 is the planar structure synoptic diagram of the single pixel of infrabasal plate of the display panels of sixth embodiment of the invention.
Fig. 9 A is the schematic cross-section of described pixel 100 along the B1-B2 direction.
Embodiment
For solving the problem of the poor contrast of display panels in the prior art, display panels of the present invention comprises: upper substrate; Infrabasal plate is oppositely arranged with described upper substrate; Liquid crystal layer, between described upper substrate and described infrabasal plate, the liquid crystal molecule in the described liquid crystal layer rotates in the plane that is parallel to described upper substrate or described infrabasal plate; Be formed with a plurality of pixels that data line and sweep trace by cross arrangement surround on the described infrabasal plate; Each described pixel comprises: pixel electrode, public electrode, first memory capacitance and thin film transistor (TFT), wherein, the voltage of two pole plates of described first memory capacitance is respectively the voltage of pixel electrode and the voltage of public electrode, the grid of described thin film transistor (TFT) is connected with described sweep trace, the source electrode of described thin film transistor (TFT) is connected with described data line, and the drain electrode of described thin film transistor (TFT) is connected with described pixel electrode; And each described pixel also comprises shading strip, and described shading strip is in order to block the light directly over described pixel electrode and/or the described public electrode.
Form electric field between described pixel electrode of the present invention and the described public electrode, the described electric field of formation is parallel to described upper substrate or described infrabasal plate, and therefore, described liquid crystal molecule rotates in the plane that is parallel to described upper substrate or described infrabasal plate.But because described pixel electrode and/or described public electrode have certain width, directly over described pixel electrode and/or described public electrode, can not form horizontal component of electric field, so, display panels for normal black display mode, described display panels can not show black completely picture, so can influence the contrast of display panels, the present invention is by being provided with described shading strip, make display panels when picture is deceived in demonstration, cover the light directly over described pixel electrode and/or the described public electrode, thereby make black picture more black, increased the contrast of display panels.
Below be described in detail for the preferred embodiment of the present invention with reference to the accompanying drawings.
First embodiment
Fig. 3 is the planar structure synoptic diagram of the single pixel of infrabasal plate of the display panels of first embodiment of the invention.The display mode of the display panels that is formed by dot structure shown in Figure 3 is the coplane conversion type display mode.As shown in Figure 3, the data line 101a of cross arrangement and sweep trace 101b surround single pixel 100, described pixel 100 is positioned on the infrabasal plate, comprise: pixel electrode 104, public electrode 105, shading strip 103, thin film transistor (TFT) 110, first memory capacitance 107 that forms by described pixel electrode 104 and described shading strip 103, wherein, described shading strip 103 is connected with described public electrode 105, and described shading strip 103 is in order to block the light directly over the described pixel electrode 104; The grid of described thin film transistor (TFT) 110 is connected with described sweep trace 101b, and the source electrode of described thin film transistor (TFT) 110 is connected with described data line 101a, and the drain electrode of described thin film transistor (TFT) 110 and described pixel electrode 104 are connected by via hole.
Fig. 3 A is that first memory capacitance 107 described in Fig. 3 is along the sectional view of A1-A2 direction.As shown in Figure 3A, on infrabasal plate 13, described pixel electrode 104 is connected by the drain electrode 108 of via hole 1 and thin film transistor (TFT) 110, described shading strip 103 is connected with described public electrode 105 by via hole 2, has insulating medium 123 between described pixel electrode 104 and the described shading strip 103, the material of described insulating medium 123 is formed by transparent material, transparent conductive material can be a silicon nitride as described, described pixel electrode 104 and described shading strip 103 and described insulating medium 123 form first memory capacitance 107, be insulation course 121 between described infrabasal plate 13 and the described shading strip 103, described insulation course 121 is a gate insulator.
Fig. 3 B is the sectional view synoptic diagram of described second memory capacitance along the B1-B2 direction.Shown in Fig. 3 B, the width of described shading strip 103 is less than the width of described pixel electrode 104, and is positioned at following one deck of described pixel electrode 104, has insulation course 121 between described shading strip 103 and the described substrate 13.The width of described shading strip 103 can effectively be avoided the electric field effects that produces between 103 pairs of described pixel electrodes 104 of described shading strip and described common point and 105 less than the width of described pixel electrode 104.
Fig. 3 C is described public electrode 105 and described shield bars 102 schematic cross-section along the C1-C2 direction.Shown in Fig. 3 C, in the present embodiment, described public electrode 105 places also are provided with shield bars 102, described shield bars 102 and described shading strip 103 also have the effect of blocking the light directly over the described public electrode 105, avoid display panels to deceive the attitude light leak, and play the effect of distinguishing the different pixels border.In the present embodiment, described shield bars 102 is positioned under the described public electrode 105 and with described public electrode 105 and is connected, preferably, vertical and away from border, the border of the described public electrode 105 of described data line 101a direction, shown in Fig. 3 C greater than described shield bars 102.
When showing black picture, because described shading strip 103 can cover the light directly over the described pixel electrode 103, thereby make black picture more black, increased the contrast of display panels.In the present embodiment, described shading strip 103 not only can shading but also can have been formed memory capacitance with pixel electrode 104,104 that form with described shading strip 103 and described pixel electrode, be defined as first memory capacitance 107 along the electric capacity of described sweep trace 101b direction, 104 that form with described shading strip 103 and described pixel electrode, be defined as second memory capacitance along the electric capacity of described data line 101a direction, then, present embodiment is by increasing by second memory capacitance, reduce the area of first memory capacitance, thereby further increased aperture opening ratio.
Preferably, as shown in Figure 3, described public electrode 105 is formed by transparent conductive material along the part 11 of described sweep trace 101b direction, and described transparent conductive material can be tin indium oxide (ITO) or indium zinc oxide (IZO) or indium oxide gallium (IGO).Described public electrode 105 is formed by transparent conductive material along the part 11 of described sweep trace 101b direction, can increase the glazed area of described pixel 100, thereby increases the aperture opening ratio of display panels.
Preferably, as shown in Figure 3, described public electrode 105 is along the part of described data line 101a direction, form in same processing step with the part 11 of described public electrode 105 along described sweep trace 101b direction, and described common point and 105 and described pixel electrode 104 also in same processing step, form, can save processing step like this.
Preferably, as shown in Figure 3, described public electrode 105 is along also being provided with shield bars 102 under the part of described data line 101a direction.Described shield bars 102 can be positioned at same one deck with the grid of described thin film transistor (TFT) 110, is formed in same processing step by commaterial; Perhaps, shown in Fig. 3 C, described shield bars 102 can be positioned at same layer with the source/drain electrode of described thin film transistor (TFT) 110, is formed in same processing step by commaterial.When described shield bars 102 and described sweep trace 101b are during with one deck, it is very near even have overlapping that described shield bars 102 and described data line 101a can lean on, thereby the light-permeable area that can further increase pixel 100 like this increases aperture opening ratio, and requires also lower to the etching precision between described shield bars 102 and the described data line 101a.
Preferably, shown in Fig. 3 C, described shield bars 102 is connected with described public electrode 105, like this, can reduce the line resistance of walking of described public electrode 105.And, when public electrode 105 when data line 101a direction opens circuit, because described shield bars 102 is connected with described public electrode 105, so can effectively avoid the display defect that opens circuit and cause owing to public electrode 105.
Preferably, described shading strip 103 is positioned at same one deck with the grid of described thin film transistor (TFT) 110, is formed in same processing step by commaterial; Perhaps described shading strip 103 is positioned at same layer with the source/drain electrode of described thin film transistor (TFT) 110, is formed in same processing step by commaterial.When the source/drain electrode of described shading strip 103 and described thin film transistor (TFT) 110 was positioned at same layer, described shading strip 103 was an integral body that is communicated with described drain electrode, can save via hole 1.
Preferably, described shading strip 103 and described shield bars 102 are positioned at same one deck, and both are an integral body that is communicated with, and are formed in processing step by commaterial.Like this, only needing to make a via hole just can couple together described shading strip 103, described shield bars 103 and described public electrode 105.
In the present embodiment, the material of described pixel electrode 104 is that transparent conductive material is formed, and described pixel electrode 104 is positioned at the last layer of described shading strip 103.Preferably, the width of described shading strip 103 is less than the width of described pixel electrode 104, and like this, the voltage on the described shading strip 103 can not influence described pixel electrode 104 and form horizontal component of electric field with described public electrode 105.
With respect to the dot structure of background technology part, the drain electrode of thin film transistor (TFT) described in the present embodiment 110 and the overlapping area of grid are less, and therefore the stray capacitance of described grid and described drain electrode formation is also less, and the possibility of pixel appearance flicker is also less.
Second embodiment
Fig. 4 is the planar structure synoptic diagram of the single pixel of infrabasal plate of the display panels of second embodiment of the invention.As shown in Figure 4, in the present embodiment, described pixel 100 also is provided with bus 109 in the second memory capacitance zone except having structure identical with first embodiment or identical deformable structure, and the material of described bus 109 is a light-proof material.As described in first embodiment, the present invention is by being provided with the aperture opening ratio that second memory capacitance can increase display panels, but the value of the memory capacitance of whole pixel (i.e. first memory capacitance and the second memory capacitance sum) can not be excessive, because the value of memory capacitance too conference causes pixel 100 undercharges, thereby cause demonstration bad.So the area of described shading strip 103 can not be too big.In the present embodiment,, under the suitable situation of the value that guarantees memory capacitance, guarantee the shading directly over the pixel electrode 104 by bus 109 is set.
Fig. 4 A is the schematic cross-section of second memory capacitance along direction B1-B2.Shown in Fig. 4 A, described bus 109 is positioned at the below of described shading strip 103, and and described shading strip 103 between have insulation course 121, have insulation course 123 between described shading strip 103 and the described pixel electrode 104.Preferably, described bus 109 is positioned at same one deck with described sweep trace 101b, and described shading strip 103 is positioned at same one deck with described data line 101a.Then, described shading strip 103 and described bus 109 are set and do not increase technology and cost.Like this, when the described pixel electrode 104 that forms described second memory capacitance 107 opens circuit, can get final product repair-deficiency by described pixel electrode 104 of laser bonding and described bus 109.
The 3rd embodiment
Fig. 5 is the planar structure synoptic diagram of the single pixel of infrabasal plate of the display panels of third embodiment of the invention.As shown in Figure 5, described bus in the present embodiment 109 is connected with the two ends of described pixel electrode 104 respectively with via hole 4 by via hole 3, and the demonstration that can avoid described pixel electrode 104 to open circuit so effectively causing is bad.
And in the present embodiment, described first memory capacitance 107 and described second memory capacitance constitute by double-layer capacitance, described second memory capacitance along the interface synoptic diagram of B1-B2 direction with shown in Fig. 4 A of Fig. 4.Therefore, can better reduce the light tight area of described pixel 100, thereby better increase aperture opening ratio.
As shown in Figure 5, described bus 109 is connected with described pixel electrode 104 by via hole 3, via hole 4, and therefore, the voltage on the described bus 109 is identical with voltage on the described pixel electrode 104; Described shading strip 103 is connected with public electrode 105 by via hole 2, and the voltage on it is identical with the voltage of described public electrode 105.Described bus 109 and described shading strip 103 and insulation course 121 constitute the part of first memory capacitance 107; Described shading strip 103 and described pixel electrode 104 and insulation course 123 constitute another part of first memory capacitance 107.The similar of the structure of described second memory capacitance and described first memory capacitance 107.Therefore, the storage capacitor construction of the described pixel 100 in the present embodiment more helps reducing the light tight area of described display panels.
The 4th embodiment
Fig. 6 is the planar structure synoptic diagram of the single pixel of infrabasal plate of the display panels of fourth embodiment of the invention.As shown in Figure 6, in the present embodiment, described pixel electrode 104 is an integral body that is communicated with the drain electrode of described thin film transistor (TFT) 110, is formed in same processing step by same conductive layer, this structure has been saved via hole 1 described in the embodiment one and via hole 2, has simplified the structure of described pixel 100.The described pixel electrode of present embodiment and the described shading strip 103 among the above embodiment unite two into one, described pixel electrode 104 is that lighttight conductive material forms, therefore, it is that pixel electrode again can shading, can also form memory capacitance with described public electrode 105.
In the present embodiment, described shield bars 102 can be connected with described public electrode 105, forms in same processing step with described sweep trace 101b or described data line 101a.
Fig. 6 A is the schematic cross-section of described first memory capacitance 107 along the A1-A2 direction.As shown in Figure 6A, be formed with insulation course 121 on the described infrabasal plate 13, be formed with described pixel electrode 104 on described insulation course 121, described pixel electrode 104 forms first memory capacitance with described public electrode 105 and insulation course between the two 123.
The 5th embodiment
Fig. 7 is the planar structure synoptic diagram of the single pixel of infrabasal plate of the display panels of fifth embodiment of the invention.As shown in Figure 7, in the present embodiment, except having the structure identical with the 4th embodiment, the expansion electrode 104a that also has pixel electrode 104, described expansion electrode 104a is connected with described pixel electrode 104, described connection can be in any place in the zone of described pixel electrode 104 and described expansion electrode 104a overlapping via hole to be set, and also can be that described expansion electrode 104a directly is formed on the described pixel electrode 104.Wherein, described pixel electrode 104 is formed by opaque conductive material, and described expansion electrode 104a is formed by transparent conductive material.Like this, described expansion electrode 104a has been equivalent to increase the electrode width of described pixel electrode 104, but does not reduce the area of the transmission region of described pixel 100; And the described expansion electrode 104a defective that also can effectively avoid described pixel electrode 104 to open circuit and cause.
Fig. 7 A be among Fig. 7 pixel electrode 104 places along a kind of schematic cross-section of A1-A2 direction.Shown in Figure 7 is a kind of embodiment that described pixel electrode 104 is connected with described expansion electrode 104a, on infrabasal plate 13, be formed with insulation course 121, described pixel electrode 104 is arranged on the described insulation course 121, described expansion electrode 104a is connected with described pixel electrode 104, also has insulation course 123 between the two, certainly, described expansion electrode 104a also can directly be formed on the described pixel electrode 104, and does not have insulation course 123.
In the present embodiment, described pixel electrode 104 is an integral body that is communicated with the drain electrode of described thin film transistor (TFT) 110, not needing to be provided with separately via hole is connected the drain electrode of described pixel electrode 104 and described thin film transistor (TFT) 110, make simple in structure, and the described pixel electrode 104 in the described first memory capacitance zone and described sweep trace be not at same one deck, so the requirement to etching precision is lower between the two.
In the present embodiment, Fig. 8 is another structural representation of planar structure of the single pixel of infrabasal plate of display panels.As shown in Figure 8, described pixel electrode 104 and described sweep trace are by forming with one deck conductive material, and described pixel electrode 104 is connected by via hole with the drain electrode of described thin film transistor (TFT) 110.Fig. 8 A is the schematic cross-sections of 104 places of pixel electrode described in Fig. 8 along the A1-A2 direction.Shown in Fig. 8 A, be formed with described pixel electrode 104 on the described infrabasal plate 13, described pixel electrode 104 is same conductive layer with the grid of thin film transistor (TFT) 110, described expansion electrode 104a is connected with described pixel electrode 104, have insulation course 121 and/or insulation course 123 between the two, perhaps do not have insulation course between the two.
The 6th embodiment
Fig. 9 is the planar structure synoptic diagram of the single pixel of infrabasal plate of the display panels of sixth embodiment of the invention.In the present embodiment, the display mode of display panels is the fringing field display mode.Described public electrode 105 is positioned under the described pixel electrode 104, and described pixel electrode 104 materials are light-proof material, also has the expansion electrode 104a that is connected with it on the described pixel electrode 104.The width of described like this pixel electrode 104 has been widened by described expansion electrode 104a's, but the glazed area of described pixel 100 does not reduce, and increased the electric field space scope that described pixel electrode 104 produces by described expansion electrode 104a, electric field intensity between described pixel electrode 104 and the described public electrode 105 has been increased, thereby can reduce the power consumption of whole liquid crystal panel.
Fig. 9 A is the schematic cross-section of described pixel 100 along the B1-B2 direction.Shown in Fig. 9 A, be formed with public electrode 105 at first on the described infrabasal plate 13, be formed with insulation course 123 on described public electrode 105, described pixel electrode 104 is positioned on the described insulation course 123, and also is formed with expansion electrode 104a on the described pixel electrode 104.Therefore, the liquid crystal molecule between the upper and lower substrate rotates under the effect of the horizontal component of electric field that described pixel electrode 104 and described public electrode 105 forms.
The 7th embodiment
Present embodiment is a kind of manufacture method of display panels, and the manufacture method of described display panels comprises step at least:
On infrabasal plate, form grid conducting layer, and the described grid conducting layer of etching;
Form gate insulator, and semiconductor island;
Formation source/drain electrode conductive layer, and the described source of etching/drain electrode conductive layer;
Form transparency conducting layer, and the described transparency conducting layer of etching;
It is characterized in that, also comprise: form the shading strip layer, and the described shading strip layer of etching.
Wherein, described formation shading strip layer and described formation grid conducting layer are same step.
Wherein, described formation shading strip layer and described formation source/drain electrode conductive layer are same step.
Wherein, described manufacture method also comprises the formation pixel electrode layer, and described formation pixel electrode layer and described formation grid conducting layer are same step.
Wherein, described manufacture method also comprises the formation pixel electrode layer, and described formation pixel electrode layer and described formation source/drain electrode conductive layer are same step.
Wherein, described manufacture method also comprises the expansion electrode layer that forms shading strip, and the expansion electrode layer of described formation shading strip and described formation transparency conducting layer are same step.
Wherein, described manufacture method also comprises formation shield bars layer.
Wherein, described formation shield bars layer and described formation grid conducting layer are same step.
Wherein, described formation shield bars layer and described formation source/drain electrode conductive layer are same step.
Wherein, described manufacture method also comprises the formation common electrode layer, and described formation common electrode layer and described formation transparency conducting layer are same step.
Wherein, described manufacture method also comprises the formation pixel electrode layer, and described formation pixel electrode layer and described formation common electrode layer are same step.
Though the present invention with preferred embodiment openly as above; right its is not in order to limit the present invention; any those skilled in the art; under the situation that does not break away from the spirit and scope of the present invention; can change and revise, so protection scope of the present invention is as the criterion with the claim institute restricted portion that is proposed.
Claims (30)
1. display panels, described display panels comprises:
Upper substrate;
Infrabasal plate is oppositely arranged with described upper substrate;
Liquid crystal layer, between described upper substrate and described infrabasal plate, the liquid crystal molecule in the described liquid crystal layer rotates in the plane that is parallel to described upper substrate or described infrabasal plate;
Be formed with a plurality of pixels that data line and sweep trace by cross arrangement surround on the described infrabasal plate;
Each described pixel comprises: pixel electrode, public electrode, first memory capacitance and thin film transistor (TFT), wherein, the top crown of described first memory capacitance is connected with one of described pixel electrode or described public electrode, bottom crown is connected with in described pixel electrode or the described public electrode another, the grid of described thin film transistor (TFT) is connected with described sweep trace, the source electrode of described thin film transistor (TFT) is connected with described data line, and the drain electrode of described thin film transistor (TFT) is connected with described pixel electrode;
It is characterized in that each described pixel also comprises shading strip, described shading strip and described pixel electrode and/or described public electrode have overlapping.
2. display panels according to claim 1 is characterized in that, described shading strip is connected with described drain electrode or described shading strip is connected with described public electrode.
3. display panels according to claim 1 is characterized in that, described shading strip be positioned at described pixel electrode and/or described public electrode under or directly over.
4. display panels according to claim 1 is characterized in that, described shading strip is described pixel electrode and/or described public electrode.
5. display panels according to claim 1 is characterized in that, also comprises second memory capacitance that is formed by described pixel electrode and described public electrode.
6. display panels according to claim 1 is characterized in that described public electrode is formed by transparent conductive material.
7. display panels according to claim 9 is characterized in that, the material of described pixel electrode is identical with the material of described public electrode.
8. display panels according to claim 1 is characterized in that, also comprises shield bars, and described shield bars and the projection of described public electrode on infrabasal plate have overlapping.
9. display panels according to claim 8 is characterized in that, also comprises the expansion electrode, and described expansion electrode is connected with described pixel electrode.
10. display panels according to claim 9 is characterized in that, described expansion electrode is connected by via hole with described pixel electrode, and perhaps described expansion electrode directly is formed on the described pixel electrode.
11. display panels according to claim 8 is characterized in that, described shield bars is connected with described public electrode and/or described shading strip.
12. display panels according to claim 8 is characterized in that, described shading strip and described sweep trace are formed by same conductive layer.
13. display panels according to claim 14 is characterized in that, described shield bars and described shading strip are formed by same conductive layer.
14. display panels according to claim 8 is characterized in that, described shading strip and described data line are formed by same conductive layer.
15. display panels according to claim 14 is characterized in that, described shield bars and described shading strip are formed by same conductive layer.
16. display panels according to claim 8 is characterized in that, also comprises bus, described bus and the projection of described pixel electrode on infrabasal plate have overlapping.
17. display panels according to claim 16 is characterized in that, described bus is connected with described pixel electrode.
18., it is characterized in that the display mode of described display panels is coplane conversion type or edge field pattern display mode according to each described display panels in the claim 1 to 17.
19. a display panels, described display panels comprises:
Upper substrate;
Infrabasal plate is oppositely arranged with described upper substrate;
Liquid crystal layer, between described upper substrate and described infrabasal plate, the liquid crystal molecule in the described liquid crystal layer rotates in the plane that is parallel to described upper substrate or described infrabasal plate;
Be formed with a plurality of pixels that data line and sweep trace by cross arrangement surround on the described infrabasal plate;
Each described pixel comprises: pixel electrode, public electrode, first memory capacitance and thin film transistor (TFT), wherein, the top crown of described first memory capacitance is connected with one of described pixel electrode or described public electrode, bottom crown is connected with in described pixel electrode or the described public electrode another, the grid of described thin film transistor (TFT) is connected with described sweep trace, the source electrode of described thin film transistor (TFT) is connected with described data line, and the drain electrode of described thin film transistor (TFT) is connected with described pixel electrode;
It is characterized in that described pixel electrode is formed by the conductive layer of the grid that forms described thin film transistor (TFT) or source/drain electrode.
20. the manufacture method of a display panels, the manufacture method of described display panels comprises step at least:
On infrabasal plate, form grid conducting layer, and the described grid conducting layer of etching;
Form gate insulator, and semiconductor island;
Formation source/drain electrode conductive layer, and the described source of etching/drain electrode conductive layer;
Form transparency conducting layer, and the described transparency conducting layer of etching;
It is characterized in that, also comprise: form the shading strip layer, and the described shading strip layer of etching.
21. the manufacture method of display panels according to claim 20 is characterized in that, described formation shading strip layer and described formation grid conducting layer are same step.
22. the manufacture method of display panels according to claim 20 is characterized in that, described formation shading strip layer and described formation source/drain electrode conductive layer are same step.
23. the manufacture method of display panels according to claim 20 is characterized in that, also comprises the formation pixel electrode layer, described formation pixel electrode layer and described formation grid conducting layer are same step.
24. the manufacture method of display panels according to claim 20 is characterized in that, also comprises the formation pixel electrode layer, described formation pixel electrode layer and described formation source/drain electrode conductive layer are same step.
25. the manufacture method of display panels according to claim 20 is characterized in that, also comprises the expansion electrode layer that forms shading strip, the expansion electrode layer of described formation shading strip and described formation transparency conducting layer are same step.
26. the manufacture method of display panels according to claim 20 is characterized in that, also comprises forming the shield bars layer.
27. the manufacture method of display panels according to claim 26 is characterized in that, described formation shield bars layer and described formation grid conducting layer are same step.
28. the manufacture method of display panels according to claim 26 is characterized in that, described formation shield bars layer and described formation source/drain electrode conductive layer are same step.
29. the manufacture method of display panels according to claim 20 is characterized in that, also comprises the formation common electrode layer, described formation common electrode layer and described formation transparency conducting layer are same step.
30. the manufacture method of display panels according to claim 29 is characterized in that, also comprises the formation pixel electrode layer, described formation pixel electrode layer and described formation common electrode layer are same step.
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