CN101893684B - BIST general basic test module based on system on chip SOC and test system thereof and test method applying same - Google Patents
BIST general basic test module based on system on chip SOC and test system thereof and test method applying same Download PDFInfo
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Abstract
基于片上系统SOC的BIST通用基础测试模块及测试系统及利用此系统的测试方法，它涉及一种混合电路的测试模块及测试方法，它解决了现有的自动测试设备存在的体积大、成本高、限制电流、测试不灵活的问题，测试功能模块由片上系统SOC、跟随器、模拟开关和电平转换电路连接而成。测试系统除包括测试功能模块外，还包括控制器。测试方法具体如下：一、片上系统SOC控制模拟开关由工作状态转换到测试状态；二、产生激励信号；三、对响应信号进行A/D采样，并存储采样结果；四、根据采样结果的数据传输方式进行数据处理并显示结果；五、片上系统SOC控制模拟开关测试状态转换到工作状态。本发明适用于混合电路的测试。
The BIST general-purpose basic test module and test system based on the system-on-chip SOC and the test method using this system relate to a test module and test method of a hybrid circuit, which solves the problem of large volume and high cost of the existing automatic test equipment , limiting current, and testing inflexibility, the test function module is composed of a system-on-chip SOC, a follower, an analog switch, and a level conversion circuit. The test system includes not only test function modules but also controllers. The test method is as follows: 1. The system-on-chip SOC controls the analog switch from the working state to the test state; 2. Generates an excitation signal; 3. Performs A/D sampling on the response signal and stores the sampling result; 4. Data based on the sampling result The transmission mode performs data processing and displays the results; 5. The system-on-chip SOC controls the transition from the test state of the analog switch to the working state. The invention is suitable for testing of hybrid circuits.
Description
Technical field
The present invention relates to a kind of test module and method of testing of plate level hybrid circuit.
Background technology
Along with development of electronic technology, electronic system becomes and becomes increasingly complex.Often comprise digital circuit, mimic channel in the common electronic system, programming devices such as microprocessor and FPGA, elder generation and then complicated electronic equipment have also brought the heavy test and the problem of fault diagnosis when improving system performance.Therefore, the design phase just should be considered the problem of testing, and so just can be beneficial to the test and the fault diagnosis of whole life cycle.Experimental studies results shows, the overall principle of test is that the total system with complicacy is divided into the plurality of sub functional module by functional requirement, handles respectively then.Usually can processing procedure be divided into two-stage: status monitoring and fault diagnosis, the former is means with the functional test, according to the state of monitoring, realizes the localization of fault of functional module level; Latter's target then is on the basis that module has been located, further to pass through the method for road build-in test, and localization of fault is arrived component-level.Modem electronic circuitry is used the present situation of core integrated circuit and auxiliary Resistor-Capacitor Unit, and the actual needs that makes fault diagnosis is not to navigate to each capacitance resistance ware.But in order to embody the versatility of basic test module, tackle then that it is well-designed, suitably arrange the configuration of function, then can satisfy requirements of one's work when truly having this specific (special) requirements in system.Certainly, the verification and measurement ratio of requirement and isolation rate are high more, then to measure, the measuring point of excitation and ground connection also just should be many more.But, after adopting the piecemeal test, the actual measuring point of ultimate demand might not be a lot, and can use a plurality of basic test modules when needed usually.
The inexorable trend that BIT and BIST (Build-in-Self-Test) are the widespread uses of reply electronic circuit, requirement improves constantly to electronic circuit test.Its intension is in tested electric function circuit, to add relevant hardware and software test circuit, in order to realize and to improve the technology of selftest ability.Adopt this technology, can carry out the planning of method of testing in the design phase by product and circuit designers, thus can obviously simplify testing procedure and to the requirement of testing apparatus, shorten the test duration, reduce testing cost.BIST is on the BIT basis; Operational testing process, the terminal works of handling test result be also placed in the circuit-under-test realize; Therefore can further reduce the degree of dependence of test process, improve the independent ability of test automatically of implementing automatic test equipment (ATE).BIST test is owing to rely on test circuit additional in the tested electric function circuit board to realize test fully, therefore with based on the tradition of ATE equipment automatically test with BIT test compare, need arrive more consideration and deliberation test event and content measurement naturally.
The method of testing of digital circuit and mimic channel has a great difference, therefore should adopt different test circuits and method.The widely-used PLD (like FPGA, CPLD etc.) of the realization of digital circuit at present; They have all supported the IEEE1149.1 boundary-scan function; Therefore can directly use the digital boundary scan testing methods of STA400, there is no need to dispose voluntarily the basic test circuit module of BIT.Yet, very different for mimic channel, not only can not scan measuring point, and be exactly integrated circuit for separating the arrangements of components simulating boundary such as resistance, electric capacity, inductance etc., the analog element that does not also at all have reality supply to select for use can be supported IEEE1149.4.STA400 is the boundary scanning chip that only a few can obtain from market; Although the function of its multiway analog switch own can be conveniently used for realizing the switching between systemic-function circuit and the test circuit; The ABM of its pin also can be used to connect the different measuring points of institute's slowdown monitoring circuit; But its valency height is hard to buy, and therefore internal switch can only need well-designed current limiting measures through the electric current of 500uA.
Simulating boundary scanning technique based on STA400 just provides virtual flexibly measuring point through ABM in the sheet for the simulation circuit-under-test, and system also is required to be chip pin AT1 and AT2 provides test and excitation source and metering circuit.The test and excitation of considering mimic channel is also much complicated than digital circuit, not only is divided into the output of voltage and electric current, but also possibly need the different waveforms amplitude of output, frequency.Like this, not only need control the switching that jtag interface comes treatment channel to operation, but also appropriate signals generator and data acquisition unit need be provided, want in addition to realize the data necessary processing capacity at STA400.Support above-mentioned basic hardware function though can utilize the microprocessor (such as DSP, single-chip microcomputer etc. on the plate) of circuit itself; Come concrete control test circuit but also still need develop corresponding firmware management program, thereby the designer of electronic circuit module is proposed higher requirement.
Summary of the invention
The present invention is big for the volume that solves existing ATE and exist, cost is high, limit electric current, test inflexible problem, provide a kind of based on SOC(system on a chip) SOC BIST general basic test module and test macro and utilize the method for testing of this system.
BIST general basic test module based on SOC(system on a chip) SOC; It comprises SOC(system on a chip) SOC, second follower, the 3rd follower, first analog switch, second analog switch, level shifting circuit, pumping signal connector and response signal connector; The square-wave signal output terminal of SOC(system on a chip) SOC1 links to each other with the first via signal input part of first analog switch; The signal output part of first analog switch links to each other with the signal input part of pumping signal connector; The signal output part of response signal connector links to each other with the signal input part of second analog switch; The signal output part of second analog switch links to each other with the signal input part of the 3rd follower; The signal output part of the 3rd follower links to each other with the signal input part of level shifting circuit; The signal output part of level shifting circuit links to each other with the input end of analog signal of SOC(system on a chip) SOC, and the first analog switch control signal output terminal of SOC(system on a chip) SOC links to each other with the signal input end of first analog switch, and the second analog switch control signal output terminal of SOC(system on a chip) SOC links to each other with the signal input end of second analog switch.
Employing is based on the test macro of the BIST general basic test module of SOC(system on a chip) SOC; It comprises BIST general basic test module, serial data communication circuit and controller based on SOC(system on a chip) SOC; Said BIST universal test functional module based on SOC(system on a chip) SOC comprises SOC(system on a chip) SOC, second follower, the 3rd follower, first analog switch, second analog switch, level shifting circuit, pumping signal connector and response signal connector; The square-wave signal output terminal of SOC(system on a chip) SOC links to each other with the signal input part of second follower; The signal output part of second follower links to each other with the first via signal input part of first analog switch; The signal output part of first analog switch links to each other with the signal input part of pumping signal connector; The signal output part of response signal connector links to each other with the signal input part of second analog switch; The signal output part of second analog switch links to each other with the signal input part of the 3rd follower; The signal output part of the 3rd follower links to each other with the signal input part of level shifting circuit; The signal output part of level shifting circuit links to each other with the input end of analog signal of SOC(system on a chip) SOC, and the first analog switch control signal output terminal of SOC(system on a chip) SOC links to each other with the signal input end of first analog switch, and the second analog switch control signal output terminal of SOC(system on a chip) SOC links to each other with the signal input end of second analog switch; SOC(system on a chip) SOC links to each other with the serial data communication end of controller through the serial data communication circuit.
Based on the method for testing of the BIST general basic test macro of SOC(system on a chip) SOC, concrete steps are following:
Test macro is connected with tested electric function circuit; The signal output part of the pumping signal connector of said test macro links to each other with the pumping signal input end of tested electric function circuit, and the response signal output terminal of tested electric function circuit links to each other with the signal input part of the response signal connector of test macro;
Controller is according to the annexation of schematic diagram and the test macro and the tested electric function circuit of tested electric function circuit; Definite pumping signal parameter that will be provided with and corresponding pumping signal connector pin, and send said pumping signal parameter and corresponding pumping signal connector pin information is given SOC(system on a chip) SOC;
SOC(system on a chip) SOC produces pumping signal according to the parameter information of the pumping signal that controller sends, and said pumping signal is sent to corresponding pumping signal connector pin through first analog switch, injects tested electric function circuit at last;
SOC(system on a chip) SOC gathers each response signal in the tested electric function circuit respectively through controlling second analog switch, and the corresponding signal that collects is changed the back as test result data through A/D;
SOC(system on a chip) SOC1 is sent to controller with the measurement result data through the serial data communication end;
Controller goes out diagnosis and isolation rate according to the measurement result data computation.
The present invention proposes a kind of BIST general basic test function module based on SOC(system on a chip) SOC that satisfies small-sized hybrid circuit test; Size is little, cost is low, test is flexible; Lower to excitation with the requirement of sampling; The test circuit structure of simplifying makes it concentrate the general BIST basic test function of performance.It is on the socket of its configuration that BIST basic test functional module of the present invention can be inserted in the tested electric function circuit 7 easily, only need take the basic function that very little circuit area just can be realized test circuit.Tested electric function circuit 7 is made up of a plurality of circuit modules often, and doing as a whole the test to circuit is the comparison difficulty, and the single circuit module of independent test is then relatively easy.Like this, use BIST basic test functional module of the present invention and can be directed against different circuit-under-tests, dispose the disparate modules of different parameters respectively and test respectively.
Description of drawings
Fig. 1 is the structural representation based on the BIST general basic test module of SOC(system on a chip) SOC.Fig. 2 is the structural representation of employing based on the test macro of the BIST general basic test module of SOC(system on a chip) SOC.Fig. 3 is the voltage-controlled BPF. test circuit of a second order surface chart.Fig. 4 is a kind of circuit theory diagrams based on the BIST general basic test module of SOC(system on a chip) SOC.
Embodiment
Embodiment one, combination Fig. 1 explain this embodiment; BIST general basic test module based on SOC(system on a chip) SOC; It comprises SOC(system on a chip) SOC1, the second follower 3-2, the 3rd follower 3-3, the first analog switch 4-1, the second analog switch 4-2, level shifting circuit 5, pumping signal connector 9-1 and response signal connector 9-2; The square-wave signal output terminal of SOC(system on a chip) SOC1 links to each other with the signal input part of the second follower 3-2; The signal output part of the second follower 3-2 links to each other with the first via signal input part of the first analog switch 4-1; The signal output part of the first analog switch 4-1 links to each other with the signal input part of pumping signal connector 9-1; The signal output part of response signal connector 9-2 links to each other with the signal input part of the second analog switch 4-2; The signal output part of the second analog switch 4-2 links to each other with the signal input part of the 3rd follower 3-3, and the signal output part of the 3rd follower 3-3 links to each other with the signal input part of level shifting circuit 5, and the signal output part of level shifting circuit 5 links to each other with the input end of analog signal of SOC(system on a chip) SOC1; The first analog switch control signal output terminal of SOC(system on a chip) SOC1 links to each other with the signal input end of the first analog switch 4-1, and the second analog switch control signal output terminal of SOC(system on a chip) SOC1 links to each other with the signal input end of the second analog switch 4-2.
The abbreviation of SOC:System On Chip is called system level chip, and the title SOC(system on a chip) is also arranged, and is an integrated circuit that application-specific target is arranged, and wherein comprises holonomic system and the full content of embedded software is arranged.
In test process; Tested electric function circuit 7 test and excitation signal input parts link to each other with the signal output part of pumping signal connector 9-1 of the present invention; Be used to inject pumping signal; The test response signal output terminal of tested electric function circuit 7 links to each other with the signal input part of response signal connector 9-2 of the present invention, is used to gather response signal.
SOC(system on a chip) SOC1 can select C8051F320, C8051F342, C8051F343, C8051F346 or the C8051F347 model single-chip microcomputer that has the A/D translation function for use, and its inner exportable frequency of programmable counter array (PCA) is up to the frequency adjustable joint square wave of 6MHz; The first follower 3-1, the second follower 3-2 and the 3rd follower 3-3 can adopt TL084 model operational amplifier to realize; The first analog switch 4-1 can adopt the CD4053 pattern to intend switch and realize; When the first analog switch 4-1 makes the work of BIST general basic test function module; The pumping signal that can select to export is communicated with pumping signal connector 9-1 or disconnection; When said analog switch was off-state, tested electric function circuit 7 can operate as normal, and test circuit just can not exert an influence to the operate as normal of circuit; The second analog switch 4-2 can adopt the CD4051 pattern to intend switch and realize; Realize the purpose that multiple signals are gathered through an A/D change-over circuit realization, particular circuit configurations is referring to Fig. 4.
Embodiment two, combination Fig. 1 explain this embodiment; The difference based on the BIST general basic test module of SOC(system on a chip) SOC of this embodiment and embodiment one is; It also comprises the low-pass filter 2 and the first follower 3-1; The pulse-width signal output terminal of SOC(system on a chip) SOC1 links to each other with the signal input part of low-pass filter 2; The signal output part of low-pass filter 2 links to each other with the signal input part of the first follower 3-1, and the signal output part of the first follower 3-1 links to each other with the first via signal input part of the first analog switch 4-1.
It is 0.4%～99.6% adjustable PWM ripple that programmable counter array (PCA) in the SOC(system on a chip) SOC can produce dutycycle, to this signal filtering, can produce 0～3.3V adjustable DC voltage.
Embodiment three, combination Fig. 1 explain this embodiment; This embodiment and embodiment one or two the difference based on the BIST general basic test module of SOC(system on a chip) SOC are; It also comprises the second operational amplifier 8-2; The signal input part of the said second operational amplifier 8-2 links to each other with the square-wave signal output terminal of SOC(system on a chip) SOC1, and the signal output part of the second operational amplifier 8-2 links to each other with the signal input part of the second follower 3-2.
The second operational amplifier 8-2 that this embodiment increases is used for the amplitude of the square-wave signal of SOC(system on a chip) SOC1 output is adjusted, and promptly to the conversion of level, and then is transferred to the second follower 3-2 and carries out exporting to the first analog switch 4-1 after the shaping.This embodiment has been realized the function to the level adjustment of output drive signal.
Embodiment four, combination Fig. 1 explain this embodiment; This embodiment is the BIST general basic test module based on SOC(system on a chip) SOC with embodiment one, two, three or four difference; It also comprises the first operational amplifier 8-1; The signal input part of the said first operational amplifier 8-1 links to each other with the signal output part of low-pass filter 2, and the signal output part of the first operational amplifier 8-1 links to each other with the signal input part of the first follower 3-1.
Exporting to the first follower 3-1 after the first operational amplifier 8-1 that this embodiment increases is used for the amplitude of the output signal of low-pass filter 2 adjusted again carries out shaping and exports to the first analog switch 4-1.This embodiment has been realized the function to the level adjustment of output drive signal.
Adopting in embodiment three and the embodiment four increases the level conversion of operational amplifier realization to driving voltage, satisfies the requirement of 7 pairs of pumping signal level of different tested electric function circuit.
Embodiment five, combination Fig. 1 explain this embodiment; This embodiment and embodiment one, two, three or four the difference based on the BIST general basic test module of SOC(system on a chip) SOC are; It also comprises the 3rd operational amplifier 8-3; The signal input part of said the 3rd operational amplifier 8-3 links to each other with the signal output part of the second analog switch 4-2, and the signal output part of the 3rd operational amplifier 8-3 links to each other with the signal output part of the 3rd follower 3-3.
SOC(system on a chip) SOC1 input voltage range requires between 0～3.3V; And the scope of tested electric function circuit 7 voltages input is-5V～5V between; Therefore be transformed between 0～3.3V through the voltage signal between two stage amplifer general-5V～5V, thereby satisfy the requirement of SOC(system on a chip) SOC1 and tested electric function circuit 7 input voltage ranges.
Embodiment six, combination Fig. 2 explain this embodiment; Employing is based on the test macro of the BIST general basic test module of SOC(system on a chip) SOC; It comprises BIST general basic test module 0, serial data communication circuit 8 and controller 6 based on SOC(system on a chip) SOC; Said BIST universal test functional module 0 based on SOC(system on a chip) SOC adopts the described BIST universal test functional module based on SOC(system on a chip) SOC of any embodiment in the embodiment one to five, and said SOC(system on a chip) SOC1 links to each other with the serial data communication end of controller 6 through serial data communication circuit 8.
Embodiment seven, adopt the method for testing of the described BIST general basic test macro based on SOC(system on a chip) SOC of embodiment six, concrete steps are following:
Test macro is connected with tested electric function circuit 7; The signal output part of the pumping signal connector 9-1 of said test macro links to each other with the pumping signal input end of tested electric function circuit 7, and the response signal output terminal of tested electric function circuit 7 links to each other with the signal input part of the response signal connector 9-2 of test macro;
SOC(system on a chip) SOC1 produces pumping signal according to the parameter information of the pumping signal that controller sends, and said pumping signal is sent to corresponding pumping signal connector 9-1 pin through the first analog switch 4-1, injects tested electric function circuit 7 at last;
SOC(system on a chip) SOC1 gathers each response signal in the tested electric function circuit respectively through controlling the second analog switch 4-2, and the corresponding signal that collects is changed the back as test result data through A/D;
SOC(system on a chip) SOC1 is sent to controller 6 with the measurement result data through the serial data communication end;
SOC(system on a chip) SOC1 need carry out electrification reset before testing.After adding excitation, because the delay of circuit and A/D sampling, the generation of response may lag behind, and therefore needs just can read response certain time delay, adopts the counter time-delay in SOC(system on a chip) SOC inside.
Embodiment eight, this embodiment are that " SOC(system on a chip) SOC1 is sent to controller 6 with the measurement result data through the serial data communication end " in the embodiment seven further specified: the response signal that SOC(system on a chip) SOC1 produces tested electric function circuit 7 is carried out the sampling of A/D sampling can carrying out one or many, adopts the continuous mode that sampled data is averaged that repeatedly reads.
In order to ensure the accuracy of data, adopt the continuous mode of averaging that repeatedly reads.Read the number of times of regulation continuously,, average after the completion as ten times.
Embodiment nine, this embodiment are the specific embodiments that utilizes the test macro of the BIST general basic test module based on SOC(system on a chip) SOC of the present invention that the voltage-controlled BPF. of second order is tested; Need the voltage-controlled BPF. groundwork of test second order state, and carry out fault diagnosis.Real process needs the software support, and under the support of PC IDE, carry out parameter configuration, simulation analysis, on-line debugging, until the final parameter run time version that forms in success back, again by BIST basic module independent operating.Fig. 3 shows IDE master interface.
At first; The schematic diagram of the voltage-controlled band pass filter circuit of tested second order is illustrated in main interface; And the voltage-controlled band pass filter circuit of tested second order analyzed, set up test item, promptly confirm to inject the measuring point of pumping signal and need apply which type of test and excitation signal; Need to measure the output response of which measuring point; Comprise measurement contents and scope, the measuring point that will inject pumping signal then is connected with the signal output part of the 9-1 of test macro respectively, and the measuring point of needs being gathered corresponding signal is connected with the signal input part of 9-2 respectively;
The parameter generating pumping signal that SOC(system on a chip) SOC1 sends according to controller, and said pumping signal is sent to corresponding measuring point in the voltage-controlled band pass filter circuit of tested second order through controlling the first analog switch 4-1;
SOC(system on a chip) SOC1 controls the second analog switch 4-2 and gathers the response signal in the tested electric function circuit, and said corresponding signal is done A/D conversion back as test result data;
SOC(system on a chip) SOC1 is sent to controller 6 with the measurement result data through the serial data communication end; Controller 6 carries out simulation analysis with regard to the nominal value of element in the voltage-controlled band pass filter circuit of tested second order and the various combination condition of fault value thereof, and in simulation process, applies and observe the content that is disposed in each test item.Emulation can be carried out through mathematical relation and circuit relationships dual mode, and its result at first sets up fault-sign relation.
Can be during practical application at first according to the basic condition configuration measuring point and the pumping signal that directly realize easily; If the calculating of diagnosis and the isolation rate of simulation analysis that condition carries out can not be satisfied the demand according to this, recomputate again after can increasing test item (measuring point and pumping signal).Obviously test item is more, then diagnosis and isolation rate just maybe be high more, until satisfying deviser's needs.After this can get back to the main frame face of IDE, continue the actual test process of operation.After promptly obtaining the measured result of each test item, diagnose according to fault-sign relation that simulation analysis is set up.After test obtained experience repeatedly to circuit-under-test, the test code that regeneration is final downloaded to the BIST basic module.
Here, at first define measuring point Tp1, Tp2, Tp3, Tp4, Tp5, represent Ui, U1, Uo, U+ and U-respectively.Intuitively observe then, can consider to add analog stimulus, test the output response of other 4 measuring points, and, record the frequency response under the different incentive actions through changing the adjustable frequency of ac square wave at the input place Ui of bandwidth-limited circuit.
Test process shows that blur level is thinner, the isolation rate is high more, and then required measuring point and excitation/response contents are many more, and it is also just big more to test required cost.Diagnosis often very need not navigate to each element in the practical application, if really need navigate to each components and parts certainly, increases corresponding testing cost so and just can meet the demands.
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| CN105808405B (en) * | 2016-04-12 | 2018-10-23 | 江南大学 | A kind of high-performance pipeline ADC frequency domain parameter assessment system based on SoPC |
| JP6920836B2 (en) * | 2017-03-14 | 2021-08-18 | エイブリック株式会社 | Semiconductor device |
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| CN109508551B (en) * | 2018-11-08 | 2023-01-06 | 成都卫士通信息产业股份有限公司 | Safe system switching method and device, electronic equipment and storage medium |
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| CN1661388A (en) * | 2004-02-26 | 2005-08-31 | 三星电子株式会社 | System-on-chip (SOC) having built-in-self-test circuits and a self-test method of the SOC |
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| US6874110B1 (en) * | 2000-05-11 | 2005-03-29 | Stretch, Inc. | Apparatus and method for self testing programmable logic arrays |
| US7313739B2 (en) * | 2002-12-31 | 2007-12-25 | Analog Devices, Inc. | Method and apparatus for testing embedded cores |
| US7134061B2 (en) * | 2003-09-08 | 2006-11-07 | Texas Instruments Incorporated | At-speed ATPG testing and apparatus for SoC designs having multiple clock domain using a VLCT test platform |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN1661388A (en) * | 2004-02-26 | 2005-08-31 | 三星电子株式会社 | System-on-chip (SOC) having built-in-self-test circuits and a self-test method of the SOC |
Non-Patent Citations (2)
| Title |
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| 方祥圣，梁华国，曹先霞.一种低功耗SoC芯片的综合BIST方案.《计算机工程》.2006,第32卷(第15期),245-249. * |
| 朱敏,杨春玲,周文,庞亮.一种组合电路内建自测试的改进方法.《计算机测量与控制》.2008,第16卷(第12期),1806-1808. * |
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