CN101887872A - Heat radiation packaging structure of semiconductor chip - Google Patents
Heat radiation packaging structure of semiconductor chip Download PDFInfo
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- CN101887872A CN101887872A CN 200910203802 CN200910203802A CN101887872A CN 101887872 A CN101887872 A CN 101887872A CN 200910203802 CN200910203802 CN 200910203802 CN 200910203802 A CN200910203802 A CN 200910203802A CN 101887872 A CN101887872 A CN 101887872A
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- heat
- material layer
- packaging structure
- chip
- heat dissipation
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Images
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/27—Manufacturing methods
- H01L2224/27011—Involving a permanent auxiliary member, i.e. a member which is left at least partly in the finished device, e.g. coating, dummy feature
- H01L2224/27013—Involving a permanent auxiliary member, i.e. a member which is left at least partly in the finished device, e.g. coating, dummy feature for holding or confining the layer connector, e.g. solder flow barrier
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
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- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
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- H01L2224/73253—Bump and layer connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/831—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus
- H01L2224/83101—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus as prepeg comprising a layer connector, e.g. provided in an insulating plate member
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
Abstract
The invention discloses a heat dissipation packaging structure of a semiconductor chip, which comprises a substrate, a frame body, a heat dissipation sheet and a heat conduction interface material layer. The substrate bears and is electrically connected with at least one chip. The frame body is combined around the substrate. The heat sink is provided with a combination surface combined with the frame body, and the combination surface is further provided with a heat conduction area. The heat conducting area is provided with a retaining wall so as to form a material limiting space in a surrounding mode. The heat conduction interface material layer is accommodated in the material limiting space. The chip is provided with a heat dissipation surface which extends into the material limiting space. The heat-conducting interface material layer is clamped between the heat-conducting area of the radiating fin and the radiating surface of the chip. The material limiting space is used for avoiding the defects of overflow or gaps and the like of the heat conducting interface material layer during the high-temperature process.
Description
[technical field]
The present invention relates to a kind of radiating packaging structure of semiconductor chip, particularly about a kind of radiating packaging structure that can prevent the semiconductor chip in generation overflow of heat conduction dielectric surface material layer or space.
[background technology]
Now, the semiconductor packages industry is in order to satisfy the demand of various high-density packages, develop the packaging structure that various different types gradually, wherein common packaging structure with substrate (substrate) comprises baii grid array packaging structure (ball grid array, BGA), stitch grid array encapsulation structure (pin grid array, PGA), land grid array package structure (land grid array, chip encapsulation construction LGA) or on the substrate (board on chip, BOC) etc.In above-mentioned packaging structure, the upper surface of described substrate carries at least one chip, and several connection pads of chip is electrically connected to several weld pads of the upper surface of described substrate by routing (wire bonding) or projection (bumping) processing procedure.Simultaneously, the lower surface of described substrate also must provide a large amount of weld pads, to weld several outputs, and tin ball for example.After finishing above-mentioned packaging structure with substrate, it can be fixed to by surface mounting technology (SMT) on the electronic installations such as motherboard.When power supply made its running by described packaging structure, the chip of described packaging structure usually can be because circuit itself possesses resistance and inevitably produces heat energy.Therefore, must utilize suitable heat-dissipating structure,, burn because of overheated to avoid described chip so that timely described chip is dispelled the heat.
For example, please refer to Figure 1A, 1B and 1C, it discloses a kind of assembling schematic diagram of radiating packaging structure of existing semiconductor chip.Shown in Figure 1A, at first, provide a substrate 11, its upper surface electrically connects and carries a chip 12.Then, a framework 14 is fixed on around the upper surface of described substrate 11, makes described chip 12 be positioned at described framework 14 by an adhesion layer 13.Subsequently, again another adhesion layer 15 is coated on the upper surface of described framework 14.On the other hand, provide a fin 16, and form a wetting layer 161, with in conjunction with heat conduction dielectric surface material layer (thermal interfacematerial, TIM) 17 at its lower surface.Moreover, shown in Figure 1B, utilize described adhesion layer 15 that described fin 16 is combined on the described framework 14, utilize described heat conduction dielectric surface material layer 17 that described fin 16 is combined on the described chip 12 simultaneously.Preliminary in conjunction with after, utilize proper temperature (about 160 ℃) to toast (cure), described adhesion layer 15 is solidified, and makes that described heat conduction dielectric surface material layer 17 is suitably softening slightly to be combined between described fin 16 and the chip 12.Then, shown in Fig. 1 C, utilize high temperature reflux welding (reflow) mode to plant several tin balls 18, so can finish the assembling processing procedure of a radiating packaging structure at the lower surface of described substrate 11.
Shown in Fig. 1 C, after finishing above-mentioned radiating packaging structure, it can be fixed to by surface mounting technology (SMT) on the electronic installations such as motherboard.When power supply made its running by described radiating packaging structure, the heat energy that described chip 12 produces can conduct to described fin 16 by described heat conduction dielectric surface material layer 17, so that described chip 12 is continued to dispel the heat.Yet, above-mentioned radiating packaging structure still has following problems at the actual assembly process that carries out: shown in Fig. 1 C, when utilizing solder reflow to plant the above tin ball 18, the about 260 ℃ high temperature of essential usually use, described high temperature is a lot of above the temperature (about 160 ℃) of above-mentioned baking processing procedure.But the material of described heat conduction dielectric surface material layer 17 is selected from low-melting soft metal usually, for example indium (In).Because the fusing point of indium is only had an appointment 156 ℃, therefore described heat conduction dielectric surface material layer 17 will absorb heat energy and melt in a large number when carrying out reflow soldering, and outwards overflow to described chip 12 around, form one excessive 171.Simultaneously, because described heat conduction dielectric surface material layer 17 has lost the part material and formed described excessive 171, therefore described heat conduction dielectric surface material layer 17 also can relatedly form at least one space (void) 172 usually in inside.Effective thermal conductive zone that described heat conduction dielectric surface material layer 17 can be reduced in described space 172 can be provided amasss, thereby reduces the radiating efficiency to described chip 12.Moreover, in some cases, if contain air or aqueous vapor in the described space 172, the heat energy that then described chip 12 produces may cause air expansion or the aqueous vapor vaporization in the described space 172, and then cause so-called popcorn effect (popcorn effect), force described heat conduction dielectric surface material layer 17 that slight crack (crack) takes place.As a result, make the radiating efficiency deterioration gradually of described radiating packaging structure, even because of dispelling the heat not as good as causing described chip 12 to burn.Because described heat conduction dielectric surface material layer 17 has the problem of above-mentioned non-refractory processing procedure, therefore in order to ensure encapsulation rate of finished products (yield), described heat conduction dielectric surface material layer 17 only is useful in land grid array package structure (LGA) or the stitch grid array encapsulation structure (PGA) that need not carry out reflow soldering, but and is not suitable for being applied in the baii grid array packaging structure (BGA) that need carry out reflow soldering.As a result, significantly limited the range of application of this type of heat dissipation design.
Therefore, be necessary to provide a kind of radiating packaging structure of semiconductor chip of Improvement type, to solve the existing in prior technology problem.
[summary of the invention]
Main purpose of the present invention provides a kind of radiating packaging structure of semiconductor chip, it is that thermal conductive surface at fin utilizes barricade to form the limit material space, can during carrying out high temperature processing procedure such as reflow soldering, prevent outside the heat conduction dielectric surface material course overflow or produce the space, and then help improving the encapsulation rate of finished products, guarantee the product radiating efficiency and increase the service life.
Secondary objective of the present invention provides a kind of radiating packaging structure of semiconductor chip, it is that lower surface at fin utilizes barricade to form the limit material space, make on the applicable baii grid array packaging structure products such as (BGA) that carries out high temperature reflux welding at need of heat conduction dielectric surface material layer, and then help enlarging the product range of application.
Another object of the present invention provides a kind of radiating packaging structure of semiconductor chip, it is that lower surface utilization point glue mode at fin provides barricade, to form the limit material space, make the not outwards overflow or produce the space of heat conduction dielectric surface material layer, and then help simplifying assembly program and reduce manufacturing cost.
For reaching above-mentioned purpose, the invention provides a kind of radiating packaging structure of semiconductor chip, it comprises a substrate, a framework, a fin and a heat-conducting interface material layer.Described substrate has a loading end, with carrying and electric connection at least one chip.Described framework be incorporated into described substrate loading end around.Described fin has a faying face, is incorporated into described framework around the described faying face.The radiating packaging structure of described semiconductor chip is characterised in that: the faying face of described fin has a thermal conductive zone in addition, its be formed on described faying face around beyond the position, and described thermal conductive zone has a barricade, with around forming a limit material space.Described heat-conducting interface material layer is placed in the described limit material space.Described chip has a radiating surface and stretches in the described limit material space.Described heat-conducting interface material layer is located between the radiating surface of the thermal conductive zone of described fin and described chip.
In a preferred embodiment of the invention, the edge of the thermal conductive zone of described fin forms a ring flange, with as described barricade.
In a preferred embodiment of the invention, described ring flange is selected from metal rim or insulation flange.
In a preferred embodiment of the invention, the thermal conductive zone of described fin is in conjunction with described heat-conducting interface material layer, and the periphery of described heat-conducting interface material layer forms a ring-type point glue portion, with as described barricade.
In a preferred embodiment of the invention, described ring-type point glue portion is coated on the periphery of described heat-conducting interface material layer, and part is coated on the surperficial antelabium of described heat-conducting interface material layer.
In a preferred embodiment of the invention, described ring-type point glue portion is selected from elargol, silica gel, epoxy resin, thermoplastic resin or thermosetting resin.
In a preferred embodiment of the invention, the thermal conductive zone place of described fin forms a groove, and utilizing described groove as described limit material space, and the internal perisporium that utilizes described groove is as described barricade.
In a preferred embodiment of the invention, the thermal conductive zone of described fin is provided with a wetting layer in addition, and described thermal conductive zone is incorporated into described heat-conducting interface material layer by described wetting layer.Described wetting layer is selected from gold, nickel, copper, chromium, silver or its alloy.
In a preferred embodiment of the invention, described heat-conducting interface material layer is selected from indium, tin or its alloy.
In a preferred embodiment of the invention, the radiating surface of described chip is provided with an adhesion layer in addition, and described radiating surface is incorporated into described heat-conducting interface material layer by described adhesion layer.
In a preferred embodiment of the invention, described adhesion layer is selected from titanium, palladium, gold, chromium, copper, nickel or its alloy.
In a preferred embodiment of the invention, described framework has a first surface and a second surface, described first surface utilizes one first adhesion layer to be combined in the loading end of described substrate, reaches described second surface and utilizes one second adhesion layer to be combined in the faying face of described fin.
In a preferred embodiment of the invention, described substrate has a signal output face in addition, and it is combined with several lead-out terminals.
In a preferred embodiment of the invention, described lead-out terminal is selected from tin ball, stitch or contact.
[description of drawings]
Figure 1A to 1C: the assembling schematic diagram of the radiating packaging structure of existing semiconductor chip.
Fig. 2 A to 2C: the assembling schematic diagram of the radiating packaging structure of the semiconductor chip of first embodiment of the invention.
Fig. 3 A to 3D: the assembling schematic diagram of the radiating packaging structure of the semiconductor chip of second embodiment of the invention.
Fig. 4 A to 4C: the assembling schematic diagram of the radiating packaging structure of the semiconductor chip of third embodiment of the invention.
[embodiment]
For allowing above-mentioned purpose of the present invention, feature and advantage become apparent, preferred embodiment of the present invention cited below particularly, and conjunction with figs. are described in detail below:
Please refer to Fig. 2 A, 2B and 2C, the assembling schematic diagram of the radiating packaging structure of the semiconductor chip of its announcement first embodiment of the invention, wherein said radiating packaging structure comprises a substrate 21, at least one chip 22, one first adhesion layer 23, a framework 24, one second adhesion layer 25, a fin 26, a heat-conducting interface material layer 27 and several lead-out terminals 28.The present invention is applicable to common packaging structure with substrate (substrate), chip encapsulation construction (BOC) etc. on baii grid array packaging structure (BGA), stitch grid array encapsulation structure (PGA), land grid array package structure (LGA) or the substrate for example, baii grid array packaging structure particularly, but be not limited to this.
Shown in Fig. 2 A, 2B and 2C, the substrate 21 of first embodiment of the invention is preferably printed circuit board (PCB) (PCB), ceramic circuit board or the flexible PCB (FCB) of single or multiple lift, in the present embodiment, is to be example with the multilayer board, but is not limited thereto.Described substrate 21 has a loading end 211 and a signal output face 212.Described loading end 211 in order to the carrying and in conjunction with above-mentioned other members, for example described chip 22 and framework 24 etc.Described signal output face 212 is another surfaces of described substrate 21 corresponding described loading ends 211, and it is in order to electrically connect described several lead-out terminals 28, and described lead-out terminal 28 can be selected from tin ball, stitch or contact, to constitute dissimilar radiating packaging structures.
Shown in Fig. 2 A, 2B and 2C, the chip 22 of first embodiment of the invention is selected from the chip that the Silicon Wafer cutting forms usually, and it has one active surperficial 221 and one radiating surface 222.In the present embodiment, described active surperficial 221 to towards described substrate 21 and be electrically connected at by several projections 223 on the loading end 211 of described substrate 21, thereby forms a flip-chip (flip chip) structure.Moreover described radiating surface 222 is described chip 22 corresponding described another surfaces of active surperficial 221, and described radiating surface 222 is towards described fin 26.In addition, in one embodiment, the radiating surface 222 of described chip 22 can select to be provided with an adhesion layer 224 in addition, make described radiating surface 222 be incorporated into described heat-conducting interface material layer 27 by described adhesion layer 224, described adhesion layer 224 can be selected from titanium, palladium, gold, chromium, copper, nickel or its alloy, for example chromium-copper-Jin composite bed, titanium-palladium-Jin composite bed, chromium-copper composite bed or chromium-nickel clad etc.
Shown in Fig. 2 A, 2B and 2C, first adhesion layer 23 of first embodiment of the invention and second adhesion layer 25 can be selected from the adhesion material of height endurabilities such as elargol, silica gel, epoxy resin, thermoplastic resin or thermosetting resin, described framework 24 can be drawn materials from metal or plastic cement simultaneously, but also can be selected from the Silicon Wafer or the circuit board of non-functional (dummy).In the present embodiment, described framework 24 is hollow ring frameworks, and its profile is generally square or rectangle haply corresponding to the profile of described substrate 21.Described framework 24 has a first surface (not indicating) and a second surface (not indicating), described first surface utilize described first adhesion layer 23 be combined in described substrate 21 loading end 211 around, and described second surface utilize described second adhesion layer 25 be combined in described fin 26 around.
Shown in Fig. 2 A, 2B and 2C; the fin 26 of first embodiment of the invention can be selected from copper, aluminium, silver, gold, nickel or its alloy; when the material itself of described fin 26 easily during oxidation, also can select plate layer protective layer (not illustrating), for example nickel etc. in its surface.In the present invention, described fin 26 has a faying face 260, and described faying face 260 is incorporated into the second surface of described framework 24 towards described framework 24 by described second adhesion layer 25 around the described faying face 260.Moreover the faying face 260 of described fin 26 has a thermal conductive zone 261 in addition, its be formed on described faying face 260 around beyond the position, the middle position of for example described faying face 260.Described thermal conductive zone 261 has a barricade 262, and to limit material space 263 around forming one, it is in order to be placed in its inside with described heat-conducting interface material layer 27.In the present embodiment, the edge of the thermal conductive zone 261 of described fin 26 forms a ring flange, with as described barricade 262.Described ring flange (being described barricade 262) can select to utilize one-body molded mode to be formed on the edge of described thermal conductive zone 261, perhaps selects to utilize modes such as scolder, adhesive agent, bolting element or ultrasonic waves welded contact to be combined in the edge of described thermal conductive zone 261.When utilizing one-body molded mode to form described barricade 262 (being described ring flange), the material of described barricade 262 is same as described fin 26; When utilizing combination to form described barricade 262, described barricade 262 can be selected from metal rim or insulation flange.In addition, the thermal conductive zone 262 of described fin 26 can select to be provided with a wetting layer 264 in addition, and described thermal conductive zone 262 is incorporated into described heat-conducting interface material layer 27 by described wetting layer 264, to increase the bond strength between the dissimilar metal.Described wetting layer 264 can be selected from gold, nickel, copper, chromium, silver or its alloy, for example metal or chromium-copper-Yin composite bed etc.
Shown in Fig. 2 A, 2B and 2C, (thermalinterface material TIM) 27 is selected from indium, tin, other low-melting-point soft metals or its alloy to the heat-conducting interface material layer of first embodiment of the invention usually.In the present embodiment, be to be example, but be not limited thereto with indium (In).Described heat-conducting interface material layer 27 is located between the radiating surface 222 of the thermal conductive zone 261 of described fin 26 and described chip 22.More particularly, described heat-conducting interface material layer 27 has a first surface (not indicating) and a second surface (not indicating), described first surface is incorporated into the thermal conductive zone 261 of described fin 26 by described wetting layer 264, and described second surface is incorporated into the radiating surface 222 of described chip 22 by described adhesion layer 224.
Shown in Fig. 2 A, when the radiating packaging structure of semiconductor chip of assembling first embodiment of the invention, at first prepare described substrate 21, then with active surperficial 221 projection 223 solder bond of described chip 22 on the connection pad (indicating) of the loading end 211 of described substrate 21.Moreover, utilize described first adhesion layer 23 first surface of described framework 24 is combined in described substrate 21 loading end 211 around, and preset described second adhesion layer 25 at the second surface of described framework 24.Then, prepare described fin 26, and utilize suitable mode to be embedded in the limit material space 263 of described fin 26 on described heat-conducting interface material layer 27.At this moment, the first surface of described heat-conducting interface material layer 27 temporarily is incorporated into the thermal conductive zone 261 of described fin 26 by described wetting layer 264.Subsequently, shown in Fig. 2 B, to be combined on the second surface of described framework 24 around the described fin 26 by described second adhesion layer 25, simultaneously the second surface of described heat-conducting interface material layer 27 is incorporated into the radiating surface 222 of described chip 22 by described adhesion layer 224, and the radiating surface 222 of described chip 22 stretches in the described limit material space 263.Then, utilize a proper temperature (about 160 ℃) to toast (cure), described first and second adhesion layer 23,25 is solidified, and make that described heat conduction dielectric surface material layer 27 is suitably softening slightly to be combined between described fin 26 and the chip 22.
Then, shown in Fig. 2 C, the entire heat dissipation packaging structure is inverted, is utilized high temperature reflux welding (reflow) mode to plant the above several lead-out terminals 28, for example tin ball in the signal output face 212 of described substrate 21.At the high temperature reflux weld period, its temperature reaches about 260 ℃.At this moment, have described barricade 262 around the thermal conductive zone of described fin 26 261, can be in order to around forming described limit material space 263, so that described heat-conducting interface material layer 27 is placed in its inside, and limit the outwards overflow of described heat-conducting interface material layer 27.Therefore, even temperature surpasses the fusing point (for example the fusing point of indium is only had an appointment 156 ℃) of the material of described heat-conducting interface material layer 27, defectives such as the excessive or space of the also unlikely generation of described heat-conducting interface material layer 27, thus help improving radiating packaging structure the encapsulation rate of finished products, guarantee the product radiating efficiency and increase the service life.Moreover, because described fin 26 utilizes described barricade 262 to form described limit material space 263, make on the applicable baii grid array packaging structure products such as (BGA) that carries out the high temperature reflux welding at need of described heat conduction dielectric surface material layer 27, thereby also help enlarging the product range of application.
Shown in Fig. 3 A, 3B, 3C and 3D, the assembling schematic diagram of the radiating packaging structure of the semiconductor chip of its announcement second embodiment of the invention.Second embodiment of the invention is similar in appearance to first embodiment of the invention, and continues to use most of figure number of first embodiment, but the radiating packaging structure of the semiconductor chip of described second embodiment has different barricade structures.Shown in Fig. 3 A and 3B, in second embodiment of the invention, when assembling, at first the first surface of described heat-conducting interface material layer 27 temporarily is incorporated into the thermal conductive zone 261 of described fin 26 by described wetting layer 264.Then, form a ring-type point glue portion the utilization of the periphery (thermal conductive zone 261 edges of just described fin 26) of described heat-conducting interface material layer 27, with as a barricade 262 ', it can define equally and form one and limit material space 263 '.In the present embodiment, described ring-type point glue portion (being described barricade 262 ') can be selected from the adhesion material of height endurabilities such as elargol, silica gel, epoxy resin, thermoplastic resin or thermosetting resin.Shown in Fig. 3 C and 3D, described ring-type point glue portion (being described barricade 262 ') not only is coated on the periphery of described heat-conducting interface material layer 27, and part is coated on the antelabium of the second surface of described heat-conducting interface material layer 27.Simultaneously, the radiating surface 222 of described chip 22 stretches in the described limit material space 263 '.Described heat-conducting interface material layer 27 is located between the radiating surface 222 of the thermal conductive zone 261 of described fin 26 and described chip 22.Therefore, be inverted radiating packaging structure and utilize high temperature reflux welding (reflow) mode plant the above several lead-out terminal 28 during, second embodiment of the invention can utilize described ring-type point glue portion (being described barricade 262 ') to provide better limiting material excessive effect, and helps simplifying assembly program and reduce manufacturing cost.
Shown in Fig. 4 A, 4B and 4C, the assembling schematic diagram of the radiating packaging structure of the semiconductor chip of its announcement third embodiment of the invention.Third embodiment of the invention is similar in appearance to first embodiment of the invention, and continues to use most of figure number of first embodiment, but the radiating packaging structure of the semiconductor chip of described the 3rd embodiment has different barricade structures.Shown in Fig. 4 A, in third embodiment of the invention, thermal conductive zone 261 places of described fin 26 utilize punching press suitable modes such as (punching) to form a groove, to utilize described groove as a limit material space 263 ", and the internal perisporium that utilizes described groove (be described limit material space 263 ") is as a barricade 262 ".In when assembling, at first the first surface of described heat-conducting interface material layer 27 temporarily is incorporated into the thermal conductive zone 261 in the groove (be described limit material space 263 ") of described fin 26 by described wetting layer 264.Then, shown in Fig. 4 B and 4C, the radiating surface 222 of described chip 22 is stretched in the described groove (be described limit material space 263 ").Described heat-conducting interface material layer 27 is located between the radiating surface 222 of the thermal conductive zone 261 of described fin 26 and described chip 22.Therefore, when being inverted radiating packaging structure and utilize high temperature reflux welding (reflow) mode to plant the above several lead-out terminal 28, described groove (be described limit material space 263 ") and internal perisporium thereof (be described barricade 262 ") can provide the good excessive effect of limiting material equally.
As mentioned above, in Figure 1A to 1C, have radiating packaging structure now when utilizing solder reflow to plant the above tin ball 18, make described heat conduction dielectric surface material layer 17 produce defectives such as described excessive 171 and space easily, the present invention utilizes this barricade 262 at thermal conductive zone 261 places of this fin 26 among Fig. 2 to 4,262 ' or 262 " form this limit material space 263; 263 ' or 263 ", can during carrying out high temperature processing procedure such as reflow soldering, prevent these heat conduction dielectric surface material layer 27 outside overflows or produce the space, and then help improving the encapsulation rate of finished products, guarantee the product radiating efficiency and increase the service life.Moreover, owing to be useful on the baii grid array packaging structure products such as (BGA) that need carry out the high temperature reflux welding, thereby also help enlarging the product range of application.In addition, the present invention also can utilize described ring-type point glue portion (being described barricade 262 ') to provide better limiting material excessive effect, and helps simplifying assembly program and reduce manufacturing cost.
The present invention is described by above-mentioned related embodiment, yet the foregoing description is only for implementing example of the present invention.Must be pointed out that disclosed embodiment does not limit the scope of the invention.On the contrary, being contained in the spirit of claims and the modification and impartial setting of scope is included in the scope of the present invention.
Claims (10)
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| CN 200910203802 CN101887872A (en) | 2009-05-12 | 2009-05-12 | Heat radiation packaging structure of semiconductor chip |
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| CN 200910203802 CN101887872A (en) | 2009-05-12 | 2009-05-12 | Heat radiation packaging structure of semiconductor chip |
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| CN104064532A (en) * | 2014-06-25 | 2014-09-24 | 中国科学院微电子研究所 | Device packaging structure with heat dissipation structure and manufacturing method |
| CN104871311A (en) * | 2013-03-21 | 2015-08-26 | 日立汽车系统株式会社 | Electronic control apparatus and method for connecting substrate of electronic control apparatus |
| CN105952748A (en) * | 2016-05-17 | 2016-09-21 | 安庆友仁电子有限公司 | Transistor continuous assembling and dispensing device |
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| CN108520867A (en) * | 2018-04-19 | 2018-09-11 | 苏州通富超威半导体有限公司 | Encapsulating structure and welding method |
| CN110767623A (en) * | 2019-09-16 | 2020-02-07 | 珠海格力电器股份有限公司 | Base material, preparation method thereof and circuit substrate |
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| CN104871311A (en) * | 2013-03-21 | 2015-08-26 | 日立汽车系统株式会社 | Electronic control apparatus and method for connecting substrate of electronic control apparatus |
| CN104064532A (en) * | 2014-06-25 | 2014-09-24 | 中国科学院微电子研究所 | Device packaging structure with heat dissipation structure and manufacturing method |
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| CN106298695B (en) * | 2015-06-05 | 2019-05-10 | 台达电子工业股份有限公司 | Packaging module, packaging module stacking structure and manufacturing method thereof |
| CN105952748A (en) * | 2016-05-17 | 2016-09-21 | 安庆友仁电子有限公司 | Transistor continuous assembling and dispensing device |
| CN108520867A (en) * | 2018-04-19 | 2018-09-11 | 苏州通富超威半导体有限公司 | Encapsulating structure and welding method |
| CN110767623A (en) * | 2019-09-16 | 2020-02-07 | 珠海格力电器股份有限公司 | Base material, preparation method thereof and circuit substrate |
| CN111446218A (en) * | 2020-03-31 | 2020-07-24 | 上海兆芯集成电路有限公司 | Chip package |
| CN111446219A (en) * | 2020-03-31 | 2020-07-24 | 上海兆芯集成电路有限公司 | chip package |
| CN111900142A (en) * | 2020-09-04 | 2020-11-06 | 星科金朋半导体（江阴）有限公司 | Chip packaging structure and packaging method thereof |
| CN112382615A (en) * | 2020-11-05 | 2021-02-19 | 海光信息技术股份有限公司 | Power device packaging structure, packaging method and packaging system |
| CN112382615B (en) * | 2020-11-05 | 2023-03-10 | 海光信息技术股份有限公司 | Power device packaging structure, packaging method and packaging system |
| CN114520201A (en) * | 2020-11-19 | 2022-05-20 | 颀邦科技股份有限公司 | Semiconductor heat dissipation package structure and manufacturing method thereof |
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