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CN101872727A - Chip welding method and structure - Google Patents

Chip welding method and structure Download PDF

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Publication number
CN101872727A
CN101872727A CN200910107150A CN200910107150A CN101872727A CN 101872727 A CN101872727 A CN 101872727A CN 200910107150 A CN200910107150 A CN 200910107150A CN 200910107150 A CN200910107150 A CN 200910107150A CN 101872727 A CN101872727 A CN 101872727A
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CN
China
Prior art keywords
chip
substrate
groove
weld pad
welding method
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN200910107150A
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Chinese (zh)
Inventor
傅敬尧
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
AMBIT ELECTRONICS (ZHONGSHAN) Co Ltd
Hon Hai Precision Industry Co Ltd
Original Assignee
AMBIT ELECTRONICS (ZHONGSHAN) Co Ltd
Hon Hai Precision Industry Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by AMBIT ELECTRONICS (ZHONGSHAN) Co Ltd, Hon Hai Precision Industry Co Ltd filed Critical AMBIT ELECTRONICS (ZHONGSHAN) Co Ltd
Priority to CN200910107150A priority Critical patent/CN101872727A/en
Priority to US12/686,514 priority patent/US20100273297A1/en
Publication of CN101872727A publication Critical patent/CN101872727A/en
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B23—MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
    • B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
    • B23K1/00—Soldering, e.g. brazing, or unsoldering
    • B23K1/0008—Soldering, e.g. brazing, or unsoldering specially adapted for particular articles or work
    • B23K1/0016—Brazing of electronic components
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/341—Surface mounted components
    • H05K3/3431—Leadless components
    • H05K3/3436—Leadless components having an array of bottom contacts, e.g. pad grid array or ball grid array components
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B23—MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
    • B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
    • B23K2101/00—Articles made by soldering, welding or cutting
    • B23K2101/36—Electric or electronic devices
    • B23K2101/40—Semiconductor devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8112—Aligning
    • H01L2224/81136—Aligning involving guiding structures, e.g. spacers or supporting members
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/818—Bonding techniques
    • H01L2224/81801—Soldering or alloying
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00011—Not relevant to the scope of the group, the symbol of which is combined with the symbol of this group
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/0105—Tin [Sn]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01075—Rhenium [Re]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/156—Material
    • H01L2924/15786—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
    • H01L2924/15787—Ceramics, e.g. crystalline carbides, nitrides or oxides
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/09372—Pads and lands
    • H05K2201/09472—Recessed pad for surface mounting; Recessed electrode of component
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
    • H05K3/107—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern by filling grooves in the support with conductive material
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50—Manufacturing or production processes characterised by the final manufactured product

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Mechanical Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Electric Connection Of Electric Components To Printed Circuits (AREA)

Abstract

The invention discloses a chip welding method. The method comprises the following steps of: opening a plurality of grooves on the surface of a substrate, and arranging a bonding pad on the bottom of the groove, wherein the thickness of the bonding pad is less than the depth of the groove; connecting the chip with the substrate through a plurality of solder balls, wherein the solder balls fall into the grooves to be contacted with the bonding pad respectively; and allowing the chip and the substrate to pass through a reflow furnace together so that the chip and the substrate are closely combined. The invention also provides a chip welding structure. Because the bonding pad on the substrate has fixed size and fixed position and the solder balls are difficult to deflect from the bonding pad in the presence of the grooves, more reliable combination between the solder balls and the substrate of the chip can be ensured to prevent the open-circuit phenomenon.

Description

A kind of chip welding method and structure
Technical field
The present invention relates to a kind of chip welding method and structure, refer to a kind of brilliant welding method and structure covered especially.
Background technology
Known ceramic base plate surface is the plane, prints conducting resinl on it, to form the chips welding circuit.Conducting resinl is the mixture of metal/non-metal oxide powder and organic solvent, conducting resinl is printed in need be by half tone on the substrate, conducting resinl is positioned on the half tone, is printed on the substrate by scraper, again by leave standstill, the processing procedure of baking, sintering forms circuit or circuit elements device.
Figure 1 shows that in the schematic diagram of known chips welding.Pull in ceramic base and to print conducting resinl on 10, form the chips welding circuit, promptly weld pad 12, and the tin ball 30 that passes through of chip 20 is connected with substrate 10, tin ball 30 with contact, by the reflow stove chip 20 is welded on the weld pad 12 of ceramic substrate 10.Because ceramic substrate 10 surfaces are the plane, when on ceramic substrate 10, printing conducting resinl, because screen painting inherent shortcoming and conducting resinl property difference cause weld pad 12 to have the deviation of size and location, wherein, the scale error that the screen painting inherent shortcoming produces when being meant the half tone design, thus cause the position of weld pad 12 to have deviation; The conducting resinl property difference is meant that there is certain error in the constituent of conducting resinl, and described error can cause the granular size difference of conducting resinl, thereby causes the deviation that has size of weld pad 12.
Therefore, with the described substrate 10 of weld pad 12 that is printed with in the process of chip 20 Overwelding and rewelding furnaces, because the pulling force difference of 12 of each weld pads when weld pad 12 exists the deviation of size and location can cause molten tin, thereby cause failure welding between weld pad 12 and the tin ball 30 and have the open circuit phenomenon.
Summary of the invention
In view of this, the invention provides a kind of on ceramic substrate the method and the structure of welding chip, can avoid substrate and chip chamber failure welding.
Chip welding method in the embodiment of the present invention comprises the steps: to offer a plurality of grooves in substrate surface; Lay conducting resinl in described bottom portion of groove, and to described conducting resinl place toast, sintering so that described conducting resinl forms weld pad; And chip is connected in described substrate by a plurality of tin balls, and and described tin ball is fallen in the described groove respectively, contacting with described weld pad, and with described chip and the common Overwelding and rewelding furnace of described substrate, thereby the two is combined closely.
Chip welded structure in the embodiment of the present invention comprises substrate and chip.Described substrate surface is provided with a plurality of grooves, and described bottom portion of groove is provided with weld pad, and the thickness of described weld pad is less than the degree of depth of described groove; Described chip is connected by the weld pad in the groove on a plurality of tin balls and the described substrate, and described tin ball falls into respectively in the described groove, contact with described weld pad, and with described chip and the common Overwelding and rewelding furnace of described substrate, thereby the two is combined closely.
Preferably, offer described groove by laser technology in described substrate surface.
Preferably, offer described groove by stamping technology in described substrate surface.
Preferably, described weld pad is formed through baking, sintering by conducting resinl.
The chip welded structure of making by described method, because weld pad size, fixed-site on the substrate, and, combine more reliably between the tin ball that can guarantee chip and the substrate because the existence of groove makes the tin ball be difficult for skew with respect to the position of weld pad, avoid the phenomenon of opening a way.
Description of drawings
Fig. 1 is known chip welding method schematic diagram.
Fig. 2 is an embodiment of the present invention chips welding method schematic diagram.
Embodiment
Figure 2 shows that in an embodiment of the present invention the method schematic diagram of welding chip on ceramic substrate.
Fig. 2 (a) is depicted as not processed substrate 40.The present invention's the method for welding chip on ceramic substrate is at first offered a plurality of grooves 42 in not processed substrate 40 surfaces, for convenience of description, comprises 3 grooves 42 in the present embodiment, shown in Fig. 2 (b).Described groove 42 can be processed to form on substrate 40 by laser technology or stamping technology, can certainly form described groove 42 by other processing method.In the present embodiment, the thickness of described substrate 40 is 10 currys (mil), and the degree of depth of described groove 42 is 1 curry (mil), and described groove 42 is a square, and its sectional area is 6 * 6 currys (mil).In other execution mode, described groove 42 also can be other shapes such as circle, ellipse.
After being processed to form described groove 42, lay conducting resinl in described groove 42 bottoms, and to described conducting resinl toast, sintering, thereby make described conducting resinl form weld pad 44.The thickness of described weld pad 44 makes tin ball 50 be contained in the wherein difficult skew in back less than the degree of depth of described groove 42 like this.
At last chip 60 is connected with described substrate 40 by a plurality of tin balls 50, and described tin ball 50 is fallen in the described groove 42 respectively, contacting with described weld pad 44, and with described chip 60 and described substrate 40 common Overwelding and rewelding furnaces, thereby the two is combined closely.
By the present invention's chip welding method, the position of accurate detent 42 is provided with weld pad 44 again in groove 42 earlier, can guarantee the accurate location of weld pad 44 on substrate 40 like this, also can determine the size of weld pad 44.When having served as the reflow stove, chip 60 is welded on the substrate 40 by tin ball 50, described tin ball 50 melts in groove 42 with weld pad 44 and is welded as a whole, groove 42 has limited the offset of the scolding tin of formation when weld pad 44 is with 50 fusings of tin ball in the reflow process owing to its cohesive force generation, thereby has prevented the phenomenon of open circuit between weld pad 44 and the tin ball 50 effectively.
Combine closely reliably between the chip welded structure shown in Fig. 2 (c), chip and substrate by tin ball 50, have excellent electrical property and connect.

Claims (8)

1. a chip welding method is characterized in that, comprising:
Offer a plurality of grooves in substrate surface;
In described bottom portion of groove weld pad is set, the thickness of described weld pad is less than the degree of depth of described groove;
Chip is connected with described substrate by a plurality of tin balls, and described tin ball falls into respectively in the described groove, contacts with described weld pad; And
With described chip and the common Overwelding and rewelding furnace of described substrate, thereby the two is combined closely.
2. chip welding method as claimed in claim 1 is characterized in that described groove is offered in described substrate surface by laser technology.
3. chip welding method as claimed in claim 1 is characterized in that described groove is offered in described substrate surface by stamping technology.
4. chip welding method as claimed in claim 1 is characterized in that, described weld pad is formed through baking, sintering by conducting resinl.
5. a chip welded structure is characterized in that, comprising:
Substrate, described surface is provided with a plurality of grooves, and described bottom portion of groove is provided with weld pad, and the thickness of described weld pad is less than the degree of depth of described groove; And
Chip, described chip is connected by the weld pad in the groove on a plurality of tin balls and the described substrate, and described tin ball falls into respectively in the described groove, contacts with described weld pad, and with described chip and the common Overwelding and rewelding furnace of described substrate, thereby the two is combined closely.
6. chip welded structure as claimed in claim 5 is characterized in that, described weld pad is formed through baking, sintering by conducting resinl.
7. chip welded structure as claimed in claim 5 is characterized in that, described groove is to form in described substrate surface by laser technology.
8. chip welded structure as claimed in claim 5 is characterized in that, described groove is to form in described substrate surface by stamping technology.
CN200910107150A 2009-04-24 2009-04-24 Chip welding method and structure Pending CN101872727A (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
CN200910107150A CN101872727A (en) 2009-04-24 2009-04-24 Chip welding method and structure
US12/686,514 US20100273297A1 (en) 2009-04-24 2010-01-13 Chip packaging method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN200910107150A CN101872727A (en) 2009-04-24 2009-04-24 Chip welding method and structure

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Publication Number Publication Date
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Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103247586A (en) * 2012-02-04 2013-08-14 隆达电子股份有限公司 Chip bonding structure and chip bonding method
CN104465598A (en) * 2014-12-19 2015-03-25 江苏长电科技股份有限公司 Metal lead frame high thermal conductivity flip chip packaging structure and technological method thereof
CN105576110A (en) * 2014-10-31 2016-05-11 首尔伟傲世有限公司 High-efficiency light-emitting device
CN105935844A (en) * 2015-03-03 2016-09-14 发那科株式会社 Substrate manufactured from sheet metal and resin, motor provided with substrate, and soldering method therefor
CN109719381A (en) * 2019-02-21 2019-05-07 巴中市特兴智能科技有限公司 A kind of process of automatic welding bonding gold thread

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CN104425287A (en) * 2013-08-19 2015-03-18 讯芯电子科技（中山）有限公司 Packaging structure and manufacturing method
WO2017015673A1 (en) * 2015-07-23 2017-01-26 Finisar Corporation Component alignment

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6880441B1 (en) * 1996-06-06 2005-04-19 International Business Machines Corporation Precision punch and die design and construction
US5924623A (en) * 1997-06-30 1999-07-20 Honeywell Inc. Diffusion patterned C4 bump pads
JP4736355B2 (en) * 2004-06-08 2011-07-27 パナソニック株式会社 Component mounting method
DE102005041225B3 (en) * 2005-08-31 2007-04-26 Advanced Micro Devices, Inc., Sunnyvale Method for producing recessed, deformed drain / source regions in NMOS and PMOS transistors
US7627878B2 (en) * 2005-12-23 2009-12-01 Eloda Inc. Method and System for automated auditing of advertising
TWI300614B (en) * 2006-07-20 2008-09-01 Siliconware Precision Industries Co Ltd Flip-chip semiconductor package and chip carrier thereof
JP5501562B2 (en) * 2007-12-13 2014-05-21 ピーエスフォー ルクスコ エスエイアールエル Semiconductor device

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103247586A (en) * 2012-02-04 2013-08-14 隆达电子股份有限公司 Chip bonding structure and chip bonding method
CN105576110A (en) * 2014-10-31 2016-05-11 首尔伟傲世有限公司 High-efficiency light-emitting device
CN105576110B (en) * 2014-10-31 2018-04-13 首尔伟傲世有限公司 High-efficiency light-emitting device
CN104465598A (en) * 2014-12-19 2015-03-25 江苏长电科技股份有限公司 Metal lead frame high thermal conductivity flip chip packaging structure and technological method thereof
CN105935844A (en) * 2015-03-03 2016-09-14 发那科株式会社 Substrate manufactured from sheet metal and resin, motor provided with substrate, and soldering method therefor
CN105935844B (en) * 2015-03-03 2020-02-21 发那科株式会社 Substrate, motor having the same, and soldering method
CN109719381A (en) * 2019-02-21 2019-05-07 巴中市特兴智能科技有限公司 A kind of process of automatic welding bonding gold thread

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Publication number Publication date
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Open date: 20101027