CN101860362B - Dual-loop tuning method for low-vibration high frequency difference frequency and phase locking and electrical architecture thereof - Google Patents

Abstract

The invention discloses a double-loop adjustment method and its electrical structure for realizing low-jitter high-frequency difference frequency-locked phase-locked, including double-loops for tuning frequency and phase respectively, and the steps are: through an interpolator and a frequency and phase detector Determine the total instantaneous phase error between the reference clock and the feedback clock; use a low-pass filter to separate and extract the total instantaneous phase error into the instantaneous phase error of the two frequency components of the static/low-frequency frequency offset and the modulation frequency offset; use the static/low-frequency frequency offset Track the static/low-frequency frequency offset through the frequency locked loop; use the instantaneous phase error of the modulation frequency offset and the clock phase output from the frequency locked loop to track the phase between the reference clock and the feedback clock through the phase locked loop Is it aligned. The dual-loop frequency-locking and phase-locking architecture of the present invention does not need to increase the loop gain or bandwidth, and can effectively avoid the increase of high-frequency jitter.

Description

Low-jitter high-frequency difference frequency-locked phase-locked double-loop adjustment method and its electrical structure

technical field

The present invention relates to a clock and data recovery technology in the field of data communication, in particular to a double-loop frequency-locking and phase-locking method and its electrical structure for maintaining phase locking and slowing down large-scale jitter under fixed or serious modulation frequency misalignment in data communication. belongs to the field of electricity.

Background technique

In the design of modern high-speed data communication systems, clock recovery is widely used by embedding clock timing information in the original data stream. It offers higher data rates, better reliability, reduced noise generation, improved noise immunity and lower power costs. To further reduce electromagnetic interference (EMI), spread spectrum clocking (SSC) technology is used to distribute the energy into a limited frequency band. The clock frequency is adjusted to a lower frequency, such as 30kHz to 33kHz in the PCI-Express protocol, and the shape and amplitude of the envelope are defined at the same time, such as a sawtooth wave shape with an amplitude of 5000ppm.

Generally speaking, the clock frequency of the receiver is not equal to the clock frequency of the transmitter. On top of this static frequency misalignment, clock spread spectrum modulation further increases the frequency misalignment between the transmitter and receiver. For example, in the PCI-Express interface, the static frequency offset can reach 600ppm, while the dynamic maximum peak-to-peak modulation frequency offset can reach 10000ppm.

In a general approach, tracking such a large instantaneous frequency misalignment is achieved by increasing the gain or bandwidth of the clock recovery loop. But the higher clock recovery bandwidth leads to excessive loop gain, which increases the high frequency jitter of the recovered clock. Therefore, it is necessary to find a method to obtain greater frequency offset tracking capability without increasing the jitter of the recovered clock.

Contents of the invention

In view of the defects and urgent needs of the above-mentioned prior art, the purpose of the present invention is to propose a low-jitter high-frequency difference frequency-locked phase-locked dual-loop adjustment method and its electrical architecture to solve the problem of large tracking in the clock recovery loop even if the frequency is out of tune. problem.

First purpose of the present invention will be achieved through the following technical solutions:

The double-loop adjustment method of low-jitter, high-frequency difference, frequency-locked and phase-locked is characterized in that it includes double-loops for tuning frequency and phase respectively, and the steps are: Ⅰ. Setting the frequency-locked loop and the phase-locked loop; Ⅱ. Through interpolation The frequency detector and phase detector determine the total real-time phase error between the reference clock and the feedback clock; Ⅲ. Using a low-pass filter, the total real-time phase error is separated and extracted into two frequency components: static/low-frequency frequency offset and modulation frequency offset Ⅳ. Using the instant phase error of the static/low-frequency frequency offset to track and adjust the static/low-frequency frequency offset through the frequency-locked loop; V. Using the instant phase error of the modulation frequency offset and the output from the frequency-locked loop Clock phase, which tracks and adjusts phase alignment between the reference clock and the feedback clock through a phase-locked loop.

Further, the above-mentioned dual-loop adjustment method of low-jitter, high-frequency difference, frequency-locked and phase-locked, wherein the dual-loop frequency-locked and phase-locked method is run by a computer, the real-time phase frequency error and filtering of the two components of static/low-frequency frequency offset and modulation frequency offset Bandwidths are stored on computer-readable media for retrieval purposes.

Further, the above-mentioned dual-loop adjustment method for low-jitter, high-frequency difference, frequency-locked and phase-locked, wherein in step II, before or after separating and extracting the instant phase errors of the two frequency components, it also includes a process of performing loop filtering on the instant phase errors.

Second purpose of the present invention, the technical means that it is realized are:

Low-jitter, high-frequency difference, frequency-locked, phase-locked dual-loop adjustment electrical architecture, characterized in that: the dual-loop electrical architecture includes a frequency and phase detector, a loop filter, a low-pass filter, a local clock generator and a phase delay unit; the reference clock and the feedback clock are respectively input into the frequency detector and phase detector, and the output of the frequency detector and phase detector is connected to the loop filter and the low-pass filter in sequence, and the static/low-frequency component output of the low-pass filter is directly connected to To the local clock generator, and the modulation frequency component output terminal is connected to the phase delay unit through a phase subtractor, and fed back to the frequency discrimination phase detector; wherein the high frequency component output terminal of the low-pass filter is connected to the phase delay unit The unit and the frequency and phase detector form a phase-locked loop, and the static/low frequency component of the low-pass filter is output to the local clock generator, and is integrated with the phase delay unit, the frequency and phase detector and the loop filter And form a frequency locked loop.

Furthermore, in the aforementioned low-jitter, high-frequency difference frequency-locked phase-locked double-loop regulation electrical architecture, the frequency-phase detector includes a frequency-phase detector that generates a digital, analog or mixed type instant phase error signal.

Further, the aforementioned low-jitter high-frequency difference frequency-locked phase-locked double-loop adjustment electrical architecture, wherein the frequency locked loop is an analog form, including a local clock generator controlled by an analog voltage or current and a phase delay controlled by an analog voltage or current unit; or the frequency locked loop is in digital form, including a digital voltage or current controlled local clock generator and a digital voltage or current controlled phase delay unit.

Further, the aforementioned low-jitter high-frequency difference frequency-locked phase-locked double-loop adjustment electrical architecture, wherein the phase-locked loop is in analog form, including a phase delay unit controlled by analog voltage or current; or the phase-locked loop is in digital form , including digital voltage or current controlled phase delay units.

Further, the aforementioned low-jitter high-frequency difference frequency-locked phase-locked double-loop adjustment electrical architecture, wherein in the frequency-locked loop or phase-locked loop, the loop filter is set at the front end of the low-pass filter or at the end of the low-pass filter rear end.

Furthermore, the aforementioned low-jitter, high-frequency difference, frequency-locked, phase-locked dual-loop adjustment electrical architecture, wherein when the loop filter is set at the front end of the low-pass filter, the analog frequency and phase detector and the digital loop filter An N-bit analog-to-digital converter is provided between the devices, or an N-bit digital-to-analog converter is provided between the digital frequency and phase detector and the analog loop filter.

Furthermore, the aforementioned low-jitter, high-frequency difference, frequency-locked, phase-locked double-loop adjustment electrical architecture, wherein when the loop filter is set at the back end of the low-pass filter, the analog frequency and phase detector and the digital low-pass An N-bit analog-to-digital converter is provided between the filters, or an N-bit digital-to-analog converter is provided between the digital frequency and phase detector and the analog low-pass filter.

After the technical solution of the present invention is applied and implemented, the outstanding technical effects compared with the prior art are:

The frequency-locked-phase-locked double-loop adjustment method and its electrical structure obtain the phase error by filtering the output of the self-frequency and phase detector, and use the instantaneous phase error signal of the static/low-frequency frequency misalignment to drive the frequency-locked loop to track the static / Low frequency frequency mistuning. The dual-loop architecture does not need to increase loop gain or bandwidth, and can effectively avoid the increase of high-frequency jitter.

Description of drawings

Fig. 1 is the clock data recovery module based on interpolator in data communication;

Figure 2 is a case of instant frequency misalignment under static and frequency-hopping modulation;

FIG. 3 is a schematic diagram of a dual-loop architecture of a frequency-locked loop and a phase-locked loop according to the present invention.

Detailed ways

The specific implementation of the present invention will be described in further detail below in conjunction with the accompanying drawings of the embodiments, so that the details of the technical solution of the present invention can be displayed more comprehensively, and its essential features are easier to understand and grasp. It should be reminded that: the following narrations about the embodiments are not limiting, and those skilled in the art use other approaches to complete the same creations, although they are not specifically described, they are also included within the protection scope of the patent application for the present invention . The method of the present invention is I, determine the total real-time phase error between the reference clock and the feedback clock by an interpolator and a frequency detector; II, separate and extract the total real-time phase error into static/low-frequency frequency offset and The instant phase error of the two frequency components of the modulation frequency offset; Ⅲ. Using the instant phase error of the static/low frequency frequency offset to track the static/low frequency frequency offset through the frequency locked loop; Ⅳ. Using the instant phase error of the modulation frequency offset and the slave frequency Lock the phase of the clock output by the loop, and track whether the phases between the reference clock and the feedback clock are aligned through the phase locked loop.

In general, phase frequency detectors compare the phase and frequency between a local clock (the feedback clock) and a reference clock (also called a reference clock) signal, which may be embedded in the received data or clock middle. What Fig. 1 shows is the clock data recovery module based on the interpolator in the data communication. As shown in FIG. 1, a frequency and phase detector 100 is used to detect instantaneous phase and frequency error signals, and an interpolator 120 is used to delay or advance the local clock to align the recovered clock with the received data. The phase frequency detector 100 outputs an up or down pulse according to the instantaneous phase frequency difference, and then is filtered by the filter 110 . The filtered signal is used to control the frequency and phase of the clock signal sent by the interpolator 120 . The multiple clock phases used by the interpolator can be easily implemented by local clock generators.

As shown in Figure 2, an example of a frequency offset between a transmitter and a receiver is depicted. Usually there is a fixed frequency deviation fsos between the transmitter and the receiver, for example, fsos is equal to 600ppm in PCI-Express. Based on the static frequency difference, the frequencies of the transmitter and receiver are also modulated simultaneously. Modulation frequency is generally relatively low, in the PCI-Express protocol is 30kHz ~ 33kHz. The modulation signal is periodic, such as a triangle wave, etc. Modulation between transmitter and receiver can be asynchronous. Therefore, the maximum instantaneous frequency deviation fmos between the transmitter and receiver can be more than twice the modulation frequency, for example, it can reach 10000ppm in PCI-Express. The total instantaneous frequency deviation is the sum of the static frequency deviation and the modulation frequency deviation. To track such a large frequency deviation, the bandwidth of a typical second-order clock recovery loop needs to be increased. But this increases the jitter of the clock loop at the same time; at the same time, due to the delay of the frequency and phase detector, the loop bandwidth is also limited by the loop stability requirements, so increasing the bandwidth is not a good method here.

As shown in FIG. 3 , the dual-loop architecture of the frequency-locked loop and the phase-locked loop of the present invention is shown. The double-loop lock electrical architecture includes a frequency detector 300, a loop filter 310, a low-pass filter 320, a local clock generator 330, and a phase delay unit 340; the reference clock and the feedback clock are respectively input into the frequency detector, And the output of the frequency and phase detector is connected to the loop filter and the low-pass filter in sequence, the static/low-frequency component output of the low-pass filter is directly connected to the local clock generator, and the modulated frequency component output is passed through a phase The subtractor is connected to the phase delay unit and fed back to the frequency and phase detector; wherein the high-frequency component output of the low-pass filter forms a phase-locked loop with the phase delay unit and the frequency and phase detector, and the The static/low-frequency component of the low-pass filter is output to the local clock generator, and forms a frequency-locked loop together with the phase delay unit, the frequency detector and the loop filter. Wherein, the frequency and phase detector 300 generates an instant phase difference by comparing the timing between the reference clock and the feedback clock. The instantaneous phase error Errorlf caused by static or low frequency misalignment is extracted by the low pass filter 320 . The other high frequency instantaneous phase error component Errorhf can be obtained by subtracting Errorlf from the total phase error. Errorlf is used to advance or retard the clock of the local clock generator 330 so that the frequency of the local clock will track the frequency of the reference clock with a static or low frequency deviation of 0 ppm. Errorhf is used to delay or advance the phase of the clock coming out of the frequency locked loop through a delay unit 340 (such as an interpolator) to track the instantaneous phase alignment between the reference clock and the feedback clock. The frequency-locked loop is capable of fully tracking stationary or low-frequency frequency deviations. The bandwidth of the phase-locked loop does not need to be very high because the phase-locked loop does not need to track large static or low-frequency frequency deviations.

The preferred solution of the above embodiment also includes that the double-loop frequency locking and phase locking method is run by a computer, and the instant phase frequency error and filter bandwidth of the static/low frequency frequency offset and modulation frequency offset components are all stored in the computer-readable medium , for calls to lookup.

Before or after the separation and extraction of the instant phase errors of the two frequency components, a process of performing loop filtering on the instant phase errors is also included.

The frequency locked loop is in analog form, including an analog voltage or current controlled local clock generator and an analog voltage or current controlled phase delay unit; or the frequency locked loop is in digital form, including a digital voltage or current controlled local A clock generator and a phase delay unit controlled by a digital voltage or current; the phase-locked loop is in an analog form and includes a phase delay unit controlled by an analog voltage or current; or the phase-locked loop is in a digital form and includes a digital voltage or Current controlled phase delay unit.

Further, in the frequency locked loop or phase locked loop, the loop filter is arranged at the front end of the low pass filter or at the rear end of the low pass filter. When the loop filter is arranged at the front end of the low-pass filter, an N-bit analog-to-digital converter is arranged between the analog frequency and phase detector and the digital loop filter, or between the digital frequency and phase detector and the digital loop filter. An N-bit digital-to-analog converter is arranged between the analog loop filter; when the loop filter is arranged at the back end of the low-pass filter, an analog phase detector and a digital low-pass filter are provided An N-bit analog-to-digital converter, or an N-bit digital-to-analog converter is provided between the digital frequency and phase detector and the analog low-pass filter.

The present invention is suitable for clock recovery or phase-locked loops, and some other possible applications include filters with non-adjustable bandwidth under the condition of low-frequency frequency deviation. To sum up, the technical characteristics of the low-jitter, high-frequency difference, frequency-locked, phase-locked double-loop adjustment method and its electrical architecture of the present invention have been comprehensively and detailedly demonstrated, and the double-loop architecture does not need to increase loop gain or bandwidth, and can effectively avoid high-frequency jitter increase.

Claims (11)

1. the dicyclo control method of low jitter high frequency difference frequency frequency locking lock phase is characterized in that comprising the double loop that is used for difference tuned frequency and phase place, the steps include:

I, frequency locked loop and phased lock loop are set;

II, confirm the total instant phase error between reference clock and the feedback clock through interpolation device and phase frequency detector;

III, utilize low pass filter, total instant phase error separation and Extraction is become the lack of proper care instant phase error of two frequency components of static state/low frequency frequency misalignment and modulating frequency;

IV, utilize the instant phase error of static state/low frequency frequency misalignment, follow the tracks of and regulate static state/low frequency frequency misalignment through frequency locked loop;

Whether V, the instant phase error of utilizing modulating frequency to lack of proper care reach from the clock phase of frequency locked loop output, aim at through the phase place that phased lock loop is followed the tracks of and regulated between reference clock and the feedback clock.

2. the dicyclo control method of low jitter high frequency difference frequency frequency locking lock phase according to claim 1; It is characterized in that: said frequency locking and lock phase dicyclo control method are through computer run; The instant phase frequency error and the filtering bandwidth of static state/low frequency frequency misalignment and two components of modulating frequency imbalance all are stored in the computer-readable recording medium of computer, search for calling.

3. the dicyclo control method of low jitter high frequency difference frequency frequency locking lock phase according to claim 1; It is characterized in that: before or after the instant phase error of two frequency components of separation and Extraction, also comprise instant phase error is carried out the process that loop filters in the step III.

4. the electrical architecture that low jitter high frequency difference frequency frequency locking lock phase dicyclo is regulated is characterized in that: comprise phase frequency detector, loop filter, low pass filter, local clock generator and phase place delay unit; Reference clock and feedback clock are imported phase frequency detector respectively; And phase frequency detector is exported linkloop filter and low pass filter in order; The static state of said low pass filter/low frequency component output is connected directly to local clock generator; And the modulating frequency component output terminal subtracts through a phase place and adds device and be connected to the phase place delay unit, and feedback exports phase frequency detector to; Wherein loop filter and phase place subtract and add device, phase place delay unit and phase frequency detector constitutes phase-locked loop; And the static state/low frequency component of said low pass filter exports local clock generator to, and constitutes frequency locked loop in the lump with phase place delay unit, phase frequency detector and loop filter.

5. the electrical architecture that low jitter high frequency difference frequency frequency locking lock phase dicyclo according to claim 4 is regulated, it is characterized in that: said phase frequency detector comprises the frequency plot detector that produces numeral, simulation or the instant phase error signal of mixed type.

6. the electrical architecture that low jitter high frequency difference frequency frequency locking lock phase dicyclo according to claim 4 is regulated; It is characterized in that: said frequency locked loop is an analog form, comprises the phase place delay unit of local clock generator and the aanalogvoltage or the Current Control of aanalogvoltage or Current Control.

7. the electrical architecture that low jitter high frequency difference frequency frequency locking lock phase dicyclo according to claim 4 is regulated; It is characterized in that: said frequency locked loop is a digital form, comprises the phase place delay unit of local clock generator and the digital voltage or the Current Control of digital voltage or Current Control.

8. the electrical architecture that low jitter high frequency difference frequency frequency locking lock phase dicyclo according to claim 4 is regulated, it is characterized in that: said phase-locked loop is an analog form, comprises the phase place delay unit of aanalogvoltage or Current Control.

9. the electrical architecture that low jitter high frequency difference frequency frequency locking lock phase dicyclo according to claim 4 is regulated, it is characterized in that: said phase-locked loop is a digital form, comprises the phase place delay unit of digital voltage or Current Control.

10. the electrical architecture that low jitter high frequency difference frequency frequency locking lock phase dicyclo according to claim 4 is regulated, it is characterized in that: in the said frequency locked loop, loop filter is located at the front end of low pass filter.

11. the electrical architecture that low jitter high frequency difference frequency frequency locking lock phase dicyclo according to claim 10 is regulated; It is characterized in that: when loop filter is located at the low pass filter front end; Between the phase frequency detector of simulation and digital loop filter, be provided with the analog to digital converter of N bit, or between the loop filter of the phase frequency detector of numeral and simulation, be provided with the digital to analog converter of N bit.

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