CN101859839A - LED chip - Google Patents
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- CN101859839A CN101859839A CN200910131545A CN200910131545A CN101859839A CN 101859839 A CN101859839 A CN 101859839A CN 200910131545 A CN200910131545 A CN 200910131545A CN 200910131545 A CN200910131545 A CN 200910131545A CN 101859839 A CN101859839 A CN 101859839A
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- 239000004065 semiconductor Substances 0.000 claims abstract description 103
- 229910002601 GaN Inorganic materials 0.000 claims abstract description 89
- RNQKDQAVIXDKAG-UHFFFAOYSA-N aluminum gallium Chemical compound [Al].[Ga] RNQKDQAVIXDKAG-UHFFFAOYSA-N 0.000 claims abstract description 85
- 239000000758 substrate Substances 0.000 claims abstract description 20
- 229910002704 AlGaN Inorganic materials 0.000 claims description 82
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- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 12
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- 239000010703 silicon Substances 0.000 claims description 12
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- 239000011777 magnesium Substances 0.000 claims description 11
- 239000013078 crystal Substances 0.000 claims description 8
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- PMHQVHHXPFUNSP-UHFFFAOYSA-M copper(1+);methylsulfanylmethane;bromide Chemical compound Br[Cu].CSC PMHQVHHXPFUNSP-UHFFFAOYSA-M 0.000 claims description 7
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- 230000005641 tunneling Effects 0.000 abstract description 6
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- 229910005540 GaP Inorganic materials 0.000 description 2
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 description 2
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- NWAIGJYBQQYSPW-UHFFFAOYSA-N azanylidyneindigane Chemical compound [In]#N NWAIGJYBQQYSPW-UHFFFAOYSA-N 0.000 description 1
- 229910052729 chemical element Inorganic materials 0.000 description 1
- 238000005253 cladding Methods 0.000 description 1
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Abstract
Description
技术领域technical field
本发明涉及一种半导体元件,特别是涉及一种发光二极管(Light Emitting Diode,LED)芯片。The invention relates to a semiconductor element, in particular to a light emitting diode (Light Emitting Diode, LED) chip.
背景技术Background technique
发光二极管属于半导体元件,其发光芯片的材料一般可使用III-V族化学元素,如:磷化镓(GaP、)、砷化镓(GaAs)、氮化镓(GaN)等化合物半导体。利用对上述这些化合物半导体施加电流,透过电子空穴对的结合,可将电能转为光能,而以光波的形态释出,达到发光的效果。由于发光二极管的发光现象是属于冷性发光,而非通过加热发光,因此发光二极管的寿命可长达十万小时以上,且无须暖灯时间(idling time)。此外,发光二极管具有反应速度快(约为10-9秒)、体积小、用电省、污染低(不含水银)、可靠度高、适合量产等优点,因此其所能应用的领域十分广泛,如扫描仪的灯源、液晶屏幕的背光源、户外显示广告牌或是车用照明设备等。Light-emitting diodes are semiconductor components, and the material of the light-emitting chip can generally use III-V chemical elements, such as compound semiconductors such as gallium phosphide (GaP,), gallium arsenide (GaAs), and gallium nitride (GaN). By applying current to the above-mentioned compound semiconductors, through the combination of electron-hole pairs, electrical energy can be converted into light energy, and released in the form of light waves to achieve the effect of light emission. Since the light emitting phenomenon of the light emitting diode belongs to cold light, rather than through heating, the life of the light emitting diode can be as long as more than 100,000 hours, and there is no need for idling time. In addition, light-emitting diodes have the advantages of fast response (about 10 -9 seconds), small size, low power consumption, low pollution (mercury-free), high reliability, and suitable for mass production. Wide range, such as the light source of the scanner, the backlight of the LCD screen, the outdoor display billboard or the lighting equipment for the car, etc.
公知的发光二极管主要是由发光层、n型掺杂半导体层及p型掺杂半导体层所组成,其中n型掺杂半导体层及p型掺杂半导体层分别设置于发光层的两侧。一般而言,由于前述各层材质之间会有晶格不匹配(lattice mismatch)的现象,这会造成在外延(epitaxy)的过程中产生较大的应力(stress)而降低外延质量。此外,由于p型掺杂半导体层具有较高的电阻值,使得在p型掺杂半导体层与发光层的接合处会具有较大的压降,因此需要较高的操作电压才能操作发光二极管。The known light-emitting diode is mainly composed of a light-emitting layer, an n-type doped semiconductor layer and a p-type doped semiconductor layer, wherein the n-type doped semiconductor layer and the p-type doped semiconductor layer are respectively disposed on both sides of the light-emitting layer. Generally speaking, due to the phenomenon of lattice mismatch between the materials of the above-mentioned layers, this will cause relatively large stress during the epitaxy process and reduce the quality of the epitaxy. In addition, due to the high resistance of the p-type doped semiconductor layer, there will be a large voltage drop at the joint between the p-type doped semiconductor layer and the light-emitting layer, so a high operating voltage is required to operate the light-emitting diode.
发明内容Contents of the invention
本发明所要解决的技术问题之一是提供一种发光二极管芯片,其具有较低的操作电压及较平坦的表面,以解决上述情况。One of the technical problems to be solved by the present invention is to provide a light emitting diode chip, which has a lower operating voltage and a flatter surface, so as to solve the above problems.
本发明所要解决的技术问题之二是提供一种发光二极管芯片,其具有较低的漏电流。The second technical problem to be solved by the present invention is to provide a light emitting diode chip with lower leakage current.
为解决上述技术问题,本发明的一种发光二极管芯片,其包括基板、第一型掺杂半导体层、第二型掺杂半导体层、发光层、至少一掺杂铟掺质的氮化铝镓系材料层(In doped AlxGa1-xN based material layer,0≤x<1)、至少一穿隧接合层(tunneling junction layer)、第一电极及第二电极。第一型掺杂半导体层设置于基板上,而第二型掺杂半导体层设置于第一型掺杂半导体层上方,且发光层设置于第一型掺杂半导体层与第二型掺杂半导体层之间。掺杂铟掺质的氮化铝镓系材料层设置于发光层的至少其中一表面上,且穿隧接合层设置于掺杂铟掺质的氮化铝镓系材料层与第一型掺杂半导体层之间及/或掺杂铟掺质的氮化铝镓系材料层与第二型掺杂半导体层之间,其中掺杂铟掺质的氮化铝镓系材料层与穿隧接合层是位于发光层的同一侧。第一电极设置于第一型掺杂半导体层上,且第二电极设置于第二型掺杂半导体层上。In order to solve the above-mentioned technical problems, a light-emitting diode chip of the present invention includes a substrate, a first-type doped semiconductor layer, a second-type doped semiconductor layer, a light-emitting layer, and at least one aluminum gallium nitride doped with an indium dopant A material layer (Indoped Al x Ga 1-x N based material layer, 0≤x<1), at least one tunneling junction layer, a first electrode and a second electrode. The first type doped semiconductor layer is disposed on the substrate, the second type doped semiconductor layer is disposed above the first type doped semiconductor layer, and the light emitting layer is disposed between the first type doped semiconductor layer and the second type doped semiconductor layer between layers. The aluminum gallium nitride-based material layer doped with indium dopant is arranged on at least one surface of the light-emitting layer, and the tunnel junction layer is arranged on the aluminum gallium nitride-based material layer doped with indium dopant and the first type doped Between the semiconductor layers and/or between the indium-doped aluminum gallium nitride-based material layer and the second-type doped semiconductor layer, wherein the indium-doped aluminum gallium nitride-based material layer and the tunnel junction layer are located on the same side of the luminescent layer. The first electrode is disposed on the first-type doped semiconductor layer, and the second electrode is disposed on the second-type doped semiconductor layer.
此外,本发明另提出一种发光二极管芯片,其包括基板、第一型掺杂半导体层、第二型掺杂半导体层、发光层、至少一未掺杂的氮化铝镓系材料层(undoped AlxGa1-xN based material layer,0≤x<1)、至少一穿隧接合层、第一电极及第二电极。第一型掺杂半导体层设置于基板上,而第二型掺杂半导体层设置于第一型掺杂半导体层上方,且发光层设置于第一型掺杂半导体层与第二型掺杂半导体层之间。未掺杂的氮化铝镓系材料层设置于发光层的至少其中一表面上,且穿隧接合层设置于未掺杂的氮化铝镓系材料层与第一型掺杂半导体层之间及/或未掺杂的氮化铝镓系材料层与第二型掺杂半导体层之间,其中未掺杂的氮化铝镓系材料层与穿隧接合层是位于发光层的同一侧。第一电极设置于第一型掺杂半导体层上,且第二电极设置于第二型掺杂半导体层上。In addition, the present invention further proposes a light-emitting diode chip, which includes a substrate, a first-type doped semiconductor layer, a second-type doped semiconductor layer, a light-emitting layer, and at least one undoped aluminum gallium nitride-based material layer (undoped AlxGa1 -xN based material layer, 0≤x<1), at least one tunnel junction layer, a first electrode and a second electrode. The first type doped semiconductor layer is disposed on the substrate, the second type doped semiconductor layer is disposed above the first type doped semiconductor layer, and the light emitting layer is disposed between the first type doped semiconductor layer and the second type doped semiconductor layer between layers. The undoped AlGaN-based material layer is disposed on at least one surface of the light-emitting layer, and the tunnel junction layer is disposed between the undoped AlGaN-based material layer and the first-type doped semiconductor layer And/or between the undoped AlGaN-based material layer and the second-type doped semiconductor layer, wherein the undoped AlGaN-based material layer and the tunnel junction layer are located on the same side of the light-emitting layer. The first electrode is disposed on the first-type doped semiconductor layer, and the second electrode is disposed on the second-type doped semiconductor layer.
所述穿隧接合层的能隙宽度可以大于发光层的能隙宽度。An energy gap width of the tunnel junction layer may be greater than an energy gap width of the light emitting layer.
所述穿隧接合层包括第一型氮化铝镓系材料层及第二型氮化铝镓系材料层,其中第二型氮化铝镓系材料层设置于第一型氮化铝镓系材料层的其中一表面上。The tunnel bonding layer includes a first-type aluminum gallium nitride-based material layer and a second-type aluminum gallium nitride-based material layer, wherein the second-type aluminum gallium nitride-based material layer is arranged on the first-type aluminum gallium nitride-based material layer on one surface of the material layer.
所述第一型氮化铝镓系材料层可以具有硅掺质、铟掺质或其组合,且第二型氮化铝镓系材料层可以具有镁掺质、铟掺质或其组合。The first-type AlGaN-based material layer may have silicon dopant, indium dopant or a combination thereof, and the second-type AlGaN-based material layer may have magnesium dopant, indium dopant or a combination thereof.
所述掺杂铟掺质的氮化铝镓系材料层/未掺杂的氮化铝镓系材料层设置于发光层的上表面上,且第二型氮化铝镓系材料层设置于掺杂铟掺质的氮化铝镓系材料层/未掺杂的氮化铝镓系材料层与第一型氮化铝镓系材料层之间。The aluminum gallium nitride-based material layer/undoped aluminum gallium nitride-based material layer doped with indium dopant is arranged on the upper surface of the light-emitting layer, and the second-type aluminum gallium nitride-based material layer is arranged on the doped aluminum gallium nitride-based material layer. Between the indium-doped AlGaN-based material layer/undoped AlGaN-based material layer and the first-type AlGaN-based material layer.
所述掺杂铟掺质的氮化铝镓系材料层/未掺杂的氮化铝镓系材料层设置于发光层的下表面上,且第一型氮化铝镓系材料层设置于掺杂铟掺质的氮化铝镓系材料层/未掺杂的氮化铝镓系材料层与第二型氮化铝镓系材料层之间。The aluminum gallium nitride-based material layer/undoped aluminum gallium nitride-based material layer doped with indium dopant is arranged on the lower surface of the light-emitting layer, and the first-type aluminum gallium nitride-based material layer is arranged on the doped aluminum gallium nitride-based material layer. Between the indium-doped AlGaN-based material layer/undoped AlGaN-based material layer and the second-type AlGaN-based material layer.
另外,所述第一型氮化铝镓系材料层也可以具有镁掺质、铟掺质或其组合,且第二型氮化铝镓系材料层可以具有硅掺质、铟掺质或其组合。所述掺杂铟掺质的氮化铝镓系材料层/未掺杂的氮化铝镓系材料层设置于发光层的上表面上,且第二型氮化铝镓系材料层设置于掺杂铟掺质的氮化铝镓系材料层/未掺杂的氮化铝镓系材料层与第一型氮化铝镓系材料层之间。所述掺杂铟掺质的氮化铝镓系材料层/未掺杂的氮化铝镓系材料层设置于发光层的下表面上,而第一型氮化铝镓系材料层设置于掺杂铟掺质的氮化铝镓系材料层/未掺杂的氮化铝镓系材料层与第二型氮化铝镓系材料层之间。In addition, the first-type aluminum gallium nitride-based material layer may also have magnesium dopant, indium dopant, or a combination thereof, and the second-type aluminum gallium nitride-based material layer may have silicon dopant, indium dopant, or a combination thereof. combination. The aluminum gallium nitride-based material layer/undoped aluminum gallium nitride-based material layer doped with indium dopant is arranged on the upper surface of the light-emitting layer, and the second-type aluminum gallium nitride-based material layer is arranged on the doped aluminum gallium nitride-based material layer. Between the indium-doped AlGaN-based material layer/undoped AlGaN-based material layer and the first-type AlGaN-based material layer. The aluminum gallium nitride-based material layer/undoped aluminum gallium nitride-based material layer doped with indium dopant is arranged on the lower surface of the light-emitting layer, and the first-type aluminum gallium nitride-based material layer is arranged on the doped Between the indium-doped AlGaN-based material layer/undoped AlGaN-based material layer and the second-type AlGaN-based material layer.
所述第一型掺杂半导体层包括缓冲层(buffer layer)、结晶层(nucleation layer)及第一型接触层。缓冲层设置于基板上,而结晶层设置于缓冲层上,且第一型接触层设置于结晶层上。The first-type doped semiconductor layer includes a buffer layer, a nucleation layer and a first-type contact layer. The buffer layer is disposed on the substrate, the crystal layer is disposed on the buffer layer, and the first type contact layer is disposed on the crystal layer.
所述第二型掺杂半导体层包括第二型接触层。The second-type doped semiconductor layer includes a second-type contact layer.
综合上述,由于穿隧接合层可以有效降低第一/第二型掺杂半导体层与发光层之间的压降,因此本发明的发光二极管具有较低的操作电压。此外,掺杂铟掺质的氮化铝镓系材料层可使发光二极管芯片具有较平坦的表面,而未掺杂的氮化铝镓系材料层可使发光二极管芯片具有较低的漏电流。因此,上述的优良特性均有效提高本发明的发光二极管芯片的质量。In summary, since the tunnel junction layer can effectively reduce the voltage drop between the first/second type doped semiconductor layer and the light-emitting layer, the light-emitting diode of the present invention has a lower operating voltage. In addition, the AlGaN-based material layer doped with indium dopant can make the light-emitting diode chip have a flatter surface, while the undoped AlGaN-based material layer can make the light-emitting diode chip have a lower leakage current. Therefore, the above-mentioned excellent characteristics can effectively improve the quality of the LED chip of the present invention.
附图说明Description of drawings
下面结合附图与具体实施方式对本发明作进一步详细的说明:Below in conjunction with accompanying drawing and specific embodiment the present invention is described in further detail:
图1是依照本发明的实施例1的发光二极管芯片的剖面示意图;1 is a schematic cross-sectional view of a light emitting diode chip according to Embodiment 1 of the present invention;
图2是依照本发明的实施例2的发光二极管芯片的剖面示意图;2 is a schematic cross-sectional view of a light emitting diode chip according to Embodiment 2 of the present invention;
图3是依照本发明的实施例3的发光二极管芯片的剖面示意图;3 is a schematic cross-sectional view of a light emitting diode chip according to Embodiment 3 of the present invention;
图4是依照本发明的实施例4的发光二极管芯片的剖面示意图。FIG. 4 is a schematic cross-sectional view of an LED chip according to Embodiment 4 of the present invention.
图中附图标记说明:Explanation of the reference signs in the figure:
100、200、300、400为发光二极管芯片, 110为基板,100, 200, 300, 400 are LED chips, 110 is the substrate,
120为第一型掺杂半导体层,122为缓冲层, 124为结晶层,120 is a first-type doped semiconductor layer, 122 is a buffer layer, 124 is a crystal layer,
126为第一型接触层, 130为第二型掺杂半导体层,126 is the first type contact layer, 130 is the second type doped semiconductor layer,
132为第二型接触层, 140为发光层,132 is the second type contact layer, 140 is the light emitting layer,
150、250为掺杂铟掺质的氮化铝镓系材料层,150 and 250 are aluminum gallium nitride-based material layers doped with indium dopant,
160、260、360、460为穿隧接合层,160, 260, 360, 460 are tunnel bonding layers,
162、262、362、462为第一型氮化铝镓系材料层,162, 262, 362, 462 are first-type aluminum gallium nitride-based material layers,
164、264、364、464为第二型氮化铝镓系材料层,164, 264, 364, 464 are second-type aluminum gallium nitride-based material layers,
170为第一电极, 180为第二电极。170 is the first electrode, 180 is the second electrode.
具体实施方式Detailed ways
实施例1Example 1
图1为依照本发明的实施例1的发光二极管芯片的剖面示意图。参照图1,本发明的发光二极管芯片100包括基板110、第一型掺杂半导体层120、第二型掺杂半导体层130、发光层140、掺杂铟掺质的氮化铝镓系材料层(In doped AlxGa1-xN based material layer,0≤x<1)150、穿隧接合层(tunneling junction layer)160、第一电极170及第二电极180。第一型掺杂半导体层120设置于基板110上,而第二型掺杂半导体层130设置于第一型掺杂半导体层120上方,且发光层140设置于第一型掺杂半导体层120与第二型掺杂半导体层130之间。此外,第一电极170设置于第一型掺杂半导体层120上,且第二电极180设置于第二型掺杂半导体层130上。当由第一电极170及第二电极180通以顺向电流时,电子及空穴会分别经由第一型掺杂半导体层120及第二型掺杂半导体层130传递至发光层140中结合,并以光波的形态释放能量而达到发光的效果。FIG. 1 is a schematic cross-sectional view of an LED chip according to Embodiment 1 of the present invention. Referring to FIG. 1 , the
在本实施例中,掺杂铟掺质的氮化铝镓系材料层150设置于发光层140的上表面上。由于本发明设置掺杂铟掺质的氮化铝镓系材料层150以减缓第二型掺杂半导体层130与发光层140材质之间晶格不匹配的现象,可降低发光二极管芯片100在外延时产生的应力。同时,由于铟掺质具有较佳的表面迁移能(surface migration capability),因此,发光二极管芯片100可形成较平坦的表面。详细而言,由于铟原子的原子半径大于镓原子的原子半径,故铟掺质可以降低氮元素的空乏密度(vacancy density),以使在外延的过程中提高V/III的比例,并改善发光二极管芯片100中的差排缺陷。In this embodiment, the AlGaN-based material layer 150 doped with indium dopant is disposed on the upper surface of the
再参照图1,在本实施例中,穿隧接合层160设置于掺杂铟掺质的氮化铝镓系材料层150与第二型掺杂半导体层130之间,如此可降低第二型掺杂半导体层130与发光层140之间的压降,因而本发明的发光二极管芯片100具有较低的操作电压。此外,当穿隧接合层160的能隙宽度大于发光层140的能隙宽度时,发光二极管芯片100具有较佳的发光特性。Referring to FIG. 1 again, in this embodiment, the
承上所述,穿隧接合层160包括第一型氮化铝镓系(AlxGa1-xN,0≤x<1)材料层162及第二型氮化铝镓系(AlxGa1-xN,0≤x<1)材料层164。在本实施例中,第二型氮化铝镓系材料层164设置于掺杂铟掺质的氮化铝镓系材料层150与第一型氮化铝镓系材料层162之间。此外,第一型氮化铝镓系材料层162可为n型氮化铝镓系材料层,且第二型氮化铝镓系材料层164可为p型氮化铝镓系材料层(如此,第一型掺杂半导体层120及第二型掺杂半导体层130则分别为n型氮化铝镓系材料层及p型氮化铝镓系材料层)。As mentioned above, the
为进一步降低发光二极管芯片100的操作电压,本发明可掺杂硅掺质、铟掺质或其组合于第一型氮化铝镓系材料层162中,亦可掺杂镁掺质、铟掺质或其组合于第二型氮化铝镓系材料层164中。值得注意的是,特别是当同时掺杂硅掺质及铟掺质于第一型氮化铝镓系材料层162中时,且同时掺杂镁掺质及铟掺质于第二型氮化铝镓系材料层164中时,发光二极管芯片100可具有更低的操作电压。In order to further reduce the operating voltage of the light-emitting
此外,上述中的掺杂铟掺质的氮化铝镓系材料层150、第一型氮化铝镓系材料层162及第二型氮化铝镓系材料层164例如是以金属有机化学气相沉积法(Metal Organic Chemical Vapor Deposition,MOCVD)形成,而其较佳的厚度是介于0.5nm~20nm之间,且其较佳的成长温度是介于800℃~1200℃之间。In addition, the AlGaN-based material layer 150 doped with indium dopant, the first-type AlGaN-based
以下将分段叙述发光二极管芯片100的基板及各薄膜层的材质及结构。The materials and structures of the substrate and each thin film layer of the
基板110的材质包括氧化铝单晶(Sapphire)、碳化硅(6H-SiC或4H-SiC)、硅(Si)、氧化锌(ZnO)、砷化镓(GaAs)、尖晶石(MgAl2O4)或其它晶格常数接近于氮化物半导体的单晶氧化物,且基板110的材质组成形态例如为C-Plane、E-Plane或A-Plane。The material of the
再参照图1,第一型掺杂半导体层120包括缓冲层122、结晶层124及第一型接触层126。缓冲层122设置于基板110上,且其例如是由氮化铝镓铟(AlaGabIn1-a-bN,0≤a<1,0≤b<1,a+b≤1)所构成。结晶层124设置于缓冲层122上,其主要功用在于使之后的外延可以更加快速,且外延的晶格排序较为整齐,且第一型接触层126设置于结晶层124上。Referring again to FIG. 1 , the first-type doped
承上所述,第二型掺杂半导体层130包括第二型接触层132。在本实施例中,第一型接触层126为n型接触层,而第二型接触层132为p型接触层,且前述的接触层例如由氮化铝镓系材质所构成,并通过掺杂离子杂质种类及浓度不同而调整其特性。此外,发光层140例如是由氮化铟镓(InaGa1-aN,0≤a<1)所构成的多重量子井结构,并通过不同比例的铟镓元素,可使其发出不同波长的光线。As mentioned above, the second-type doped
附带一提的是,为增进发光二极管芯片100的电特性,第一型掺杂半导体层120还可以包括第一型被覆层(图中未表示)设置于第一型接触层126上。第二型掺杂半导体层130还可以包括第二型被覆层(图中未表示)设置于第二型接触层132与发光层140之间。此外,本实施例的穿隧接合层160同时具有被覆层的特性,如此发光二极管芯片100不需设置第二型被覆层即可具有较佳的电特性。Incidentally, to improve the electrical properties of the
值得注意的是,本发明可用未掺杂的氮化铝镓系材料层(undoped,AlxGa1-xN based material layer,0≤x<1)以取代掺杂铟掺质的氮化铝镓系材料层150。如此,则本发明可以大幅降低发光二极管芯片100的漏电流现象,以使其具有较佳的电特性。附带一提的是,未掺杂的氮化铝镓系材料层例如是以金属有机化学气相沉积法形成,而其较佳的厚度是介于0.5nm~20nm之间,且其较佳的成长温度是介于800℃~1200℃之间。It is worth noting that the present invention can use an undoped aluminum gallium nitride based material layer (undoped, Al x Ga 1-x N based material layer, 0≤x<1) to replace the aluminum nitride doped with indium dopant Gallium-based material layer 150 . In this way, the present invention can greatly reduce the leakage current phenomenon of the
此外,本发明并不限定掺杂铟掺质的氮化铝镓系材料层150与穿隧接合层160只能位于第二型掺杂半导体层130及发光层140之间。以下,将列举其它实施例并配合附图说明本发明其它结构的发光二极管。In addition, the present invention does not limit that the AlGaN-based material layer 150 doped with indium dopant and the
实施例2Example 2
图2为依照本发明的实施例2的发光二极管芯片的剖面示意图。参照图2,实施例2的发光二极管芯片200与实施例1的发光二极管芯片100(如图1所示)相似,其差别在于掺杂铟掺质的氮化铝镓系材料层250与穿隧接合层260的配设位置不同。在本实施例中,掺杂铟掺质的氮化铝镓系材料层250设置于发光层140的下表面上,且穿隧接合层260设置于掺杂铟掺质的氮化铝镓系材料层250与第一型掺杂半导体层120之间。此外,穿隧接合层260包括第一型氮化铝镓系材料层262及第二型氮化铝镓系材料层264,其中第一型氮化铝镓系材料层262设置于掺杂铟掺质的氮化铝镓系材料层250与第二型氮化铝镓系材料层264之间。FIG. 2 is a schematic cross-sectional view of an LED chip according to Embodiment 2 of the present invention. Referring to FIG. 2 , the light emitting
类似前述理由,掺杂铟掺质的氮化铝镓系材料层250可减缓第一型掺杂半导体层120与发光层140材质之间晶格不匹配的现象,以使发光二极管芯片200形成较平坦的表面。此外,穿隧接合层260可降低第一型掺杂半导体层120与发光层140之间的压降,以使发光二极管芯片200具有较低的操作电压。当然,亦可用未掺杂的氮化铝镓系材料层取代掺杂铟掺质的氮化铝镓系材料层250,以使发光二极管芯片200具有较低的漏电流。附带一提的是,本实施例的穿隧接合层260亦可同时作为被覆层而取代前述的第一型被覆层以增进发光二极管芯片200的电特性。Similar to the aforementioned reasons, the aluminum gallium nitride-based
值得注意的是,本发明并不限定掺杂铟掺质的氮化铝镓系材料层及穿隧接合层的数量。举例而言,本发明可以结合实施例1及实施例2的发光二极管芯片100、200,以使掺杂铟掺质的氮化铝镓系材料层与穿隧接合层可位于发光层与第一掺杂半导体层之间,以及发光层与第二掺杂半导体层之间。所属技术领域的技术人员可以自行推得上述的情形,此处不再附图表示。It should be noted that the present invention does not limit the quantity of the AlGaN material layer and the tunnel junction layer doped with indium dopant. For example, the present invention can be combined with the light-emitting
此外,本发明亦不限定第一型氮化铝镓系材料层为n型氮化铝镓系材料层,且第二型氮化铝镓系材料层为p型氮化铝镓系材料层。以下,将列举其它实施例并配合附图说明本发明其它形态的发光二极管。In addition, the present invention does not limit the first-type AlGaN-based material layer to be an n-type AlGaN-based material layer, and the second-type AlGaN-based material layer to be a p-type AlGaN-based material layer. Hereinafter, other embodiments and accompanying drawings will be used to illustrate other forms of light emitting diodes of the present invention.
实施例3、实施例4Embodiment 3, Embodiment 4
图3为依照本发明的实施例3的发光二极管芯片的剖面示意图,图4为依照本发明的实施例4的发光二极管芯片的剖面示意图。参照图3,实施例3的发光二极管芯片300与实施例1的发光二极管芯片100(如图1所示)相似,其差别在于穿隧接合层360的第一型氮化铝镓系材料层362为p型氮化铝镓系材料层,而第二型氮化铝镓系材料层364为n型氮化铝镓系材料层。参照图4,实施例4的发光二极管芯片400与实施例2的发光二极管芯片200(如图2所示)相似,其差别在于穿隆接合层460的第一型氮化铝镓系材料层462为p型氮化铝镓系材料层,而第二型氮化铝镓系材料层464为n型氮化铝镓系材料层。3 is a schematic cross-sectional view of a light emitting diode chip according to embodiment 3 of the present invention, and FIG. 4 is a schematic cross-sectional view of a light emitting diode chip according to embodiment 4 of the present invention. Referring to FIG. 3 , the LED chip 300 of Embodiment 3 is similar to the
承上所述,同时参照图3及图4,在这两实施例中,第一型氮化铝镓系材料层可以具有镁掺质、铟掺质或其组合,且第二型氮化铝镓系材料层364、464可以具有硅掺质、铟掺质或其组合。值得注意的是,特别是当同时掺杂镁掺质及铟掺质于第一型氮化铝镓系材料层362、462中时,且同时掺杂硅掺质及铟掺质于第二型氮化铝镓系材料层364、464中时,发光二极管芯片300、400可具有更低的操作电压。当然,在此两实施例的形态架构中,则第一型掺杂半导体层120及第二型掺杂半导体层130则需分别对应为p型氮化铝镓系材料层及n型氮化铝镓系材料层。Based on the above, referring to FIG. 3 and FIG. 4 at the same time, in these two embodiments, the first-type aluminum gallium nitride-based material layer may have magnesium dopant, indium dopant or a combination thereof, and the second-type aluminum nitride The gallium-based material layers 364, 464 may have silicon dopants, indium dopants, or a combination thereof. It is worth noting that, especially when magnesium dopant and indium dopant are simultaneously doped in the first type AlGaN-based material layers 362, 462, and silicon dopant and indium dopant are simultaneously doped in the second type When the AlGaN-based material layer 364 , 464 is used, the
附带一提的是,本发明可用未掺杂的氮化铝镓系材料层取代掺杂锢掺质的氮化铝镓系材料层150、250(如图3、图4所示),以使发光二极管芯片200具有较低的漏电流。此外,本发明可以结合实施例3及实施例4的发光二极管芯片300、400,以使掺杂铟掺质的氮化铝镓系材料层与穿隧接合层可位于发光层与第一掺杂半导体层之间,以及发光层与第二掺杂半导体层之间。所属技术领域的技术人员可以自行推得上述的情形,此处不再附图表示。Incidentally, in the present invention, the AlGaN-based material layers 150 and 250 (as shown in FIG. 3 and FIG. 4 ) doped with impurity dopant can be replaced by an undoped AlGaN-based material layer, so that The
在上述各实施例的发光二极管芯片100、200、300、400中(如图1、图2、图3、图4所示),掺杂铟掺质的氮化铝镓系材料层(或未掺杂的氮化铝镓系材料层)与穿隧接合层是位于发光层与第一掺杂半导体层之间,或是位于发光层与第二掺杂半导体层之间。然而,本发明并不限定掺杂铟掺质的氮化铝镓系材料层(或未掺杂的氮化铝镓系材料层)与穿隧接合层只能位于前述的两个位置。举例而言,其亦可以位于第二电极与第二型接触层之间,或是位于第二型接触层与第二型被覆层之间,或是位于第一型被覆层与第一型接触层之间等位置以使发光二极管芯片具有较佳的质量。In the light-emitting
综上所述,本发明的发光二极管芯片至少具有下列优点:In summary, the LED chip of the present invention has at least the following advantages:
一、由于设置掺杂铟掺质的氮化铝镓系材料层,可使发光二极管芯片具有较平坦的表面,并改善发光二极管芯片于外延时产生的差排缺陷;1. Since the aluminum gallium nitride-based material layer doped with indium dopant is provided, the surface of the light-emitting diode chip can be relatively flat, and the dislocation defects generated during the epitaxy of the light-emitting diode chip can be improved;
二、由于设置未掺杂的氮化铝镓系材料层,可降低发光二极管芯片的漏电流,以提高其电特性;2. Since the undoped aluminum gallium nitride material layer is set, the leakage current of the light-emitting diode chip can be reduced to improve its electrical characteristics;
三、由于穿隧接合层可有效降低第一/第二型掺杂半导体层与发光层之间的压降,因此发光二极管芯片具有较低的操作电压;3. Since the tunnel junction layer can effectively reduce the voltage drop between the first/second type doped semiconductor layer and the light-emitting layer, the light-emitting diode chip has a lower operating voltage;
四、由于第一型氮化铝镓系材料层同时掺杂镁掺质及铟掺质,且第二型氮化铝镓系材料层同时掺杂硅掺质及铟掺质,因此可进一步降低发光二极管芯片的操作电压;4. Since the first-type aluminum gallium nitride-based material layer is doped with magnesium dopant and indium dopant at the same time, and the second-type aluminum gallium nitride-based material layer is doped with silicon dopant and indium dopant at the same time, it can further reduce the The operating voltage of the LED chip;
五、穿隧接合层同时具有被覆层的特性,如此发光二极管芯片不需设置被覆层即可具有较佳的电特性。5. The tunnel bonding layer also has the characteristics of the covering layer, so that the light-emitting diode chip can have better electrical characteristics without providing a covering layer.
以上通过实施例,对本发明进行了详细的说明,但这些并非构成对本发明的限制。在不脱离本发明原理的情况下,本领域的技术人员还可做出许多变形和改进,这些也应视为本发明的保护范围。The present invention has been described in detail through the above examples, but these are not intended to limit the present invention. Without departing from the principle of the present invention, those skilled in the art can also make many modifications and improvements, which should also be regarded as the protection scope of the present invention.
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