CN101834158B - Fabrication Process of Silicon-on-Insulator Deep Silicon Trench Isolation Structure - Google Patents
Fabrication Process of Silicon-on-Insulator Deep Silicon Trench Isolation Structure Download PDFInfo
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- CN101834158B CN101834158B CN2010101465084A CN201010146508A CN101834158B CN 101834158 B CN101834158 B CN 101834158B CN 2010101465084 A CN2010101465084 A CN 2010101465084A CN 201010146508 A CN201010146508 A CN 201010146508A CN 101834158 B CN101834158 B CN 101834158B
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Abstract
The invention provides a preparation process of an upper silicon and deep silicon trench isolation structure for an insulator, comprising the following steps: a. setting an embedded oxidation layer on a semiconductor substrate, setting N-type top monocrystalline silicon on the embedded oxidation layer, generating a surface oxidation layer on the N-type top monocrystalline silicon, coating photoresist on the surface of the surface oxidation layer, and etching a window with the same size as a deep silicon trench on the photoresist; b. corroding the naked surface oxidation layer and exposing the N-type top monocrystalline silicon to be etched; c. taking the surface oxidation layer as a masking layer for etching the N-type top monocrystalline silicon, and etching the deep silicon trench with the aspect ratio of 7:1.2-7:3 by a anisotropic plasma dry etching process; and completely corroding the surface oxidation layer and corroding the embedded oxidation layer so that the moving depth of the bottom of the deep silicon trench is 15%-25% of the thickness of the embedded oxidation layer; d. growing an isolation oxidation layer on the side wall of the deep silicon trench by a wet oxidation method; and e. filling up the deep silicon trench by undoped polysilicon.
Description
Technical field
The present invention relates to the power semiconductor integrated circuit and make the field, the fabricating technology of the dark full dielectric isolation structure of silicon groove on specifically a kind of silicon-on-insulator (SOI) material.
Background technology
In the high-low pressure power integrated circuit, one of difficult problem that need overcome is exactly how the high-low pressure part isolates fully.Because hi-lo circuit is made on the same substrate, device injects the charge carrier of substrate can be collected by contiguous large area power device, may cause that like this opening by mistake of power device open, and Here it is, and the restriction hi-lo circuit is difficult to an integrated principal element.The Perfected process of device isolation should be that each device is all wrapped in the insulating material fully.And increasingly mature along with SOI (silicon-on-insulator) bonding techniques, silicon-on-insulator deep trench isolation mechanism is applied in the power integrated circuit design by increasing.
In actual manufacture process; Because growth sidewall isolating oxide layer reacting gas flows in the silicon groove from top to bottom; And when oxidizing temperature is spent less than 1200, have silicon convex-concave angle oxide layer attenuation effect, finally cause silicon trench bottom oxide layer relatively weaker, dielectric breakdown takes place easily too early.
In relevant technology, the someone proposes after dark silicon groove etching is accomplished, and is infused in through energetic ion and forms one deck N type doped region on the silicon groove sidewall to quicken the isolation oxidation layer growth; But because there is one about 7 ° injection angle of inclination in the energetic ion injection technology; And owing to be the dark silicon groove of silicon-on-insulator structure, the aspect ratio of dark silicon groove is general bigger, and ion injects and is difficult to be injected into trench bottom; Cause and inject inequality, have equally in dark silicon trench bottom oxide layer weak spot.
In addition; Someone proposes the amorphous silicon of after deep etching is accomplished deposit or selective epitaxy one deck doped N-type impurity; This layer amorphous silicon part and the dark silicon groove of silicon-on-insulator top silicon surface sidewall be the zone of crystallization formation one deck N+ type again, and a part of in addition amorphous silicon is used to form the silicon dioxide of isolating usefulness.But amorphous silicon still can produce lattice defect in recrystallization process, and silicon layer and isolating oxide layer transition region are not obvious, can influence the electric isolation characteristic of dark silicon groove.
Summary of the invention
The object of the invention provides a kind of preparation technology of upper silicon and deep silicon trench isolation structure for insulator, has weakened the electric leakage weak spot phenomenon that the isolating oxide layer uneven thickness causes on the dark silicon groove sidewall greatly, simultaneously through the time prolongation that the dielectric breakdown time also obtains.
The present invention adopts following technical scheme:
A kind of preparation technology of upper silicon and deep silicon trench isolation structure for insulator; Comprise: a, on Semiconductor substrate, be provided with and bury oxide layer; Be provided with N type top monocrystalline silicon on the oxide layer burying; On N type top monocrystalline silicon, generate surface oxide layer,, on photoresist, etch the window of dark silicon groove size and expose surface oxide layer at surface oxide layer surface-coated photoresist; The surface oxide layer that b, corrosion expose also exposes the N type top monocrystalline silicon of wanting etching; It is characterized in that,
C, utilize the masking layer of surface oxide layer, adopt the anisotropic plasma dry etch process, etch aspect ratio and be 7: 1.2 to 7: 3 dark silicon groove as etching N type top monocrystalline silicon; And then erode surface oxide layer fully, oxide layer is buried in corrosion simultaneously, and making the degree of depth that moves down of the bottom position of dark silicon groove is to bury the 15%-25% of thickness of oxide layer;
D, adopt the wet oxygen method isolating oxide layer of on the sidewall of dark silicon groove, growing;
E, the undoped polysilicon of employing are filled dark silicon groove.
Compared with prior art, the present invention has following advantage:
Among the upper silicon and deep silicon trench isolation structure for insulator preparation technology among the present invention, bury the position that oxide layer moves down the isolating oxide layer weak spot, increased the isolation oxidation layer thickness at weak spot place simultaneously through the corrosion partial SOI.
(1) through eroding the oxide layer of burying that thickness is 15%-25%, the degree of depth of promptly having deepened the silicon groove makes dark silicon trench bottom isolating oxide layer weak spot move down 15%-25% in original weak spot position, shown in yellow reference line among Fig. 4; And dark silicon trench bottom moves down and has increased bottom corners place silicon face and oxidation reaction gas contact area; Thereby increased the isolation oxidation layer thickness (seeing black circles mark place among Fig. 4) at original weak spot place; And then increased the dielectric breakdown voltage between the active area of dark silicon groove both sides and reduced the horizontal leakage current between deep trench isolation district and active area, as shown in Figure 5.For example, thinnest part isolation oxidation layer thickness increases approximately 34% in cross-section structure comparison diagram shown in Figure 4, and in Fig. 5, can obviously draw the dark silicon groove dielectric breakdown voltage that the technology that adopts among the present invention makes and improves about 50V;
(2) part is buried oxide layer technology and removal surface oxidation layer process carries out simultaneously owing to eroding, and whole process does not increase new processing step and technology cost.
(3) bury oxide layer through corrosion part and make dark silicon trench bottom isolation oxidation layer thickness increase, the isolating oxide layer average thickness increases, dark silicon groove through the time dielectric breakdown life-span increase, improved the reliability that dark silicon groove is isolated.As shown in Figure 6; The dark silicon groove that adopts the traditional handicraft manufacturing under the constant voltage stress 225v through the time dielectric breakdown time be 20s; And the dark silicon groove that adopts the described technology manufacturing of this patent under the constant voltage stress 260v through the time dielectric breakdown time can reach 32s, increased the operating voltage range and the useful life of dark silicon groove.
Description of drawings
Fig. 1-the 1st, the growth step of surface oxide layer in the traditional handicraft;
Fig. 1-2 adopts photoresist to etch the window of silicon groove size in the traditional handicraft;
Fig. 1-the 3rd, the step of etching top layer silicon in the traditional handicraft;
Fig. 1-the 4th, the growth step of isolating oxide layer in the traditional handicraft;
Fig. 1-the 5th, polysilicon is filled dark silicon groove step in the traditional handicraft.
Fig. 2-the 1st, the growth step of surface oxide layer among the present invention;
Fig. 2-the 2nd adopts photoresist to etch the window of silicon groove size among the present invention;
Fig. 2-the 3rd, silicon groove etching step among the present invention;
Fig. 2-the 4th, the corrosion surface oxide layer is buried the oxide layer step with part among the present invention;
Fig. 2-the 5th, the growth step of isolating oxide layer among the present invention;
Fig. 2-the 6th, polysilicon is filled the step of dark silicon groove among the present invention.
Fig. 3 is the horizontal over etching phenomenon of ubiquitous bottom silicon in the actual etching technics.
Fig. 4 is the dark silicon grooved profile structure comparison diagram that adopts traditional handicraft and technology of the present invention to make.
Fig. 5 is the dark silicon groove structure voltage endurance that adopts traditional handicraft and technology of the present invention to make.
Fig. 6 be adopt traditional handicraft and technology of the present invention manufacturing dark silicon groove structure through the time dielectric breakdown (TDDB) curve.
Embodiment
With reference to Fig. 2-1-2-6, a kind of preparation technology of upper silicon and deep silicon trench isolation structure for insulator comprises:
A, on Semiconductor substrate 1, be provided with and bury oxide layer 2; Be provided with N type top monocrystalline silicon 3 on the oxide layer 2 burying; On N type top monocrystalline silicon 3, generate surface oxide layer 41; At surface oxide layer 41 surface-coated photoresists 42, on photoresist 42, etch the window of dark silicon groove size and expose surface oxide layer 41;
The surface oxide layer 41 that b, corrosion expose also exposes the N type top monocrystalline silicon 3 of wanting etching;
C, utilize the masking layer of surface oxide layer 41, adopt the anisotropic plasma dry etch process, etch aspect ratio and be 7: 1.2 to 7: 3 dark silicon groove as etching N type top monocrystalline silicon 3; And then erode surface oxide layer 41 fully; Oxide layer 2 is buried in corrosion simultaneously; Making the degree of depth that moves down of the bottom position of dark silicon groove is to bury the 15%-25% of the thickness of oxide layer 2, in the present embodiment, moves down the degree of depth and be 15%, 18%, 23% or 25% of the thickness that buries oxide layer 2;
D, employing wet oxygen method growth isolating oxide layer 5 on the sidewall of dark silicon groove;
E, the undoped polysilicon 6 of employing are filled dark silicon groove, and whole deep trouth inside is filled by medium fully.
In the present embodiment, said surface oxide layer 41 thickness as the etching masking layer are less than burying 15% of oxide layer 2 thickness, for example: surface oxide layer 41 thickness as the etching masking layer are to bury 2%, 7%, 10% or 15% of oxide layer 2 thickness.
Below be to realize the concrete specific embodiments of the present invention:
1, protection oxide layer; On silicon-on-insulator material; Form surface oxide layer through dry oxidation or low-pressure vapor phase chemical deposition, thickness
is like Fig. 2-1.
2, etching photoresist covers one deck photoresist in step 1 back, utilizes photoresist to etch the window of silicon groove size and exposes the protection oxide layer, like Fig. 2-2.
3, the protection oxide layer of falling to expose with conventional method photoetching or wet etching, and expose the N type top monocrystalline silicon of wanting etching.
4, etch silicon groove utilizes the protection oxide layer as the etching masking layer, adopts anisotropic plasma reactive ion etching technology etching N type top monocrystalline silicon, etches aspect ratio and be 7: 2 dark silicon groove, like Fig. 2-3.
5, corrosion protection oxide layer and bury oxide layer is because the oxide layer of burying oxide layer and top monocrystalline silicon surface coverage that trench bottom exposes out can be corroded simultaneously.Set the corrosion menu, guarantee to erode the oxide layer of burying of the about 15%-25% of thickness, like Fig. 2-4.For example to burying the silicon-on-insulator material that oxidated layer thickness is 1-1.5um, desired etching is buried oxidated layer thickness, and erode thickness for
is extra be that the oxide layer of burying of 15%-25% is obviously not influence for the vertical withstand voltage of SOI device.
6, growth isolating oxide layer, the method for utilizing means of wet thermal oxidation one deck isolating oxide layer of on N type top monocrystalline silicon surface and silicon groove sidewall, growing is like Fig. 2-5.For example; To operating voltage is the system of 200v, and isolating oxide layer can be in
scope.
7, fill polysilicon, the undoped polysilicon of deposit in the silicon groove because it is mobile strong, fills up whole silicon groove easily, is not prone to cavity in the silicon groove, like Fig. 2-6.
Claims (2)
1. the preparation technology of a upper silicon and deep silicon trench isolation structure for insulator; Comprise: a, on Semiconductor substrate (1), be provided with and bury oxide layer (2); Be provided with N type top monocrystalline silicon (3) on the oxide layer (2) burying; Go up generation surface oxide layer (41) in N type top monocrystalline silicon (3),, on photoresist (42), etch the window of dark silicon groove size and expose surface oxide layer (41) at surface oxide layer (41) surface-coated photoresist (42); The surface oxide layer (41) that b, corrosion expose also exposes the N type top monocrystalline silicon (3) of wanting etching; It is characterized in that,
C, utilize the masking layer of surface oxide layer (41), adopt the anisotropic plasma dry etch process, etch aspect ratio and be 7: 1.2 to 7: 3 dark silicon groove, and N type top monocrystalline silicon (3) is carved fully and worn as etching N type top monocrystalline silicon (3); And then erode surface oxide layer (41) fully, oxide layer (2) is buried in corrosion simultaneously, and making the degree of depth that moves down of the bottom position that is arranged in the dark silicon groove that buries oxide layer (2) is to bury the 15%-25% of the thickness of oxide layer (2);
D, adopt the wet oxygen method isolating oxide layer (5) of on the sidewall of dark silicon groove, growing;
E, adopt undoped polysilicon (6) to fill dark silicon groove.
2. the preparation technology of the dark silicon groove of silicon-on-insulator according to claim 1 is characterized in that said surface oxide layer as the etching masking layer (41) thickness is less than burying 15% of oxide layer (2) thickness.
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