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CN101820721B - Substrate for circuit board, circuit board and method for manufacturing circuit board - Google Patents

Substrate for circuit board, circuit board and method for manufacturing circuit board Download PDF

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Publication number
CN101820721B
CN101820721B CN2009100067890A CN200910006789A CN101820721B CN 101820721 B CN101820721 B CN 101820721B CN 2009100067890 A CN2009100067890 A CN 2009100067890A CN 200910006789 A CN200910006789 A CN 200910006789A CN 101820721 B CN101820721 B CN 101820721B
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circuit board
substrate
layer
elasticity
matrix
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CN101820721A (en
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曾毅
高国书
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Industrial Technology Research Institute ITRI
Chunghwa Picture Tubes Ltd
Chi Mei Optoelectronics Corp
Hannstar Display Corp
Taiwan TFT LCD Association
AUO Corp
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Industrial Technology Research Institute ITRI
Chunghwa Picture Tubes Ltd
Chi Mei Optoelectronics Corp
Hannstar Display Corp
AU Optronics Corp
Taiwan TFT LCD Association
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Abstract

The invention discloses a base material for a circuit board, the circuit board and a manufacturing method of the circuit board. The circuit board comprises a substrate, a plurality of elastic bumps and a patterned circuit layer. The elastic bumps are arranged in a matrix manner and are arranged on the substrate. The patterned circuit layer is configured on part of the elastic salient points and part of the substrate.

Description

电路板用的基材、电路板以及电路板的制造方法Substrate for circuit board, circuit board and method for manufacturing circuit board

技术领域 technical field

本发明涉及一种电路板,特别是涉及电路板用的基材的结构与其制造方法。The invention relates to a circuit board, in particular to the structure of a base material for the circuit board and its manufacturing method.

背景技术 Background technique

可挠性电路板或称柔性电路板是以软质有机材料做为基板的一种线路板,其可应用在连续性动态弯折的产品中。目前可挠性电路板大多以铜制作电极,为了提供足够的空间以容置粘合所需要的胶材,铜电极(或称线路)的厚度通常厚达8微米至12微米。然而,由于铜电极的厚度太厚,可挠性差,而且其与有机基板的热膨胀系数的差异大,因此,在接合后或弯折时所产生的应力,而导致电路板可靠度不佳等问题。此外,在工艺上,在蚀刻铜层以形成铜电极的过程中,由于铜层的厚度较厚,因此,在蚀刻角的限制下,蚀刻的间距过小会造成铜电极的底部无法完全蚀刻分离而发生短路的现象,或因过度蚀刻造成电极顶部面积过小而影响导电性能。为了避免短路的发生,通常,铜电极之间必须维持足够的间距,如此,将使得小型化的发展受限。Flexible circuit board or flexible circuit board is a kind of circuit board with soft organic material as the substrate, which can be applied in continuous dynamic bending products. At present, the electrodes of flexible circuit boards are mostly made of copper. In order to provide enough space to accommodate the glue required for bonding, the thickness of copper electrodes (or circuits) is usually as thick as 8 microns to 12 microns. However, because the thickness of the copper electrode is too thick, the flexibility is poor, and the difference in thermal expansion coefficient between it and the organic substrate is large, so the stress generated after bonding or bending will cause problems such as poor reliability of the circuit board. . In addition, in terms of technology, in the process of etching the copper layer to form the copper electrode, due to the thick copper layer, under the limitation of the etching angle, the etching spacing is too small, which will cause the bottom of the copper electrode to be unable to be completely etched and separated. Short circuit occurs, or the top area of the electrode is too small due to over-etching, which affects the conductivity. In order to avoid the occurrence of short circuits, generally, sufficient spacing must be maintained between the copper electrodes, which limits the development of miniaturization.

有关可挠性电路板的专例如美国专利7,250,575。然而,该专利的方法是把原本在IC端的金凸块工艺改在软板工艺中。另外,美国专利5,949,512,通过机构设计来解决软板在弯折时因铜与有机材料的杨氏模量(Young’sModule)差异造成应力集中而使铜线路断裂。此外,美国专利7,299,547主要是以有机的弹性线路取代原有的铜线路,以使结构的可靠度增加。Patents related to flexible circuit boards include US Patent 7,250,575. However, the method of this patent is to change the original gold bump process on the IC side to the soft board process. In addition, US Patent No. 5,949,512 solves the problem of breaking the copper circuit due to the stress concentration caused by the difference in the Young's Module of the copper and the organic material when the soft board is bent through the design of the mechanism. In addition, US Patent No. 7,299,547 mainly replaces the original copper circuit with an organic elastic circuit to increase the reliability of the structure.

发明内容 Contents of the invention

本发明提出一种电路板,其包括基板、多个弹性凸点以及图案化的线路层。上述多个弹性凸点以至少一矩阵方式排列,设置于基板上。图案化的线路层配置于一部分的上述多个弹性凸点上以及部分的基板上。The invention provides a circuit board, which includes a substrate, a plurality of elastic bumps and a patterned circuit layer. The above-mentioned plurality of elastic bumps are arranged in at least one matrix and arranged on the substrate. The patterned circuit layer is disposed on a part of the plurality of elastic bumps and a part of the substrate.

本发明又提出一种电路板用的基材,其包括基板;以及多个弹性凸点,以至少一矩阵方式排列,设置于该基板上。The invention further provides a base material for a circuit board, which includes a substrate; and a plurality of elastic bumps arranged in at least one matrix and disposed on the substrate.

本发明又提出一种电路板的制造方法,此方法是先在基板上形成弹性凸点材料层,再图案化弹性凸点材料层,以形成以至少一矩阵方式排列的多个弹性凸点。之后,再形成至少一层导电层,覆盖上述多个弹性凸点与基板。其后,图案化导电层,以形成图案化的线路层,覆盖于一部分的上述多个弹性凸点以及部分的基板上。The present invention also proposes a method for manufacturing a circuit board. In the method, an elastic bump material layer is first formed on a substrate, and then the elastic bump material layer is patterned to form a plurality of elastic bumps arranged in at least one matrix. After that, at least one conductive layer is formed to cover the plurality of elastic bumps and the substrate. Thereafter, the conductive layer is patterned to form a patterned circuit layer covering a part of the plurality of elastic bumps and a part of the substrate.

为让本发明的上述特征和优点能更明显易懂,下文特举优选实施例,并配合附图,作详细说明如下。In order to make the above-mentioned features and advantages of the present invention more comprehensible, preferred embodiments will be described in detail below together with the accompanying drawings.

附图说明 Description of drawings

图1是依照本发明实施例所绘示的一种电路板用的基材的剖面示意图。FIG. 1 is a schematic cross-sectional view of a substrate for a circuit board according to an embodiment of the present invention.

图1A是图1的一种电路板用的基材的俯视图。FIG. 1A is a top view of a substrate for a circuit board in FIG. 1 .

图1B是图1的另一种电路板用的基材的俯视图。FIG. 1B is a top view of another circuit board substrate of FIG. 1 .

图2A是依照本发明另一实施例所绘示的一种电路板用的基材的俯视图。FIG. 2A is a top view of a substrate for a circuit board according to another embodiment of the present invention.

图2B是依照本发明又一实施例所绘示的一种电路板用的基材的俯视图。FIG. 2B is a top view of a substrate for a circuit board according to yet another embodiment of the present invention.

图3是依照本发明再一实施例所绘示的一种电路板用的基材的剖面示意图。3 is a schematic cross-sectional view of a substrate for a circuit board according to yet another embodiment of the present invention.

图4A是依照本发明实施例所绘示的一种电路板的立体视图。FIG. 4A is a perspective view of a circuit board according to an embodiment of the present invention.

图4B是依照本发明另一实施例所绘示的一种电路板的立体视图。FIG. 4B is a perspective view of a circuit board according to another embodiment of the present invention.

图5A至5E是一种集成电路的电路板的制造方法的剖面示意图,这些图为沿着图4A的剖面线V-V的剖面图。5A to 5E are schematic cross-sectional views of a manufacturing method of a circuit board of an integrated circuit, and these figures are cross-sectional views along the line V-V of FIG. 4A.

附图标记说明Explanation of reference signs

10、10A、10B、10C、10D、10E:电路板用的基材10, 10A, 10B, 10C, 10D, 10E: Substrates for circuit boards

12:基板                      13:弹性材料层12: Substrate 13: Elastic material layer

14:弹性凸点                  16:导电层14: Elastic bumps 16: Conductive layer

16A、16B:图案化的线路层      16a:内引脚16A, 16B: patterned circuit layer 16a: inner pin

16b:外引脚                   16c:连接部16b: External pin 16c: Connecting part

18:保护层                    20A、20B:电路板18: Protective layer 20A, 20B: Circuit board

22:图案化光致抗蚀剂层        24、26、30、40、50、60:矩阵22: Patterned photoresist layer 24, 26, 30, 40, 50, 60: Matrix

W、W1、W2:间隙宽度           h:弹性凸点高度W, W1, W2: Gap width h: Elastic bump height

V-V:剖面线V-V: hatching

具体实施方式 Detailed ways

图1是依照本发明实施例所绘示的一种电路板用的基材的剖面示意图。图1A是图1的一种电路板用的基材的俯视图。图1B是图1的另一种电路板用的基材的俯视图。图2A是依照本发明另一实施例所绘示的一种电路板用的基材的俯视图。图2B是依照本发明又一实施例所绘示的一种电路板用的基材的俯视图。图3是依照本发明再一实施例所绘示的一种电路板用的基材的剖面示意图。FIG. 1 is a schematic cross-sectional view of a substrate for a circuit board according to an embodiment of the present invention. FIG. 1A is a top view of a substrate for a circuit board in FIG. 1 . FIG. 1B is a top view of another circuit board substrate of FIG. 1 . FIG. 2A is a top view of a substrate for a circuit board according to another embodiment of the present invention. FIG. 2B is a top view of a substrate for a circuit board according to yet another embodiment of the present invention. 3 is a schematic cross-sectional view of a substrate for a circuit board according to yet another embodiment of the present invention.

请同时参照图1,本发明实施例的电路板用的基材10包括基板12与多个弹性凸点14。基板12的材料包括有机绝缘材料或无机绝缘材料。有机绝缘材料,例如是聚酰亚胺(Polyimide,PI)、聚对苯二甲酸乙二酯(Polyethyleneterephthalate,PET)。无机绝缘材料例如是玻璃或陶瓷。基板12可以是可挠式基板或硬式基板Please also refer to FIG. 1 , the substrate 10 for a circuit board according to the embodiment of the present invention includes a substrate 12 and a plurality of elastic bumps 14 . The material of the substrate 12 includes an organic insulating material or an inorganic insulating material. The organic insulating material is, for example, polyimide (Polyimide, PI), polyethylene terephthalate (Polyethyleneterephthalate, PET). Inorganic insulating materials are, for example, glass or ceramics. The substrate 12 can be a flexible substrate or a rigid substrate

弹性凸点14的作用像是“坐垫(Cushion)”,可吸收来自多种电子元件间因热膨胀系数差异所产生的热应力,以及接合时的机械应力,因此弹性凸点14愈软、愈有弹性,其效果愈明显。弹性凸点14是以矩阵方式排列,设置于基板12上。在实施例中,本发明的弹性凸点14排列成单一矩阵,如图1A的电路板用的基材10A的矩阵24,或图1B的电路板用的基材10B矩阵26所示者。在另一实施例中,请参照图2A所示,电路板用的基材10C的弹性凸点14也可以排列成两个彼此分隔的矩阵30、40。在图2A中,矩阵30、40可以相同或是相异。此处所述的相同或相异,是指矩阵中弹性凸点14的排列方式、弹性凸点14的大小、高度、形状或弹性凸点14之间的间隙宽度相同或是相异。当然弹性凸点14也可以依据需要排列成多个彼此分隔的矩阵。在又一实施例中,请参照图2B所示,电路板用的基材10D的弹性凸点14排列成两个彼此相邻的不同的矩阵50、60。此处所述的不同的矩阵50、60可以是指矩阵50、60中的弹性凸点14的排列方式、弹性凸点14的大小、高度、形状或弹性凸点14之间的间隙宽度不同,在图2B中以弹性凸点14排列方式不同的两个矩阵50、60来说明。当然弹性凸点14也可以依据需要排列成多个彼此相邻的矩阵。The function of the elastic bump 14 is like a "cushion", which can absorb the thermal stress caused by the difference in thermal expansion coefficient between various electronic components, as well as the mechanical stress during bonding, so the softer the elastic bump 14 is, the more firm it is. The more elastic, the more obvious the effect. The elastic bumps 14 are arranged in a matrix and disposed on the substrate 12 . In an embodiment, the elastic bumps 14 of the present invention are arranged in a single matrix, such as the matrix 24 of the substrate 10A for a circuit board in FIG. 1A or the matrix 26 of the substrate 10B for a circuit board in FIG. 1B . In another embodiment, as shown in FIG. 2A , the elastic bumps 14 of the substrate 10C for circuit boards can also be arranged in two separate matrices 30 , 40 . In FIG. 2A, the matrices 30, 40 may be the same or different. The same or different here means that the arrangement of the elastic bumps 14 in the matrix, the size, height, shape of the elastic bumps 14 or the width of the gap between the elastic bumps 14 are the same or different. Of course, the elastic bumps 14 can also be arranged in a plurality of matrixes separated from each other as required. In yet another embodiment, as shown in FIG. 2B , the elastic bumps 14 of the substrate 10D for circuit boards are arranged in two different matrices 50 , 60 adjacent to each other. The different matrices 50, 60 described here may refer to the arrangement of the elastic bumps 14 in the matrix 50, 60, the size, height, shape of the elastic bumps 14 or the gap width between the elastic bumps 14, In FIG. 2B , two matrices 50 and 60 with different arrangements of the elastic bumps 14 are used for illustration. Of course, the elastic bumps 14 can also be arranged in a plurality of adjacent matrices as required.

关于矩阵中弹性凸点14的排列方式,请参照图1A,在实施例中,本发明的多个弹性凸点14所排列成的矩阵24包括数列C1.....CN与数行R1...RN,且任意相邻两列,如C3、C4的多个凸点彼此对齐,任意相邻两行,如R2、R3的多个凸点也是彼此对齐。在另一实施例中,请参照图1B,本发明的多个弹性凸点14所排行成的矩阵26例如是包括数列C1.....CN与数行R1...RN,且任意相邻两列,如C3、C4的多个凸点彼此交错,任意相邻两行,如R2、R3的多个凸点也是彼此交错。Regarding the arrangement of the elastic bumps 14 in the matrix, please refer to FIG. 1A. In an embodiment, the matrix 24 formed by the plurality of elastic bumps 14 of the present invention includes a sequence C1.....CN and a number row R1. ..RN, and any two adjacent columns, such as multiple bumps of C3 and C4 are aligned with each other, and any two adjacent rows, such as multiple bumps of R2 and R3 are also aligned with each other. In another embodiment, please refer to FIG. 1B , the matrix 26 formed by a plurality of elastic bumps 14 of the present invention includes, for example, a number of columns C1...CN and a number of rows R1...RN, and any phase Two adjacent columns, such as multiple bumps of C3 and C4 are staggered with each other, and any two adjacent rows, such as multiple bumps of R2 and R3 are also staggered with each other.

请参照图1、图1A与图1B,在实施例中,弹性凸点14的大小例如是直径10微米,但,并不以此为限。高度h至少3微米或以上,以提供足够的空间以容置粘合所需要的胶材。此外,在本实施例中,是以圆形的弹性凸点14做为说明,然而,弹性凸点14的形状并不以此为限,其可以呈方形、菱形、矩形、多角形、椭圆形等。弹性凸点14的材料包括有机材料或是无机材料。有机材料,其可以是绝缘或是导电,例如是聚酰亚胺(Polyimide,PI)、聚对苯二甲酸乙二酯(Polyethylene terephthalate,PET)。无机材料例如是玻璃或陶瓷。Please refer to FIG. 1 , FIG. 1A and FIG. 1B , in the embodiment, the size of the elastic bump 14 is, for example, 10 microns in diameter, but it is not limited thereto. The height h is at least 3 microns or above to provide enough space for accommodating the glue required for bonding. In addition, in this embodiment, the circular elastic bump 14 is used as an illustration, however, the shape of the elastic bump 14 is not limited thereto, and it can be square, rhombus, rectangle, polygon, oval wait. The materials of the elastic bumps 14 include organic materials or inorganic materials. The organic material can be insulating or conductive, such as polyimide (PI), polyethylene terephthalate (PET). Inorganic materials are, for example, glass or ceramics.

请参照图1、图1A,在矩阵中,弹性凸点14之间的间隙宽度W至少5微米或以上,以提供粘合胶材在压合时有足够的流动空间。在实施例中,在矩阵中,任意相邻两列,如C3、C4的弹性凸点14的之间的间隙宽度W1,其与任意相邻两行,如R2、R3的弹性凸点14的之间的间隙宽度W2实质上相同。在另一实施例中,在矩阵中,任意相邻两列,如C3、C4的弹性凸点14的之间的间隙宽度W1实质上相同,任意相邻两行,如R2、R3的弹性凸点14的之间的间隙宽度W2也实质上相同,但,间隙宽度W1与间隙宽度W2不同。Please refer to FIG. 1 and FIG. 1A , in the matrix, the gap width W between the elastic bumps 14 is at least 5 microns or more, so as to provide sufficient flow space for the adhesive material during lamination. In an embodiment, in the matrix, the gap width W1 between any two adjacent columns, such as the elastic bumps 14 of C3 and C4, is the same as that of any two adjacent rows, such as the elastic bumps 14 of R2 and R3. The gap width W2 between them is substantially the same. In another embodiment, in the matrix, any two adjacent columns, such as the gap width W1 between the elastic bumps 14 of C3 and C4 are substantially the same, and any two adjacent rows, such as the elastic bumps of R2 and R3 The gap width W2 between the dots 14 is also substantially the same, but the gap width W1 is different from the gap width W2.

请参照图1,在以上的实施例中,电路板用的基材10包括基板12与多个弹性凸点14,业者在取得上述的电路板用的基材之后,仅需再形成导电层16并对导电层16进行图案化即可形成具有图案化的线路层的电路板。Please refer to FIG. 1 , in the above embodiment, the base material 10 for circuit boards includes a substrate 12 and a plurality of elastic bumps 14 , and the industry only needs to form a conductive layer 16 after obtaining the base material for circuit boards described above. And patterning the conductive layer 16 can form a circuit board with a patterned circuit layer.

请参照图3,在另一实施例中,除了基板12与多个弹性凸点14之外,电路板用的基材10E还包括至少一层导电层16,其毯覆式覆盖于弹性凸点14与基板12上,以作为线路层。导电层16的材料例如金属或是导电高分子。金属例如是铜、铜合金、铝、银、镍、金或钛。金属层的厚度可依电流大小调整,其厚度至少0.1微米或以上,但并不以此为限。导电高分子例如是聚乙炔(Polyacetylene)、聚苯胺(Polyaniline;PANi)、聚吡咯(Polypyrrole)。导电高分子的厚度至少3微米或以上,以提供足够的空间容置粘合所需要的胶材。业者在取得此电路板用的基材10A之后,仅需对导电层16进行图案化即可形成具有图案化的线路层的电路板。Please refer to FIG. 3, in another embodiment, in addition to the substrate 12 and a plurality of elastic bumps 14, the base material 10E for the circuit board also includes at least one layer of conductive layer 16, which blankets the elastic bumps. 14 and the substrate 12 as a circuit layer. The material of the conductive layer 16 is, for example, metal or conductive polymer. Metals are, for example, copper, copper alloys, aluminum, silver, nickel, gold or titanium. The thickness of the metal layer can be adjusted according to the magnitude of the current, and the thickness is at least 0.1 micron or above, but not limited thereto. The conductive polymer is, for example, polyacetylene (Polyacetylene), polyaniline (Polyaniline; PANi), and polypyrrole (Polypyrrole). The thickness of the conductive polymer is at least 3 micrometers or above to provide enough space for the adhesive required for bonding. After obtaining the substrate 10A for the circuit board, the trader only needs to pattern the conductive layer 16 to form a circuit board with a patterned circuit layer.

图4A是依照本发明实施例所绘示的一种电路板的立体视图。图4B分别是依照本发明另一实施例所绘示的另一种电路板的立体视图。FIG. 4A is a perspective view of a circuit board according to an embodiment of the present invention. FIG. 4B is a three-dimensional view of another circuit board according to another embodiment of the present invention.

请参照图4A或4B,本发明的电路板20A或20B除了包括如图1A、1B、2A或2B所述基板12与多个呈矩阵排列的弹性凸点14之外,还包括具有图案化的线路层16A以及保护层18,如图4A所示,或还包括具有图案化的线路层16B以及保护层18,如图4B所示。图案化的线路层16A或16B配置于部分的弹性凸点14上以及部分的基板12上。保护层18覆盖部分图案化的线路层16A或16B、未被图案化的线路层16A或16B覆盖的部分的弹性凸点14以及部分的基板12上。Please refer to FIG. 4A or 4B, the circuit board 20A or 20B of the present invention, in addition to including the substrate 12 and a plurality of elastic bumps 14 arranged in a matrix as shown in FIG. 1A, 1B, 2A or 2B, also includes patterned The wiring layer 16A and the protective layer 18 are shown in FIG. 4A , or further include a patterned wiring layer 16B and the protective layer 18 , as shown in FIG. 4B . The patterned circuit layer 16A or 16B is disposed on part of the elastic bumps 14 and part of the substrate 12 . The protection layer 18 covers part of the patterned circuit layer 16A or 16B, the part of the elastic bump 14 not covered by the patterned circuit layer 16A or 16B, and part of the substrate 12 .

请参照图4A,本实施例的电路板20A可以用做为集成电路的载板,其图案化的线路层16A包括内引脚16a、外引脚16b以及连接内引脚16a与外引脚16b的连接部16c。保护层18覆盖图案化的线路层16A的连接部16c,裸露出图案化的线路层16a的内引脚16a与外引脚16b,使内引脚16a可以与芯片连接,而外引脚16b可以与其他印刷电路板或是面板等连接。Please refer to Fig. 4A, the circuit board 20A of the present embodiment can be used as the carrier board of integrated circuit, and its patterned line layer 16A comprises inner pin 16a, outer pin 16b and connects inner pin 16a and outer pin 16b The connection part 16c. The protective layer 18 covers the connection portion 16c of the patterned circuit layer 16A, exposing the inner pin 16a and the outer pin 16b of the patterned circuit layer 16a, so that the inner pin 16a can be connected to the chip, and the outer pin 16b can Connect with other printed circuit boards or panels.

请参照图4B,本实施例的电路板20B图案化的线路层16B的图案例如是具有多条平行的金属线,但并不以此为限,使电路板20B可以用做为电子元件间的连接板,或测试板,如IC测试板、LCD面板测试板。Please refer to FIG. 4B, the pattern of the circuit layer 16B patterned on the circuit board 20B of this embodiment, for example, has a plurality of parallel metal lines, but it is not limited thereto, so that the circuit board 20B can be used as a connection between electronic components. Connection board, or test board, such as IC test board, LCD panel test board.

本发明是以弹性凸点与导电层来制作弹性电极。弹性凸点可解决电子元件接合后,因元件间的热膨胀系数(Coefficient of Thermal Expansion)差异所造成的可靠度不良的问题。The invention uses elastic bumps and conductive layers to make elastic electrodes. Elastic bumps can solve the problem of poor reliability caused by differences in the coefficient of thermal expansion (Coefficient of Thermal Expansion) between components after bonding electronic components.

图5A至5E是一种集成电路的电路板的制造方法的剖面示意图,这些图为沿着图4A的剖面线V-V的剖面图。5A to 5E are schematic cross-sectional views of a manufacturing method of a circuit board of an integrated circuit, and these figures are cross-sectional views along the line V-V of FIG. 4A.

请参照图5A,提供基板12。基板12的材料包括有机材料,例如是聚酰亚胺(Polyimide,PI)、聚对苯二甲酸乙二酯(Polyethylene terephthalate,PET)。基板12可以是可挠式基板12或硬式基板12。接着,在基板12上形成弹性材料层13。弹性材料层13的材料包括至少一种有机材料,例如是聚酰亚胺(Polyimide,PI)。弹性材料层13的形成方法例如是涂布法或是压合法。之后,可以依据需要对弹性材料层13进行预烘烤工艺,使弹性材料层13固化。Referring to FIG. 5A , a substrate 12 is provided. The material of the substrate 12 includes organic materials such as polyimide (PI) and polyethylene terephthalate (PET). The substrate 12 can be a flexible substrate 12 or a rigid substrate 12 . Next, the elastic material layer 13 is formed on the substrate 12 . The material of the elastic material layer 13 includes at least one organic material, such as polyimide (PI). The method of forming the elastic material layer 13 is, for example, a coating method or a pressing method. Afterwards, the elastic material layer 13 may be pre-baked as required to cure the elastic material layer 13 .

然后,请参照图5B,将弹性材料层13图案化,以形成多个弹性凸点14,这些弹性凸点14排列成两个分隔的矩阵30与40。当弹性材料层13为感光性有机材料时,将弹性材料层13图案化的方法例如是直接对弹性材料层13进行曝光与显影。至此,即完成如上图1所示的电路板用的基材的制作。Then, referring to FIG. 5B , the elastic material layer 13 is patterned to form a plurality of elastic bumps 14 , and these elastic bumps 14 are arranged into two separate matrices 30 and 40 . When the elastic material layer 13 is a photosensitive organic material, the method of patterning the elastic material layer 13 is, for example, directly exposing and developing the elastic material layer 13 . So far, the production of the base material for the circuit board as shown in Fig. 1 above is completed.

之后,请参照图5C,在基板12上形成至少一导电层16,覆盖上述弹性凸点14。导电层16的材料例如金属或是导电高分子。金属例如是铜、铜合金、铝、银、镍、金,形成的方法例如是溅镀(Sputter)、蒸镀(Evaporation)或其他适当的物理气相沉积法,或者是无电电镀(Electroless plating)、化学气相沉积法(chemical vapor deposition,CVD)或其他适当的化学沉积法。金属的导电层16的厚度依电流大小调整,其厚度例如为0.1微米或以上,但并不以此为限。导电高分子例如是聚乙炔(Polyacetylene)、聚苯胺(Polyaniline;PANi)、聚吡咯(Polypyrrole)。形成的方法例如是涂布。导电高分子的导电层16的厚度为3微米以上,提供足够的空间以容置粘合所需要的胶材。至此,即完成如上图3所示的电路板用的基材的制作。Afterwards, referring to FIG. 5C , at least one conductive layer 16 is formed on the substrate 12 to cover the elastic bumps 14 . The material of the conductive layer 16 is, for example, metal or conductive polymer. Metals such as copper, copper alloys, aluminum, silver, nickel, gold, formed by methods such as sputtering (Sputter), evaporation (Evaporation) or other appropriate physical vapor deposition methods, or electroless plating (Electroless plating) , chemical vapor deposition (chemical vapor deposition, CVD) or other appropriate chemical deposition methods. The thickness of the metal conductive layer 16 is adjusted according to the magnitude of the current, and its thickness is, for example, 0.1 μm or above, but not limited thereto. The conductive polymer is, for example, polyacetylene (Polyacetylene), polyaniline (Polyaniline; PANi), and polypyrrole (Polypyrrole). The forming method is, for example, coating. The thickness of the conductive layer 16 of the conductive polymer is more than 3 micrometers, which provides enough space for accommodating the glue required for bonding. So far, the production of the base material for the circuit board as shown in Fig. 3 above is completed.

之后,请参照图5D,在导电层16上形成光致抗蚀剂层(未绘示)。其后,进行曝光与显影,以图案化光致抗蚀剂层22。之后,再以图案化的光致抗蚀剂层22为掩模,将导电层16图案化,以形成图案化的线路层16A,覆盖部分弹性凸点14以及部分的基板12。图案化的线路层16A包括内引脚16a、外引脚16b以及连接内引脚16a与外引脚16b的连接部16c。After that, referring to FIG. 5D , a photoresist layer (not shown) is formed on the conductive layer 16 . Thereafter, exposure and development are performed to pattern the photoresist layer 22 . Afterwards, the conductive layer 16 is patterned by using the patterned photoresist layer 22 as a mask to form a patterned wiring layer 16A covering part of the elastic bumps 14 and part of the substrate 12 . The patterned circuit layer 16A includes an inner lead 16a, an outer lead 16b, and a connecting portion 16c connecting the inner lead 16a and the outer lead 16b.

然后,请参照图5E,将图案化的光致抗蚀剂层22移除。当图案化的光致抗蚀剂层22移除之后,基板12上仍保留着矩阵30与40的弹性凸点14,而其中,一部分的弹性凸点14被图案化的线路层16A所覆盖;另一部份的弹性凸点14则未被图案化的线路层所覆盖。之后,再于基板12上形成保护材料层18。保护材料层18的材料包括绝缘材料,例如高分子材料,如环氧树脂(Epoxy),形成的方法例如是网板印刷。Then, referring to FIG. 5E , the patterned photoresist layer 22 is removed. After the patterned photoresist layer 22 is removed, the elastic bumps 14 of the matrix 30 and 40 still remain on the substrate 12, and a part of the elastic bumps 14 are covered by the patterned circuit layer 16A; Another part of the elastic bumps 14 is not covered by the patterned circuit layer. After that, a protective material layer 18 is formed on the substrate 12 . The material of the protective material layer 18 includes insulating materials, such as polymer materials, such as epoxy resin (Epoxy), and the forming method is, for example, screen printing.

本发明是以弹性凸点与导电层来制作弹性电极,取代已知柔性电路板上原有的铜电极,因舍去原有的铜电极,增加柔性电路板的柔软度,故,可增加接合后及弯折时的可靠性。由于弹性凸点可提供足够的高度以容置接合胶材,因此,所需要的导电层较薄,因此,在工艺上具有较大的蚀刻角容忍度,而且,可蚀刻出较为精细的图案,使蚀刻间距大幅缩小,大幅提升电极的密度。另外,由于弹性凸点是以矩阵方式设置在基板上,因此,可供不同线路图案应用,因此,其可应用的范围广泛。另一方面,此技术亦可应用在硬板上,除接合外亦可作测试板应用在测试领域上。此外,本发明实施例的工艺可以现有生产技术作改良,因此并不需再投资大笔的生产设备即可大量生产。The present invention uses elastic bumps and conductive layers to make elastic electrodes to replace the original copper electrodes on the known flexible circuit board. Because the original copper electrodes are discarded, the softness of the flexible circuit board is increased, so the post-bonding can be increased. and reliability when bending. Since the elastic bumps can provide sufficient height to accommodate the bonding adhesive, the required conductive layer is thinner, so the process has a greater tolerance for etching angles, and more fine patterns can be etched. The etching spacing is greatly reduced, and the electrode density is greatly increased. In addition, since the elastic bumps are arranged on the substrate in a matrix, they can be used in different circuit patterns, and thus have a wide range of applications. On the other hand, this technology can also be applied to rigid boards, and it can also be used as a test board in the testing field in addition to bonding. In addition, the process of the embodiment of the present invention can be improved by the existing production technology, so mass production can be achieved without further investment in large production equipment.

虽然本发明已以实施例披露如上,然其并非用以限定本发明,任何所属技术领域中普通技术人员,在不脱离本发明的精神和范围内,当可作些许的更动与润饰,因此本发明的保护范围当视后附的权利要求所界定的为准。Although the present invention has been disclosed above with embodiments, it is not intended to limit the present invention. Any person skilled in the art may make some changes and modifications without departing from the spirit and scope of the present invention. Therefore, The protection scope of the present invention shall prevail as defined by the appended claims.

Claims (13)

1. a circuit board comprises
Substrate;
A plurality of elasticity salient points are arranged with at least one matrix-style, are arranged on this substrate;
The line layer of patterning is disposed on the said elasticity salient point of first and on this substrate of part; And
Protective layer is on the said elasticity salient point of the second portion that be covered on the line layer of this patterning of part, the line layer that is not patterned covers and on this substrate of not covered by the said elasticity salient point of this second portion of part.
2. circuit board as claimed in claim 1, the material of wherein said elasticity salient point comprises at least a organic material.
3. circuit board as claimed in claim 1, wherein said elasticity salient point are to arrange with one or more matrix-style.
4. circuit board as claimed in claim 3, wherein said elasticity salient point are to arrange with a plurality of matrix-style, and said matrix is adjacent one another are or separation.
5. circuit board as claimed in claim 1, wherein the material of this substrate comprises at least a organic or inorganic insulating material.
6. circuit board as claimed in claim 5, wherein the substrate of this organic or inorganic insulating material comprises bendable substrate or rigid substrate.
7. circuit board as claimed in claim 1, wherein the line layer of this patterning comprises at least one conductive layer.
8. circuit board as claimed in claim 7, wherein the material of conductive layer comprises metal, alloy, conducting polymer or its combination.
9. the manufacturing approach of a circuit board as claimed in claim 1 comprises:
On this substrate, form this elasticity convex point material layer;
This elasticity convex point material layer of patterning is to form these a plurality of elasticity salient points of arranging with at least one matrix-style;
Form this at least one conductive layer, cover said elasticity salient point and this substrate; And
This conductive layer of patterning to form the line layer of this patterning, is covered on the said elasticity salient point and this substrate of part of this first.
10. the manufacturing approach of circuit board as claimed in claim 9, wherein the material of this elasticity convex point material layer comprises at least a organic material.
11. the manufacturing approach of circuit board as claimed in claim 9, wherein this elasticity convex point material layer be with the coating or the mode of pressing forms.
12. the manufacturing approach of circuit board as claimed in claim 9, wherein the material of the line layer of this patterning comprises at least one conductive layer.
13. the manufacturing approach of circuit board as claimed in claim 12, wherein the material of this conductive layer comprises metal, alloy, conducting polymer or its combination.
CN2009100067890A 2009-02-27 2009-02-27 Substrate for circuit board, circuit board and method for manufacturing circuit board Expired - Fee Related CN101820721B (en)

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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1551714A (en) * 2003-04-17 2004-12-01 �����ɷ� Method for Improving Mechanical Properties of Chip-on-Board Module Devices
JP2005229065A (en) * 2004-02-16 2005-08-25 Fujikura Ltd Method for manufacturing multi-layer and double-sided substrate
US7299547B2 (en) * 2004-06-30 2007-11-27 Samsung Electronics Co., Ltd. Method for manufacturing tape wiring board
US20080017873A1 (en) * 2006-07-18 2008-01-24 Sony Corporation Device, method of manufacturing device, board, method of manufacturing board, mounting structure, mounting method, led display, led backlight and electronic device
JP7250575B2 (en) * 2019-03-13 2023-04-03 株式会社アルバック Deposition equipment

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1551714A (en) * 2003-04-17 2004-12-01 �����ɷ� Method for Improving Mechanical Properties of Chip-on-Board Module Devices
JP2005229065A (en) * 2004-02-16 2005-08-25 Fujikura Ltd Method for manufacturing multi-layer and double-sided substrate
US7299547B2 (en) * 2004-06-30 2007-11-27 Samsung Electronics Co., Ltd. Method for manufacturing tape wiring board
US20080017873A1 (en) * 2006-07-18 2008-01-24 Sony Corporation Device, method of manufacturing device, board, method of manufacturing board, mounting structure, mounting method, led display, led backlight and electronic device
JP7250575B2 (en) * 2019-03-13 2023-04-03 株式会社アルバック Deposition equipment

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
JP特开2005-229065A 2005.08.25

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