CN101814512B - A CMOS Ring Oscillator Based on Silicon-on-Insulator Technology - Google Patents

Abstract

The invention discloses a CMOS ring oscillator based on a silicon-on-insulator process. Its circuit design adopts a reinforced silicon-on-insulator body connection (BC) NMOS tube source terminal to a depleted silicon-on-insulator floating body (FB) NMOS tube. The special device structure suspended in the body area of the floating body improves the relationship between the rise time and the power supply voltage, and improves the correlation between the frequency output and the power supply voltage, thereby better providing stable frequency output and utilizing the high performance of silicon-on-insulator process devices The barrier substrate and buried oxide layer significantly reduce crosstalk and minimize parasitic capacitance, better shielding substrate noise. The vibration frequency of the invention has little change with the power supply voltage, the circuit is simple, and the utility model has strong practicability.

Description

A CMOS Ring Oscillator Based on Silicon-on-Insulator Technology

technical field

The invention relates to the technical field of integrated circuit design and signal processing, in particular to a complementary metal oxide semiconductor (CMOS) ring oscillator based on silicon-on-insulator technology.

Background technique

With the rapid development of wireless communication technology, there is an increasing need for high-performance, low-cost phase-locked loop (Phase Lock Loop) circuits and their basic unit oscillators in the field of RF front-end applications. The phase-locked loop is an important component of the phase-locked loop module circuit in communication circuits and high-speed systems. It is mainly used to generate time references, and its performance determines the performance of the entire system. The Voltage-Controlled Oscillator (Voltage-Controlled Oscillator) is the unit that works at the highest frequency in the phase-locked loop circuit. In recent years, people have conducted extensive research on the Voltage-Controlled Oscillator. There are two main types of voltage-controlled oscillators implemented in integrated circuits: LC voltage-controlled oscillators and ring oscillators.

The ring oscillator is one of the standard oscillator structures widely used in the design of various integrated circuit chips, providing a stable frequency output. Due to the limitations of the process technology, the traditional bulk silicon CMOS ring oscillator cannot realize the high-resistance substrate, reduce the parasitic capacitance, and cannot control the substrate noise well. The oscillation frequency is affected by the change of the power supply voltage and the substrate voltage. The impact is great, when the power supply voltage is reduced by half, the oscillation frequency will be reduced by more than half. The circuit structure of a traditional bulk silicon CMOS ring oscillator is given, as shown in Figure 1.

At present, the main process technologies used in the design of ring oscillators in the field of integrated circuits include traditional bulk silicon RFCMOS technology and SiGe BiCMOS technology, of which SiGe BiCMOS technology is generally used in the design of LC voltage-controlled oscillators to provide better phase noise performance; traditional bulk silicon RFCMOS technology is more suitable for the design of ring oscillators. However, the limitations of traditional bulk silicon RFCMOS technology in terms of noise and characteristic frequency make it not dominant in high-frequency, high-performance RF applications.

The cross-sectional view of the structure of a traditional bulk silicon CMOS device is shown in Figure 2. The active region of the device is directly on the substrate, and full dielectric isolation cannot be achieved. The resulting parasitic thyristor latch-up effect will make the circuit potential At the same time, due to the reduction of feature size and the soft failure problem caused by the reduction of power supply voltage, the anti-interference ability of the circuit will be reduced and the reliability will be reduced.

The chip area occupied by the isolation region between traditional bulk silicon CMOS devices will increase as the device size decreases, which will bring more parasitic capacitance, which is not conducive to improving integration density and circuit speed. At the same time, various multi-dimensional nonlinear effects brought about by device size reduction will become more obvious, seriously affecting circuit performance.

Contents of the invention

The purpose of the present invention is to introduce a CMOS ring oscillator based on the silicon-on-insulator process, which fully utilizes the characteristics of the silicon-on-insulator process technology, and adopts an improved new circuit structure in the circuit design. The advantages of simplicity, low noise, and good frequency stabilization performance have good application prospects.

The purpose of the present invention is achieved like this:

The silicon-on-insulator CMOS device structure that the present invention adopts is: on insulating substrate (silicon substrate), grow one deck single crystal silicon thin film, device is just manufactured in this silicon film that surface layer is very thin, between device and substrate separated by a buried oxide layer. Taking the P tube as an example, a P-type source and drain region, an N-type channel region, and gate oxide and polysilicon gate above the N-type channel region are formed in the silicon film by means of photolithography, oxidation, deposition and ion implantation. . The two P tubes are separated by a field oxide layer. It is because of this unique structure that the silicon-on-insulator CMOS device of the present invention has advantages that cannot be compared with ordinary bulk silicon devices.

A CMOS ring oscillator based on silicon-on-insulator technology, including IN terminal, OUT terminal, power supply VDD and ground wire GND, wherein the IN terminal is the monitoring terminal, and the OUT terminal is the output terminal. The characteristics are: the silicon-on-insulator technology based The CMOS ring oscillator also includes the first MOS transistor M1, the second MOS transistor M2, the third MOS transistor M3, the fourth MOS transistor M4, the fifth MOS transistor M5, the sixth MOS transistor M6, the seventh MOS transistor M7, the eighth MOS transistor MOS tube M8, ninth MOS tube M9, tenth MOS tube M10, eleventh MOS tube M11, twelfth MOS tube M12, thirteenth MOS tube M13, fourteenth MOS tube M14, fifteenth MOS tube M15 , the sixteenth MOS tube M16, the seventeenth MOS tube M17, the eighteenth MOS tube M18, the nineteenth MOS tube M19, the twentieth MOS tube M20, the twenty-first MOS tube M21, the first capacitor C1, the The second capacitor C2, the third capacitor C3, the fourth capacitor C4, the fifth capacitor C5, the sixth capacitor C6, and the seventh capacitor C7, wherein the first MOS transistor M1, the third MOS transistor M3, the fifth MOS transistor M5, the seventh The MOS transistor M7, the ninth MOS transistor M9, the eleventh MOS transistor M11, and the thirteenth MOS transistor M13 are reinforced silicon-on-insulator (BC) PMOS transistors, the second MOS transistor M2, the fourth MOS transistor M4, the thirteenth MOS transistor M13 The sixth MOS transistor M6, the eighth MOS transistor M8, the tenth MOS transistor M10, the twelfth MOS transistor M12, and the fourteenth MOS transistor M14 are reinforced silicon-on-insulator (BC) NMOS transistors, and the fifteenth MOS transistor M15 , the sixteenth MOS tube M16, the seventeenth MOS tube M17, the eighteenth MOS tube M18, the nineteenth MOS tube M19, the twentieth MOS tube M20, and the twenty-first MOS tube M21 are depletion silicon-on-insulator Floating body (FB) NMOS tube.

A circuit connection of a CMOS ring oscillator based on a silicon-on-insulator process, the gate and drain of the first MOS transistor M1 and the second MOS transistor M2 are respectively connected together, the source of the first MOS transistor M1 is connected to a power supply, and the second MOS transistor M1 is connected to the power supply. The source of the second MOS transistor M2 is connected to the drain of the fifteenth MOS transistor M15, the source and gate of the fifteenth MOS transistor M15 are connected together and then grounded, the first MOS transistor M1, the second MOS transistor M2, the Fifteen MOS transistors M15 constitute the first stage (stage1) of the ring oscillator; the gate and drain of the third MOS transistor M3 and the fourth MOS transistor M4 are respectively connected together, and the source of the third MOS transistor M3 is connected to the power supply , the source of the fourth MOS transistor M4 is connected to the drain of the sixteenth MOS transistor M16, the source and the gate of the sixteenth MOS transistor M16 are connected together and then grounded, the third MOS transistor M3, the fourth MOS transistor M4 1. The sixteenth MOS transistor M16 constitutes the second stage (stage2) of the ring oscillator; the gate and drain of the fifth MOS transistor M5 and the sixth MOS transistor M6 are respectively connected together, and the source of the fifth MOS transistor M5 is connected to Power supply connection, the source of the sixth MOS transistor M6 is connected to the drain of the seventeenth MOS transistor M17, the source and gate of the seventeenth MOS transistor M17 are connected together and then grounded, the fifth MOS transistor M5, the sixth MOS transistor The transistor M6 and the seventeenth MOS transistor M17 constitute the third stage (stage3) of the ring oscillator; the gate and drain of the seventh MOS transistor M7 and the eighth MOS transistor M8 are respectively connected together, and the source of the seventh MOS transistor M7 pole is connected to the power supply, the source of the eighth MOS transistor M8 is connected to the drain of the eighteenth MOS transistor M18, the source and gate of the eighteenth MOS transistor M18 are connected together and grounded, the seventh MOS transistor M7, the eighth MOS transistor M18 The eighth MOS transistor M8 and the eighteenth MOS transistor M18 constitute the fourth stage (stage4) of the ring oscillator; the gate and drain of the ninth MOS transistor M9 and the tenth MOS transistor M10 are respectively connected together, and the ninth MOS transistor M9 The source of the tenth MOS transistor M1O is connected to the drain of the nineteenth MOS transistor M19, the source and gate of the nineteenth MOS transistor M19 are connected together and grounded, and the ninth MOS transistor M9 , the tenth MOS transistor M10, and the nineteenth MOS transistor M15 constitute the fifth stage (stage5) of the ring oscillator; the grid and drain of the eleventh MOS transistor M11 and the twelfth MOS transistor M12 are respectively connected together, The source of the eleventh MOS transistor M11 is connected to the power supply, the source of the twelfth MOS transistor M12 is connected to the drain of the twentieth MOS transistor M20, and the source and gate of the twentieth MOS transistor M20 are connected together Grounded, the eleventh MOS transistor M11, the twelfth MOS transistor M12, and the twentieth MOS transistor M20 constitute the sixth stage (stage6) of the ring oscillator, and the gates of the thirteenth MOS transistor M13 and the fourteenth MOS transistor M14 and the drain are respectively connected together, the source of the thirteenth MOS tube M13 is connected to the power supply, and the source of the fourteenth MOS tube M14 The source is connected to the drain of the twenty-first MOS transistor M21, the source and the gate of the twenty-first MOS transistor M21 are connected together and then grounded, the thirteenth MOS transistor M13, the fourteenth MOS transistor M14, the second Eleven MOS tubes M21 constitute the seventh stage (stage7) of the ring oscillator.

The silicon-on-insulator process technology (silicon-insulator CMOS device structure) adopted in the present invention is particularly suitable for ring oscillator applications, because its unique high-resistance substrate and buried oxide layer can significantly reduce crosstalk and minimize parasitic capacitance, Better shield the substrate noise. At the same time, on the basis of the original traditional ring oscillator structure, the source of the NMOS tube is connected to the depletion-type silicon-on-insulator floating body (FB) NMOS tube, and the special device structure that uses the floating body tube body area to float, Improved rise time vs. supply voltage and improved frequency output vs. supply voltage dependence to better provide a stable frequency output.

The present invention can realize a high-performance ring oscillator through a simple circuit structure based on a silicon-on-insulator CMOS process. Compared with a traditional bulk silicon CMOS ring oscillator, the present invention has the advantage that a 0.6 μm silicon-on-insulator CMOS is now used The ring oscillator manufactured by the process is illustrated as an example.

(1), the present invention improves the rising edge time due to the adoption of silicon-on-insulator CMOS technology. When the power supply voltage is VDD, the charging time is T seconds, and the rising edge time can be improved as:

${\mathrm{<span\; class="notranslate">\; T</span>}}_{\mathrm{<span\; class="notranslate">\; r</span>}}<span\; class="notranslate">\; =</span>\frac{\mathrm{<span\; class="notranslate">\; 2</span>}\mathrm{<span\; class="notranslate">\; C</span>}<span\; class="notranslate">\; \&CenterDot;</span>{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; dd</span>}}}{<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; W</span>}<span\; class="notranslate">\; /</span>\mathrm{<span\; class="notranslate">\; L</span>}<span\; class="notranslate">\; )</span>{\mathrm{<span\; class="notranslate">\; K</span>}}_{\mathrm{<span\; class="notranslate">\; p</span>}}{<span\; class="notranslate">\; (</span>{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; dd</span>}}<span\; class="notranslate">\; -</span><span\; class="notranslate">\; |</span>{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; the\; th</span>}}<span\; class="notranslate">\; |</span><span\; class="notranslate">\; )</span>}^{\mathrm{<span\; class="notranslate">\; 2</span>}}}<span\; class="notranslate">\; ,</span>$

It can be seen that as the power supply voltage increases, the rise time gradually decreases;

(2), the present invention has improved the falling time due to the adoption of silicon-on-insulator CMOS technology. In the discharge process, because the depletion type NMOS tube is a floating body tube and is in a saturated state, it is equivalent to a current source tube, that is, the discharge current is basically Determined by the saturation current of the silicon floating body (FB) NMOS tube on the insulator, the discharge time can be estimated to be a relatively constant amount, which is greatly improved compared with the discharge time of the traditional bulk silicon ring oscillator;

(3), the present invention owing to adopt silicon-on-insulator CMOS process, oscillation period can be written as:

$\mathrm{<span\; class="notranslate">\; f</span>}<span\; class="notranslate">\; =</span>\mathrm{<span\; class="notranslate">\; 1</span>}<span\; class="notranslate">\; /</span>\mathrm{<span\; class="notranslate">\; T</span>}<span\; class="notranslate">\; =</span>\frac{\mathrm{<span\; class="notranslate">\; 2</span>}}{\mathrm{<span\; class="notranslate">\; N</span>}<span\; class="notranslate">\; \&CenterDot;</span><span\; class="notranslate">\; (</span>{\mathrm{<span\; class="notranslate">\; T</span>}}_{\mathrm{<span\; class="notranslate">\; r</span>}}<span\; class="notranslate">\; +</span>{\mathrm{<span\; class="notranslate">\; T</span>}}_{\mathrm{<span\; class="notranslate">\; f</span>}}<span\; class="notranslate">\; )</span>}<span\; class="notranslate">\; =</span>\frac{\mathrm{<span\; class="notranslate">\; 1</span>}}{\mathrm{<span\; class="notranslate">\; NC</span>}<span\; class="notranslate">\; (</span>\frac{\mathrm{<span\; class="notranslate">\; 1</span>}}{\mathrm{<span\; class="notranslate">\; \&beta;</span>}\frac{{{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; the\; th</span>}}}^{\mathrm{<span\; class="notranslate">\; 2</span>}}}{{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; dd</span>}}}<span\; class="notranslate">\; +</span>\frac{\mathrm{<span\; class="notranslate">\; Vdd</span>}}{\mathrm{<span\; class="notranslate">\; \&beta;</span>}{{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; the\; th</span>}}}^{\mathrm{<span\; class="notranslate">\; 2</span>}}}}<span\; class="notranslate">\; )</span>}$

It can be seen that the oscillation frequency has the most stable frequency output under a specific power supply voltage Vdd, that is, a stable frequency quantity is obtained.

Description of drawings

Figure 1 is a circuit topology diagram of a traditional silicon-on-insulator CMOS process ring oscillator

Figure 2 is a cross-sectional view of a traditional silicon-on-insulator CMOS process device

Fig. 3 is a cross-sectional view of the silicon-on-insulator CMOS process device of the present invention

Fig. 4 is the circuit diagram of the present invention

Fig. 5 is the CMOS ring oscillator chip diagram based on silicon-on-insulator technology of the present invention

Fig. 6 is the frequency output stabilization curve of the present invention

Detailed ways

The technical solution of the present invention is a specific embodiment, and will not be repeated here. Describe the working process of the present invention in detail below.

Referring to Figure 4, when the IN terminal is at a high level and the power supply voltage starts to supply power, the first MOS transistor M1 and the second

The inverter composed of the MOS transistor M2 outputs a low level, that is, the phase inversion is completed through the first stage (stage 1); at the same time, the inverter composed of the third MOS transistor M3 and the fourth MOS transistor M4 outputs a high level, that is, The inversion is completed through the second stage (stage2); the inverter formed by the fifth MOS transistor M5 and the sixth MOS transistor M6 outputs a low level, that is, the inversion is completed through the third stage (stage3); the seventh MOS transistor M7 and the The inverter composed of the eighth MOS transistor M8 outputs a high level, that is, the phase inversion is completed through the fourth stage (stage4); the inverter composed of the ninth MOS transistor M9 and the tenth MOS transistor M10 outputs a high level, that is, through The fifth stage (stage5) completes the inversion; the inverter composed of the eleventh MOS transistor M11 and the twelfth MOS transistor M12 outputs a low level, that is, the sixth stage (stage6) completes the inversion; the thirteenth MOS transistor The inverter formed by M13 and the fourteenth MOS transistor M14 outputs a low level, that is, completes the inversion through the seventh stage (stage7); and finally feeds back to the input terminal IN through the OUT terminal, and pulls it to a low level.

According to Backhouse's criterion:

|H(jω ₀ )|≥1

∠H(jω ₀ )＝180°

The loop gain can be approximately equal to

$<span\; class="notranslate">\; |</span>\mathrm{<span\; class="notranslate">\; h</span>}<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; j</span>}{\mathrm{<span\; class="notranslate">\; \&omega;</span>}}_{\mathrm{<span\; class="notranslate">\; 0</span>}}<span\; class="notranslate">\; )</span><span\; class="notranslate">\; |</span><span\; class="notranslate">\; =</span>\frac{<span\; class="notranslate">\; -</span>{\mathrm{<span\; class="notranslate">\; A</span>}}_{\mathrm{<span\; class="notranslate">\; 0</span>}}^{\mathrm{<span\; class="notranslate">\; 7</span>}}}{{<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 1</span>}<span\; class="notranslate">\; +</span>\frac{\mathrm{<span\; class="notranslate">\; j</span>}{\mathrm{<span\; class="notranslate">\; \&omega;</span>}}_{\mathrm{<span\; class="notranslate">\; 0</span>}}}{{\mathrm{<span\; class="notranslate">\; \&omega;</span>}}_{\mathrm{<span\; class="notranslate">\; c</span>}}}<span\; class="notranslate">\; )</span>}^{\mathrm{<span\; class="notranslate">\; 7</span>}}}$

The phase shift is about 26 degrees per stage.

The component parameters in the present invention are: the size of the reinforced silicon-on-insulator (BC) NMOS tube is 4/0.6 μm, the size of the reinforced silicon-on-insulator (BC) PMOS tube is 8/0.6 μm, and the size of the depleted silicon-on-insulator (BC) is 8/0.6 μm. Silicon floating body (FB) NMOS tube size is 2/0.6μm.

The specific data of the silicon-on-insulator process based on the present invention are as shown in Table 1:

Table 1

Specification Parameters and definitions Exhaustion mode Partially depleted (PD-SOI) crystal direction <100> Feature size 0.18μm Silicon layer thickness 145nm Buried oxide layer thickness 1000nm Substrate resistivity 1Kohm.cm Top Metal Thickness 4μm

The ring oscillator of the invention is suitable for the front-end application of the 900MHz UHF RFID radio frequency identification receiver.

Claims (1)

1. CMOS ring oscillator based on silicon-on-insulator process, this oscillator contains the IN end, the OUT end, power vd D and ground wire GND, wherein the IN end is the monitoring side, the OUT end is output, it is characterized in that, this oscillator also contains the first metal-oxide-semiconductor M1, the second metal-oxide-semiconductor M2, the 3rd metal-oxide-semiconductor M3, the 4th metal-oxide-semiconductor M4, the 5th metal-oxide-semiconductor M5, the 6th metal-oxide-semiconductor M6, the 7th metal-oxide-semiconductor M7, the 8th metal-oxide-semiconductor M8, the 9th metal-oxide-semiconductor M9, the tenth metal-oxide-semiconductor M10, the 11 metal-oxide-semiconductor M11, the 12 metal-oxide-semiconductor M12, the 13 metal-oxide-semiconductor M13, the 14 metal-oxide-semiconductor M14, the 15 metal-oxide-semiconductor M15, the 16 metal-oxide-semiconductor M16, the 17 metal-oxide-semiconductor M17, the 18 metal-oxide-semiconductor M18, the 19 metal-oxide-semiconductor M19, the 20 metal-oxide-semiconductor M20, the 21 metal-oxide-semiconductor M21, first capacitor C 1, second capacitor C 2, the 3rd capacitor C 3, the 4th capacitor C 4, the 5th capacitor C 5, the 6th capacitor C 6, the 7th capacitor C 7, the wherein first metal-oxide-semiconductor M1, the 3rd metal-oxide-semiconductor M3, the 5th metal-oxide-semiconductor M5, the 7th metal-oxide-semiconductor M7, the 9th metal-oxide-semiconductor M9, the 11 metal-oxide-semiconductor M11, the 13 metal-oxide-semiconductor M13 is that the silicon body connects (BC) PMOS pipe on the reinforced insulation body; The second metal-oxide-semiconductor M2, the 4th metal-oxide-semiconductor M4, the 6th metal-oxide-semiconductor M6, the 8th metal-oxide-semiconductor M8, the tenth metal-oxide-semiconductor M10, the 12 metal-oxide-semiconductor M12, the 14 metal-oxide-semiconductor M14 are that the silicon body connects (BC) NMOS pipe on the reinforced insulation body; The 15 metal-oxide-semiconductor M15, the 16 metal-oxide-semiconductor M16, the 17 metal-oxide-semiconductor M17, the 18 metal-oxide-semiconductor M18, the 19 metal-oxide-semiconductor M19, the 20 metal-oxide-semiconductor M20, the 21 metal-oxide-semiconductor M21 are depleted silicon on insulator buoyancy aid (FB) NMOS pipe; The physical circuit form is: input IN links to each other with the grid of the first metal-oxide-semiconductor M1, the first metal-oxide-semiconductor M1 is connected to the second metal-oxide-semiconductor M2 grid, drain electrode, the source electrode of the first metal-oxide-semiconductor M1 is connected with power supply, the source electrode of the second metal-oxide-semiconductor M2 is connected with the drain electrode of the 15 metal-oxide-semiconductor M15, ground connection after the source electrode of the 15 metal-oxide-semiconductor M15 and grid link together, the first metal-oxide-semiconductor M1, the second metal-oxide-semiconductor M2, the 15 metal-oxide-semiconductor M15 have constituted the first order (stage1) of ring oscillator; The 3rd metal-oxide-semiconductor M3 is connected to the 4th metal-oxide-semiconductor M4 grid, drain electrode, the source electrode of the 3rd metal-oxide-semiconductor M3 is connected with power supply, the source electrode of the 4th metal-oxide-semiconductor M4 is connected with the drain electrode of the 16 metal-oxide-semiconductor M16, ground connection after the source electrode of the 16 metal-oxide-semiconductor M16 and grid link together, the 3rd metal-oxide-semiconductor M3, the 4th metal-oxide-semiconductor M4, the 16 metal-oxide-semiconductor M16 have constituted the second level (stage2) of ring oscillator; The 5th metal-oxide-semiconductor M5 is connected to the 6th metal-oxide-semiconductor M6 grid, drain electrode, the source electrode of the 5th metal-oxide-semiconductor M5 is connected with power supply, the source electrode of the 6th metal-oxide-semiconductor M6 is connected with the drain electrode of the 17 metal-oxide-semiconductor M17, ground connection after the source electrode of the 17 metal-oxide-semiconductor M17 and grid link together, the 5th metal-oxide-semiconductor M5, the 6th metal-oxide-semiconductor M6, the 17 metal-oxide-semiconductor M17 have constituted the third level (stage3) of ring oscillator; The 7th metal-oxide-semiconductor M7 is connected to the 8th metal-oxide-semiconductor M8 grid, drain electrode, the source electrode of the 7th metal-oxide-semiconductor M7 is connected with power supply, the source electrode of the 8th metal-oxide-semiconductor M8 is connected with the drain electrode of the 18 metal-oxide-semiconductor M18, ground connection after the source electrode of the 18 metal-oxide-semiconductor M18 and grid link together, the 7th metal-oxide-semiconductor M7, the 8th metal-oxide-semiconductor M8, the 18 metal-oxide-semiconductor M18 have constituted the fourth stage (stage4) of ring oscillator; The 9th metal-oxide-semiconductor M9 is connected to the tenth metal-oxide-semiconductor M10 grid, drain electrode, the source electrode of the 9th metal-oxide-semiconductor M9 is connected with power supply, the source electrode of the tenth metal-oxide-semiconductor M10 is connected with the drain electrode of the 19 metal-oxide-semiconductor M19, ground connection after the source electrode of the 19 metal-oxide-semiconductor M19 and grid link together, the 9th metal-oxide-semiconductor M9, the tenth metal-oxide-semiconductor M10, the 19 metal-oxide-semiconductor M19 have constituted the level V (stage5) of ring oscillator; The 11 metal-oxide-semiconductor M11 is connected to the 12 metal-oxide-semiconductor M12 grid, drain electrode, the source electrode of the 11 metal-oxide-semiconductor M11 is connected with power supply, the source electrode of the 12 metal-oxide-semiconductor M12 is connected with the drain electrode of the 20 metal-oxide-semiconductor M20, ground connection after the source electrode of the 20 metal-oxide-semiconductor M20 and grid link together, the 11 metal-oxide-semiconductor M11, the 12 metal-oxide-semiconductor M12, the 20 metal-oxide-semiconductor M20 have constituted the 6th grade (stage6) of ring oscillator; The 13 metal-oxide-semiconductor M13 is connected to the 14 metal-oxide-semiconductor M14 grid, drain electrode, the source electrode of the 13 metal-oxide-semiconductor M13 is connected with power supply, the source electrode of the 14 metal-oxide-semiconductor M14 is connected with the drain electrode of the 21 metal-oxide-semiconductor M21, ground connection after the source electrode of the 21 metal-oxide-semiconductor M21 and grid link together, the 13 metal-oxide-semiconductor M13, the 14 metal-oxide-semiconductor M14, the 21 metal-oxide-semiconductor M21 have constituted the 7th grade (stage7) of ring oscillator; Output OUT links to each other with the drain electrode of the 13 metal-oxide-semiconductor M13; One end of first capacitor C 1 is connected with the drain electrode of the first metal-oxide-semiconductor M1, the other end ground connection of first capacitor C 1; One end of second capacitor C 2 is connected with the drain electrode of the 3rd metal-oxide-semiconductor M3, the other end ground connection of second capacitor C 2; One end of the 3rd capacitor C 3 is connected with the drain electrode of the 5th metal-oxide-semiconductor M5, the other end ground connection of the 3rd capacitor C 3; One end of the 4th capacitor C 4 is connected with the drain electrode of the 7th metal-oxide-semiconductor M7, the other end ground connection of the 4th capacitor C 4; One end of the 5th capacitor C 5 is connected with the drain electrode of the 9th metal-oxide-semiconductor M9, the other end ground connection of the 5th capacitor C 5; One end of the 6th capacitor C 6 is connected with the drain electrode of the 11 metal-oxide-semiconductor M11, the other end ground connection of the 6th capacitor C 6; One end of the 7th capacitor C 7 is connected with output OUT, the other end ground connection of the 7th capacitor C 7; Output OUT links to each other with input IN.

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