CN101814321A - Memory power gating circuit and method - Google Patents
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Abstract
A kind of memory power gating circuit, be configured to be connected to memory array with builtin voltage, wherein, this power gating circuit comprises the circuit with output signal, this output signal is lower than the builtin voltage of rising memory array under the first threshold voltage condition and is higher than at builtin voltage under the situation of second threshold voltage at builtin voltage and reduces builtin voltage, thereby builtin voltage is remained between the first threshold voltage and second threshold voltage.The present invention also provides the method for the data of the memory array that a kind of maintenance has builtin voltage.
Description
The cross reference of related application
The application requires the right of priority of No. the 61/154th, 744, the U. S. application submitted on February 23rd, 2009, and its application is hereby expressly incorporated by reference.
Technical field
Present invention relates in general to field of semiconductor devices, more specifically, relate to the apparatus and method of the power supply requirement that is used for control store.
Background technology
Development has fast been experienced in SIC (semiconductor integrated circuit) (IC) industry.The technical progress of IC material and design has produced many for IC, and wherein, each Dai Jun has than last Dai Gengxiao and more complicated circuit.The IC technology scales is contracted to the nanometer state has increased power dissipation.The power dissipation that is increased causes some problems, comprises the battery life that shortens in the mobile system, expensive encapsulation and cooling scheme, and can cause failure of chip.In causing the multiple factor of power dissipation, the power dissipation or the static power dissipation that are caused by leakage constantly increase, and are expected in the near future and can dissipate above dynamic power.
The Passive Power gating helps to reduce the power dissipation in the storer.Traditional power gating circuit is made of the head driver that is connected to head (header), and this head is made of a plurality of transistors.During aggressive mode, the transistor of head driver conducting head is to provide drive current to storer.During deep power down mode, head driver ends the transistor of head.During keeping data mode, the transistor of head plays the function of diode, and the head driver oxide-semiconductor control transistors is to keep lower internal power source voltage level.
Summary of the invention
In at least one embodiment, the memory array with builtin voltage is connected to power gating circuit (power gating circuit, power gating circuit).The power gating circuit reduces builtin voltage under the situation of second threshold voltage and builtin voltage is remained between the first threshold voltage and second threshold voltage by being lower than rising builtin voltage under the first threshold voltage condition at builtin voltage and being higher than at builtin voltage.
In at least one embodiment, the data maintenance method with memory array of builtin voltage comprises: the builtin voltage of detection of stored device array; And be lower than rising builtin voltage under the first threshold voltage condition and be higher than at builtin voltage under the situation of second threshold voltage different at builtin voltage and reduce builtin voltage, thereby builtin voltage is remained between the first threshold voltage and second threshold voltage with first threshold voltage.
Will in conjunction with hereinafter and accompanying drawing these and other embodiment and feature thereof are described in further detail.
Description of drawings
When reading in conjunction with the accompanying drawings, the present invention may be better understood according to the following detailed description.Should be emphasized that according to the standard practices in the industry, various parts are not drawn in proportion and only are used for illustrative purposes.In fact, in order clearly to discuss, the quantity of various parts and size can be increased arbitrarily or be reduced.
Fig. 1 is the synoptic diagram that the exemplary power gating circuit that is connected with memory array is shown.
Fig. 2 is the synoptic diagram that the exemplary comparator circuit is shown.
Fig. 3 is the V that the output signal and the memory array of comparator circuit are shown
InternalBetween the synoptic diagram of hysteresis (hysteresis) relation.
Fig. 4 is the synoptic diagram that another example memory that comprises the power gating circuit is shown, and this power gating circuit has fin formula multi-gated transistor (FinFET).
Fig. 5 is the synoptic diagram that the memory array that is connected with the exemplary power gating circuit that comprises finite state machine is shown.
Fig. 6 be illustrate with comprise finite state machine the synoptic diagram of the memory array that is connected of another exemplary power gating circuit.
Fig. 7 is the synoptic diagram that the exemplary power gating circuit that is connected with memory array is shown.
Fig. 8 is the V that the output signal and the memory array of comparator circuit are shown
InternalBetween the synoptic diagram of lagged relationship.
Fig. 9 is the synoptic diagram that another exemplary power gating circuit that is connected with memory array is shown.
Embodiment
During the keeping data mode of memory array, the transistor of head plays the function of diode.Transistorized diode current is very little, and therefore, a large amount of transistors in the head are used to provide the required diode current of data message that keeps storer.Yet a large amount of transistors needs very big area, and this has increased the size of storer.As everyone knows, variation is flimsy to the conventional power gating circuit for technology-voltage-temperature (PVT).
The power dissipation that active biased method reduces storer has been proposed.Active biased method is used operational amplifier to continue monitoring and is regulated the voltage level of storer.Yet, operational amplifier need a large amount of memory area and not with in-line memory (such as, embedded static RAM) compatibility.
Should be appreciated that following disclosing provides many different embodiment or example, is used to the parts of realizing that they are different.The particular instance that parts or layout are described below is of the present invention open to simplify.Certainly, these only are examples, limit and be not used in.For example, in the following description, first parts are formed on second parts or the top can comprise that first parts and second parts directly contact the embodiment of formation, and can comprise that miscellaneous part can be formed between first parts and second parts so that the embodiment that first parts and second parts directly do not contact.In addition, the disclosure can be in different examples repeat reference numerals and/or letter.This repetition is in order to simplify and purpose clearly, and is not the relation between described different embodiment of perfect representation and/or the configuration.
Embodiment relate to power gating circuit and integrated circuit (such as, driver, storer, other circuit that comprise memory array and/or their combination) operation method.The power gating circuit can be storer the ring (hysteresis loop) that stagnates is provided, and is used for during the keeping data mode builtin voltage of storer being remained between two threshold voltages.
Fig. 1 shows the synoptic diagram of the exemplary power gating circuit that is connected to memory array.In Fig. 1, system 100 comprises the power gating circuit 110 that is connected to memory array 120.In certain embodiments, system 100 is storer (for example, DRAM, SRAM, embedded DRAM and/or embedded SRAM), driver, other integrated circuit and/or their combination.In certain embodiments, memory array 120 be connected to external power source (such as, ground or VSS).Memory array 120 comprises array matrix 121, and has the builtin voltage (V that voltage is provided to array matrix 121
Internal).In an embodiment, builtin voltage (V
Internal) be virtual CVDD (storage core power supply voltage).
In an embodiment, power gating circuit 110 comprises at least one first switch, such as the head 111 with the first end 111a and second end 111b.In certain embodiments, the first end 111a of head 111 is connected to the V of memory array 120
InternalThe second end 111b of head 111 is connected to outer power voltage (such as, the external power source CVDD of memory array 120), thereby to system's 100 power supplies.In an embodiment, head 111 comprises the transistor of a plurality of parallel connections, such as P-type mos FET (PMOSFET).Parallel transistor is connected with memory array 120 and working current is offered memory array 120.During keeping data mode, the transistor of head 111 is as diode.
In at least some embodiment, at least one second switch 113 is connected to head 111.The first end 113a of second switch 113 is connected to the first end 111a of head 111.The second end 113b of second switch 113 is connected to the second end 111b of head 111.In an embodiment, switch 113 is digital switch, analog switch, relay, other electronic switch and/or their combination.In other embodiments, switch 113 comprises at least one transistor, such as field effect transistor (FET).In an embodiment, switch 113 comprises at least one PMOSFET.In other embodiments, switch 113 comprises the PMOSFET that is connected to NMOSFET.
In certain embodiments, comparator circuit 115 is connected with switch 113.The input end 115a of comparator circuit 115 is connected to the first end 113a of switch 113, and the input end 115b of comparator circuit 115 is connected to switch 113.The V of comparator circuit 115 detection of stored device arrays 120
Internal, to generate output signal.Comparator circuit 115 and switch 113 are configured to the V to memory array 120
InternalFeedback loop is provided.In an embodiment, switch 113 comprises PMOSFET.
In an embodiment, comparator circuit 115 is other circuit of Schmidt trigger or the positive feedback that is provided for switch 113 control.Fig. 2 is the synoptic diagram of exemplary comparator circuit.In Fig. 2, comparator circuit 115 is Schmidt triggers.Comparator circuit 115 comprises the V that is connected to memory array 120
Internal Input end 115a (as shown in Figure 1) and the output terminal 115b (as shown in Figure 1) that is connected to switch 113.In an embodiment, comparator circuit 115 comprises PMOSFET 211,213,215 and 217 and NMOSFET 221,223,225 and 227.Notice that the configuration of transistorized quantity and comparer 115 only is exemplary.Based on embodiment, those of ordinary skills can change comparator circuit 115 and/or use other circuit to provide the digital feedback of switch 113 is controlled.
Following description is about keeping the V of memory array 120 during storer maintenance pattern
InternalIn order to keep the data of memory array 120, power gating circuit 110 provides hysteresis, with at V
InternalBe lower than the V of rising memory array 120 under the first threshold voltage condition
InternalAnd at V
InternalThe V that is higher than the situation decline low memory array 120 of second threshold voltage
Internal Power gating circuit 110 is with the V of memory array 120
InternalRemain between the first threshold voltage and second threshold voltage.
Fig. 3 is the V that the output signal and the memory array of comparator circuit are shown
InternalBetween the synoptic diagram of lagged relationship.With reference to Fig. 1 and Fig. 3, the V of the input end 115a monitoring memory array 120 of comparator circuit 115
Internal System 100 be transformed into from " A " " B " during, comparator circuit 115 generates output signal " 1 " at output terminal 115b.Output signal " 1 " cut-off switch 113.Locate at " B ", if determine V
InternalBe lower than first threshold voltage (such as, the data sustaining voltage (DRV) of the memory cell of array matrix 121), then comparator circuit 115 is in output terminal 115b output signal " 0 ", thereby connects switch 113, the V that provides the expectation magnitude of current from CVDD to raise memory array 120
InternalAnd system 100 is transformed into " C " from " B ".If system 100 is transformed into " D " from " C ", comparator circuit 115 holding signals " 0 " then are to connect switch 113." D " locates at state, if the V of memory array 120
InternalBe higher than second threshold voltage (for example, DRV+ Δ V), the signal " 1 " of comparator circuit 115 output cut-off switch 113 then changes to " A " with the state of system 100 from " D ".Δ V is the amount with the voltage difference of DRV, and is any suitable value.Those of ordinary skills can use different Δ V to realize different results.
Notice that during keeping data mode, the PMOSFET of switch 113 provides the electric current that produces than the transistor by head 111 the high electric current of at least one order of magnitude approximately.The PMOSFET of switch 113 is configured to the V with memory array 120
InternalBecome greater than the transistor of head 111.By using the PMOSFET of switch 113, keep V
InternalThe number of transistors of the required head 111 of state and the area of head 111 also reduced.For example, traditional 32M storer has the traditional head that is connected to the 32M memory array.The tradition head has 32,768 transistors, is used to the state that working current is provided and keeps the builtin voltage of 32M memory array.In one embodiment, said system 100 comprises the memory array 120 of power gating circuit 110 and 32M.Power gating circuit 110 comprises the switch 113 that further has 16,384 transistorized heads 111 and have 4 PMOSFET.Thereby, half that transistorized quantity is traditional head in the head 111, and the area of head 111 be traditional head pact half.In addition, system 100 even change in the poorest technology-voltage-temperature (PVT) under the situation of (such as FF/SS/0.9V/-40 ℃) moves in design specifications.
Fig. 4 is the synoptic diagram that another exemplary storage device that comprises the power gating circuit with FinFET is shown.In Fig. 4, system 400 comprises the power gating circuit 410 that is connected to memory array 420.Memory array 420 comprises array matrix 421 and has builtin voltage V
InternalRepresent by identical reference number with Fig. 1 components identical among Fig. 4 that just the reference number number has increased by 300.
In an embodiment, head 412 comprises the FinFET with preceding grid 412a and back of the body grid 412b.Preceding grid 412a receives the control signal (such as the data holding signal) from driver.Back of the body grid 412b is connected to the output terminal 415b of comparator circuit 415, and control ratio makes the electric current by back of the body grid 412b control can raise or reduce the V of memory array 420 by the electric current of the high at least order of magnitude of electric current of preceding grid 412a control
Internal
The following open V that during storer maintenance pattern, keeps memory array 420 that described
InternalAn embodiment of apparatus and method.In order to keep the data of memory array 420, power gating circuit 410 provides hysteresis, with at V
InternalBe lower than the V of rising memory array 420 under the first threshold voltage condition
InternalAnd at V
InternalThe V that is higher than the situation decline low memory array 420 of second threshold voltage
Internal Power gating circuit 410 is with the V of memory array 420
InternalRemain between the first threshold voltage and second threshold voltage.
With reference to Fig. 3 and Fig. 4, the V of the input end 415a detection of stored device array 420 of comparator circuit 415
InternalThe running status of supposing the system 400 is transformed into " B " (as shown in Figure 3) from " A ", and then in the time period of A to B, comparator circuit 415 is in output terminal 415b output signal " 1 ".Output signal " 1 " is applied in the back of the body grid 412b to head 412, to disconnect the current path by back of the body grid 412b control.In state " B ", if determine V
Internal(for example, DRV), then comparator circuit 415 is in output terminal 415b output signal " 0 ", to connect the current path by back of the body grid 412b control to be lower than first threshold voltage.Current path by back of the body grid 412b control is configured to provide the magnitude of current of expectation and the V of the memory array 420 that raises from CVDD
InternalThe state of system 400 changes to " C " (as shown in Figure 3) from " B ".If the running status of system 400 changes to " D " from " C ", then comparator circuit 415 keeps output signal " 0 " with conducting back of the body grid 412b.In state " D ", if determine the V of memory array 420
InternalBe higher than second threshold voltage (for example, DRV+ Δ V), then comparator circuit 415 outputs are used for the turn-off current path by the signal " 1 " of back of the body grid 412b.The state of system 400 changes to " A " from " D ".
Notice that the system 400 of Fig. 4 comprises power gating circuit 410, it uses FinFET to provide working current to memory array 420.Compare with the power gating circuit 110 of Fig. 1, power gating circuit 410 does not comprise switch 113, has further reduced the area of head 412.In other embodiments, power gating circuit 410 comprises the switch such as switch 113, to realize the feedback compensation or the hysteresis of expectation.
Fig. 5 is the synoptic diagram that the memory array that is connected to the exemplary power gating circuit that comprises finite state machine is shown.Represent by identical reference number with Fig. 1 components identical among Fig. 5 that just the reference number number has increased by 400.In Fig. 5, power gating circuit 510 comprises the finite state machine 530 that is connected between comparator circuit 515 and the switch 513.Finite state machine 530 from comparator circuit 515 receive output signals and generate subsequently and have a plurality of states (such as, 4,8,16 or more) signal.The operation of multimode output signal gauge tap 513 is to provide feedback loop or lag compensation.Those of ordinary skills can select the number of states of finite state machine 530, to realize the expectation lag compensation to system 400.
Fig. 6 shows the synoptic diagram of the memory array that is connected to another exemplary power gating circuit that comprises finite state machine.Represent by identical reference number with Fig. 4 components identical among Fig. 6 that just the reference number number has increased by 200.In Fig. 6, finite state machine 630 is connected between the back of the body grid 612b and comparator circuit 615 of FinFET.Finite state machine 630 from comparator circuit 615 receive output signals and have subsequently a plurality of states (such as, 4,8,16 or more) signal.The operation of the back of the body grid of multimode output signal control FinFET is to provide feedback loop or lag compensation.Those of ordinary skills can select the number of states of finite state machine 630, to realize the expectation lag compensation to system 600.
Fig. 7 is the synoptic diagram that the system 700 that comprises the exemplary power gating circuit that is connected to memory array is shown.Represent by identical reference number with Fig. 1 components identical among Fig. 7 that just the reference number number has increased by 600.System 700 comprises the power gating circuit 710 that is connected to memory array 720.In Fig. 7, power gating circuit 710 comprises at least one switch, such as the foot (footer) 712 with the first end 712a and second end 712b.The first end 712a is connected to the first end 713a of switch 713, and the second end 712b is connected to second end of switch 713.In an embodiment, switch 713 is NMOSFET.
Following description is the exemplary operation of system 700 during the data hold mode.Fig. 8 is the V that the output signal and the memory array of comparator circuit are shown
InternalBetween the synoptic diagram of lagged relationship.With reference to Fig. 7 and Fig. 8, the V of the input end 715a monitoring memory array 720 of comparator circuit 715
InternalIn an embodiment, builtin voltage (V
Internal) be virtual VSS (V_VSS).System 700 be transformed into from " E " " F " during, comparator circuit 715 generates output signal " 1 " at output terminal 715b, it connects switch 113.In state " F ", if determine V
InternalBe lower than first threshold voltage (such as, CVDD-DRV-Δ V), the signal " 0 " of comparator circuit 715 output cut-off switch 113 then is to keep or the V of rising memory array 720
InternalSubsequently, the state of system 700 is transformed into " G " from " F ".If the running status of system 700 is changed into " H " from " G ", then comparator circuit 715 keeps output signal " 0 ", with cut-off switch 713.In state " H ", if the V of memory array 720
Internal(for example, CVDD-DRV), then the signal " 1 " of switches 713 is connected in comparator circuit 715 output, and the state of system 700 is changed to " E " from " H " to be higher than second threshold voltage.In an embodiment, power gating circuit 710 comprises finite state machine 530 as shown in Figure 5.Finite state machine is connected between comparator circuit 715 and the switch 712, with a plurality of states of generation for switch 713, thereby provides the feedback loop compensation.
Fig. 9 is the synoptic diagram that another exemplary power gating circuit that is connected to memory array is shown.Represent by identical reference number with Fig. 4 components identical among Fig. 9 that just the reference number number has increased by 500.In Fig. 9, system 900 comprises the power gating circuit 910 that is connected to memory array 920.In an embodiment, power gating circuit 910 comprises at least one switch, such as the foot 911 that is connected to comparator circuit 915.
In an embodiment, foot 911 comprises the N type FinFET with preceding grid 911a and back of the body grid 911b.Before grid 911a receive signal from driver (such as, data holding signal).Back of the body grid 911b is connected to the output terminal 915b of comparator circuit 915, and control ratio makes the electric current by back of the body grid 911b control can raise or reduce the V of memory array 920 by the electric current of high at least one order of magnitude of electric current of preceding grid 911a control
Internal
With reference to Fig. 8 and Fig. 9, the V of the input end 915a monitoring memory array 920 of comparator circuit 915
InternalWhen the state of system 900 when " E " is transformed into " F ", comparator circuit 915 generates the output signal " 1 " of the back of the body grid 911b that imposes on head 911 at output terminal 915b during time period E-F, to connect the current path by back of the body grid 911b control.In state " F ", if determine V
InternalBe lower than first threshold voltage (for example, VCDD-DRV-Δ V), then comparator circuit 915 is in output terminal 915b output signal " 0 ".Output signal " 0 " is applied in the current path of being controlled by back of the body grid 911b with disconnection to back of the body grid 911b, thus the V of rising memory array 920
InternalThen, the state of system 900 changes to " G " from " F ".If the state of system 900 changes to " H " from " G ", then comparator circuit 915 keeps output signal " 0 " to end back of the body grid 911b.In state " H ", if determine the V of memory array 920
Internal(for example, VCDD-DRV), then the signal " 1 " of grid 911b is carried on the back in comparator circuit 915 output conductings, to reduce the V of memory array 920 to be higher than second threshold voltage
InternalThe state of system 900 changes to " E " from " H ".In at least one embodiment, power gating circuit 910 comprises finite state machine as shown in Figure 6.Finite state machine is connected between the back of the body grid 713b of comparator circuit 715 and switch 713, with a plurality of states of generation for switch 713, thereby provides the feedback loop compensation.
Note, above power gating circuit of describing in conjunction with Fig. 1 to Fig. 9 and storer all be formed on can physics and be electrically connected to printed wiring board or printed circuit board (PCB) (PCB) with in the system that forms electronic package.This electronic package can be the part of electronic system (such as, computing machine, Wireless Telecom Equipment, peripherals that computing machine is relevant, amusement equipment etc.).
Discuss the parts of some embodiment above, made those of ordinary skills' various aspects that the present invention may be better understood.It will be understood by those skilled in the art that can use at an easy rate the present invention design or change as the basis other be used to reach with here the identical purpose of the embodiment that introduces and/or realize the processing and the structure of same advantage.Those of ordinary skills should be appreciated that also this equivalent constructions does not deviate from the spirit and scope of the present invention, and under the situation that does not deviate from the spirit and scope of the present invention, can carry out multiple variation, replacement and change.
Claims (15)
1. a power gating circuit is configured to be connected to the memory array with builtin voltage, and described power gating circuit comprises:
Circuit with output signal, described output signal is lower than under the first threshold voltage condition the described builtin voltage of the described memory array that raises and is higher than at described builtin voltage under the situation of second threshold voltage at described builtin voltage and reduces described builtin voltage, thereby described builtin voltage is remained between described first threshold voltage and described second threshold voltage.
2. power gating circuit according to claim 1, wherein, described circuit provides hysteresis.
3. power gating circuit according to claim 1, wherein, described circuit comprises:
At least one first switch, first end of described at least one first switch is connected to described builtin voltage, and second end of described at least one first switch is connected to external power voltage;
Second switch, first end of described second switch is connected to first end of described at least one first switch, and second end of second switch is connected to second end of described at least one first switch; And
Comparator circuit, the input end of described comparator circuit is connected to first end of described second switch, and the output terminal of described comparator circuit is connected to described second switch, and wherein, described second switch and described comparator circuit are configured to provide feedback loop to described builtin voltage.
4. power gating circuit according to claim 3, wherein, described at least one first switch is to comprise the transistorized head of at least one P-type mos (PMOS), and described external power voltage is outer power voltage; Perhaps
Described at least one first switch is for comprising at least one transistorized foot of N type metal oxide semiconductor (NMOS), and described external power voltage is ground voltage.
5. power gating circuit according to claim 3, wherein, described second switch comprises at least one field effect transistor, described at least one field effect transistor is configured to regulate described builtin voltage to keep the data message of described memory array; Perhaps
Wherein, described comparator circuit comprises Schmidt trigger, and described Schmidt trigger is configured to detect described builtin voltage is used to control described switch with generation output signal; Perhaps
Also comprise finite state machine, be connected between described comparator circuit and the described second switch.
6. power gating circuit according to claim 1 also comprises:
At least one first switch, comprise fin formula field effect transistor (FinFET), second end that first end of described first switch is connected to described builtin voltage and described first switch is connected to external power voltage, wherein, grid and back of the body grid before described FinFET comprises, and grid can receive the data holding signal before described; And
Comparator circuit, the output terminal that the input end of described comparator circuit is connected to described builtin voltage and described comparator circuit is connected to the described back of the body grid of described FinFET, to regulate described builtin voltage, wherein, described FinFET and described comparator circuit are configured to provide feedback loop to described builtin voltage.
7. power gating circuit according to claim 6, wherein, described first switch is the head that comprises at least one P type FinFET, and described external power voltage is outer power voltage; Perhaps
Wherein, described first switch is the foot that comprises at least one N type FinFET, and described external power voltage is ground voltage; Perhaps
Also be included in the finite state machine between the described back of the body grid of described comparator circuit and described FinFET.
8. system comprises:
Memory array has builtin voltage; And
The power gating circuit, be connected to described memory array, wherein, described power gating circuit is provided at described builtin voltage and is lower than under the first threshold voltage condition and raises described builtin voltage and to be higher than the function that reduces described builtin voltage under the situation of second threshold voltage at described builtin voltage, described builtin voltage is remained between described first threshold voltage and described second threshold voltage.
9. system according to claim 8, wherein, described function is a hysteresis.
10. system according to claim 8, wherein, described power gating circuit comprises:
At least one first switch, first end of described at least one first switch is connected to described builtin voltage, and second end of described at least one first switch is connected to external power voltage;
Second switch, first end of described second switch is connected to first end of described at least one first switch, and second end of second switch is connected to second end of described at least one first switch; And
Comparator circuit, the input end of described comparator circuit is connected to first end of described second switch, and the output terminal of described comparator circuit is connected to described second switch, and wherein, described second switch and described comparator circuit are configured to provide feedback loop to described builtin voltage.
11. system according to claim 10, wherein, described second switch comprises at least one field effect transistor, and described at least one field effect transistor is configured to regulate described builtin voltage to keep the data message of described memory array; Perhaps
Wherein, described comparator circuit comprises Schmidt trigger, and described Schmidt trigger is configured to detect described builtin voltage is used to control described switch with generation output signal; Perhaps
Also comprise the finite state machine that is connected between described comparator circuit and the described second switch, and the finite state machine between the described back of the body grid of described comparator circuit and described FinFET.
12. system according to claim 8, wherein, described power gating circuit comprises:
At least one first switch, comprise fin formula field effect transistor (FinFET), second end that first end of described first switch is connected to described builtin voltage and described first switch is connected to external power voltage, wherein, grid and back of the body grid before described FinFET comprises, and grid can receive the data holding signal before described; And
Comparator circuit, the output terminal that the input end of described comparator circuit is connected to described builtin voltage and described comparator circuit is connected to the back of the body grid of described FinFET, to regulate described builtin voltage, wherein, described FinFET and described comparator circuit are configured to provide feedback loop to described builtin voltage.
13. the method for the data of a memory array that is used to keep to have builtin voltage, described method comprises:
Detect the described builtin voltage of described memory array; And
Based on detected builtin voltage, being provided at described builtin voltage is lower than under the first threshold voltage condition and raises described builtin voltage and to be higher than the function that reduces described builtin voltage under the situation of second threshold voltage at described builtin voltage, described builtin voltage is remained between described first threshold voltage and described second threshold voltage, wherein, described first threshold voltage is different from described second threshold voltage.
14. method according to claim 13, wherein, described function is a hysteresis; Perhaps
Wherein, the described function that raises or reduce the builtin voltage of described memory array comprises the current path that is switched on or switched off between described builtin voltage and the external power source, wherein, described current path can provide the electric current than high at least one order of magnitude of transistor current of head that is connected to described memory array or foot.
15. method according to claim 13 also comprises: export one of four states at least, to provide described function based on detected builtin voltage.
Applications Claiming Priority (4)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US15474409P | 2009-02-23 | 2009-02-23 | |
| US61/154,744 | 2009-02-23 | ||
| US12/707,788 | 2010-02-18 | ||
| US12/707,788 US8305829B2 (en) | 2009-02-23 | 2010-02-18 | Memory power gating circuit for controlling internal voltage of a memory array, system and method for controlling the same |
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| Publication Number | Publication Date |
|---|---|
| CN101814321A true CN101814321A (en) | 2010-08-25 |
| CN101814321B CN101814321B (en) | 2015-11-25 |
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| CN201010119548.XA Active CN101814321B (en) | 2009-02-23 | 2010-02-23 | Memory power gating circuit and method |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104810042A (en) * | 2014-01-29 | 2015-07-29 | 爱思开海力士有限公司 | System using minimum operation power and power supply voltage setting method of memory device |
| CN105393307A (en) * | 2013-05-16 | 2016-03-09 | 英特尔公司 | Low power transient voltage collapse apparatus and method for a memory cell |
| CN110648697A (en) * | 2018-06-27 | 2020-01-03 | 台湾积体电路制造股份有限公司 | Selection circuit, latch-up prevention circuit for memory storage system and method |
Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5821808A (en) * | 1995-08-25 | 1998-10-13 | Nec Corporation | Voltage circuit for preventing voltage fluctuation |
| CN1637946A (en) * | 2003-12-30 | 2005-07-13 | 海力士半导体有限公司 | Internal voltage generating circuit in semiconductor memory device |
| US20050259497A1 (en) * | 2004-05-14 | 2005-11-24 | Zmos Technology, Inc. | Internal voltage generator scheme and power management method |
| US20060091937A1 (en) * | 2004-11-04 | 2006-05-04 | Hynix Semiconductor Inc. | Internal voltage generator |
| US20070069808A1 (en) * | 2005-09-29 | 2007-03-29 | Hynix Semiconductor Inc. | Internal voltage generator |
| CN101105974A (en) * | 2006-07-14 | 2008-01-16 | 威刚科技股份有限公司 | Non-volatile memory device and control method thereof |
| US20080303494A1 (en) * | 2007-06-08 | 2008-12-11 | Fujitsu Limited | Semiconductor integrated circuit and system |
-
2010
- 2010-02-23 CN CN201010119548.XA patent/CN101814321B/en active Active
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5821808A (en) * | 1995-08-25 | 1998-10-13 | Nec Corporation | Voltage circuit for preventing voltage fluctuation |
| CN1637946A (en) * | 2003-12-30 | 2005-07-13 | 海力士半导体有限公司 | Internal voltage generating circuit in semiconductor memory device |
| US20050259497A1 (en) * | 2004-05-14 | 2005-11-24 | Zmos Technology, Inc. | Internal voltage generator scheme and power management method |
| US20060091937A1 (en) * | 2004-11-04 | 2006-05-04 | Hynix Semiconductor Inc. | Internal voltage generator |
| US20070069808A1 (en) * | 2005-09-29 | 2007-03-29 | Hynix Semiconductor Inc. | Internal voltage generator |
| CN101105974A (en) * | 2006-07-14 | 2008-01-16 | 威刚科技股份有限公司 | Non-volatile memory device and control method thereof |
| US20080303494A1 (en) * | 2007-06-08 | 2008-12-11 | Fujitsu Limited | Semiconductor integrated circuit and system |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105393307A (en) * | 2013-05-16 | 2016-03-09 | 英特尔公司 | Low power transient voltage collapse apparatus and method for a memory cell |
| CN105393307B (en) * | 2013-05-16 | 2019-05-10 | 英特尔公司 | The low-power transient voltage of memory cell collapses device and method |
| CN104810042A (en) * | 2014-01-29 | 2015-07-29 | 爱思开海力士有限公司 | System using minimum operation power and power supply voltage setting method of memory device |
| CN110648697A (en) * | 2018-06-27 | 2020-01-03 | 台湾积体电路制造股份有限公司 | Selection circuit, latch-up prevention circuit for memory storage system and method |
| US11145335B2 (en) | 2018-06-27 | 2021-10-12 | Taiwan Semiconductor Manufacturing Co., Ltd. | Latch-up prevention circuit for memory storage system |
| CN110648697B (en) * | 2018-06-27 | 2021-12-31 | 台湾积体电路制造股份有限公司 | Selection circuit, latch-up prevention circuit for memory storage system and method |
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