CN101808029B - Method and device for preloading packet header and system using method - Google Patents

Abstract

The invention relates to a method and a device for preloading a packet header and a system applying the method. The method downloads the packet header data from a main memory to a packet header register in advance before a central processing unit executes downloading of the packet header data to accelerate the processing speed of the packet header data.

Description

Method and device for packet header preloading and system using said method

technical field

The invention relates to packet processing, in particular to a method and device for packet header preloading.

Background technique

With the increasing popularity of the Internet, various applications have also developed rapidly, and many teams have also invested in the research of improving the data transmission performance of the Internet. In different usage occasions, the length of packets allowed for data transmission is not the same, and it contains a variety of packet data processing procedures, such as inspection, disassembly, combination, search, content comparison, forwarding and other procedures. With the sharp increase in the bandwidth requirements of network applications such as home networks, campus networks, and enterprise networks and the transmission of a large amount of packet data, the transmission performance of packets and the development of packet computing and processing technologies have also received increasing attention.

In network packet data applications, in order to ensure its service quality, there are some related requirements for packet transmission. For example, in VoIP applications, packet delays can cause echoes and vibrato. When the packet is delayed, the human ear can tell that there is an echo. A good network transmission environment and packet data processing performance must ensure that the packet delay is less than 150 milliseconds. The sound delay acceptable to the human ear is about 150 milliseconds to 400 milliseconds. Delays of more than 400 milliseconds can result in poor sound quality that cannot be answered. Therefore, in addition to enhancing the quality of network transmission, the transmission timing of various types of packets also needs to be properly managed. For example, the processing priority of the packets is marked according to the urgency, so that subsequent network devices can process them according to the requirements of their service characteristics.

With the continuous improvement of network transmission speed and the need to process packet information of voice transmission and multimedia transmission at the same time, in order to improve the performance of processing, various technologies and methods have been proposed. For example, SoC designers are working to increase the operating clock of the central processing unit, increase the cache memory space, or use an arithmetic processor specialized in processing packet data in the system. However, the above method also increases the cost and power consumption. Therefore, the industry needs a method that can increase the packet transmission speed in a low-cost manner.

Contents of the invention

The packet header preloading method and device of the present invention download the packet header data into a packet header register in advance before the central processing unit executes downloading of the packet header data, so as to accelerate the processing speed of the packet header data.

An embodiment of the present invention discloses a packet header preloading device, the packet header preloading device includes at least one packet detector, at least one packet header register and at least one data scheduler. The at least one packet detector is used for monitoring the action of the at least one packet direct memory access controller storing at least one packet into a main memory. The at least one data scheduler is used for reading the header data of the at least one packet from the main memory and storing it in the at least one packet header register.

Another embodiment of the present invention discloses a packet header preloading method. The method comprises the steps of: monitoring at least one packet of direct memory access controller for storing at least one packet into a main memory; downloading header data of said at least one packet into a packet header register; and if in a device If within a certain period of time, a central processing unit wishes to read the header data of the at least one packet, then the packet header register provides the header data of the at least one packet.

An embodiment of the present invention discloses a system comprising a MAC, a packet DMA controller, a central processing unit, a main memory, and a packet header preloader. The packet header preloading device monitors the action of the packet direct memory access controller storing at least one packet into a main memory, and reads in advance before the central processing unit has read the header data of the at least one packet Pick. And if the central processing unit wishes to read the header data of the packet within a set time, the header data of the packet is provided by the packet header preloading device.

Description of drawings

FIG. 1 shows a block diagram of a packet processing system according to an embodiment of the present invention;

FIG. 2 shows a block diagram of a packet header preloading device according to an embodiment of the present invention;

Fig. 3 shows the block diagram of the packet header preloading device of another embodiment of the present invention; And

FIG. 4 shows a flowchart of a packet header preloading method according to yet another embodiment of the present invention.

Detailed ways

FIG. 1 shows a block diagram of a packet processing system according to an embodiment of the present invention. Media access control (media access control, MAC) 103 provides addressing and media access control methods, so that different devices or nodes on the network can communicate on a multi-point network. When the MAC 103 receives the packet, it transmits the data to the main memory 101 via the direct memory access (DMA) controller 102 of the packet. In the embodiment of the present invention, the main memory 101 may be a dynamic random access memory, a synchronous dynamic random access memory or a dual-channel synchronous dynamic random access memory. Before the central processing unit 106 reads a packet header data from the main memory 101 to the cache memory 105, the packet header preloading device 104 completes the packet reading work in advance, and stores the packet header data to the packet header preload device 104.

FIG. 2 shows an internal block diagram of the packet header preloading device 104 . The packet header preloading device 104 includes a packet detector 201 , a location information queue 202 , a packet header register 203 , a timer 204 and a data scheduler 205 . The packet detector 201 monitors the action of the packet DMA controller 102 storing packets into the main memory 101 . When the packet detector 201 detects that a packet is stored from the DMA 102 to the main memory 101 , it stores the storage location of the packet in the main memory 101 in the location information queue 202 . The length of the location information queue 202 can be set by the user. The packet header register 203 downloads the header data of the packet into the packet header register 203 through the data scheduler 205 according to the storage location of the packet in the location information queue 202 in the main memory 101 . In the embodiment of the present invention, the packet header register 203 may be a static random access memory. After the download of the package is completed, the timer 204 sets a registration time immediately. When the central processing unit 106 wants to download the header data of the packet, it downloads directly from the packet header register 203 instead of from the main memory 101 . On the other hand, after the set registration time, if the central processing unit 106 has not read the packet header data, then clear all stored data in the packet header register 203 and the location information queue 202 . The packet detector 201 in the embodiment of the present invention may be implemented in one of software implementation, hardware implementation, and implementation on a platform embedded with a single processor or multiple processors.

FIG. 3 shows a system block diagram of a packet header preloading device according to another embodiment of the present invention. The packet header preloading device 300 includes an Ethernet port packet detector 301, a location information queue 302, a wireless LAN port packet detector 303, a location information queue 304, an Ethernet port packet header register 305, a timer 306, and a wireless LAN port packet header Register 307 , Timer 308 and Data Scheduler 309 .

The Ethernet port packet detector 301 and the WLAN port packet detector 303 respectively monitor the actions of the Ethernet port packet DMA controller 310 and the WLAN port packet DMA controller 311 storing packets in the main memory 101 . When the Ethernet port packet detector 301 detects that a packet is stored to the main memory 101 by the Ethernet port packet direct memory access controller 310, the storage location of the packet in the main memory 101 is stored in the location information queue 302 middle. The Ethernet port packet header register 305 downloads the header data of the packet into the Ethernet port packet header register 305 through the data scheduler 309 according to the storage location of the packet in the location information queue 302 in the main memory 101 . When the download of the package is completed, the timer 306 sets a registration time immediately. When the central processing unit wants to download the header data of the packet, it directly downloads from the packet header register 305 without downloading from the main memory 101 through the data scheduler 309 . On the other hand, after the set registration time, if the central processing unit has not read the packet header data, then clear all stored data in the Ethernet port packet header register 305 and the location information queue 302 .

Similarly, when the WLAN port packet detector 303 detects that a packet is stored into the main memory 101 by the WLAN port packet DMA controller 311, it stores the storage location of the packet in the main memory 101 in the location In the message queue 304. The wireless LAN port packet header register 307 downloads the header data of the packet into the wireless LAN port packet header register 307 through the data scheduler 309 according to the storage location of the packet in the location information queue 304 in the main memory 101 . When the download of the package is completed, the timer 308 sets a registration time immediately. When the central processing unit wants to download the header data of the packet, it downloads directly from the WLAN port packet header register 307 without downloading from the main memory 101 through the data scheduler 309 . On the other hand, after the set registration time, if the central processing unit has not read the packet header data, then clear all stored data in the wireless LAN port packet header register 307 and the location information queue 304 . In the embodiment of the present invention, the Ethernet port packet header register 305 and the WLAN port packet header register 307 may be static random access memories. The lengths of the location information queue 302 and the location information queue 304 can be set by the user. The Ethernet port packet detector 301 and the wireless LAN port packet detector 303 in the embodiment of the present invention may be implemented in one of software implementation, hardware implementation, and implementation on a platform embedded with a single processor or multiple processors.

In order to enable those skilled in the art to implement the present invention through the teaching of this embodiment, an embodiment of a method for preloading a packet header is provided below in combination with the above-mentioned packet header preloading device.

FIG. 4 shows a flowchart of a packet header preloading method according to yet another embodiment of the present invention. In step S401, a packet detector keeps monitoring packet access status. In step S402, it is determined whether there is an action of storing a packet to a main memory by a direct memory access. If not, return to step S401 to continue monitoring. If yes, then in step S403, the storage location of the package in the main memory is stored in a location information queue. In step S404, a packet header register downloads the header data of the packet into the packet header register through a data scheduler according to the storage location of the packet in the location information queue in the main memory. After downloading the header data of the packet to the packet header register, the location information of the packet in the location information queue is cleared. In step S405, a registration time is set. In step S406, it is judged whether it has been read. If yes, clear the data stored in the packet header register in step S408. If not, it is judged in step S407 whether the registration time has expired. If not, go back to step S406 to judge whether it has been read again. If yes, clear all stored data in the packet header register and the location information queue in step S409.

In summary, the packet header preloading method and device of the present invention download the packet header data into a packet header register in advance before the central processing unit executes downloading of a packet header data to speed up the processing of the packet header data speed. In addition, the present invention incorporates a mechanism for setting a registration time to improve the robustness of the packet header preloading device of the present invention in processing packets.

The technical content and technical features of the present invention have been disclosed above, but those skilled in the art may still make various replacements and modifications based on the teaching and disclosure of the present invention without departing from the spirit of the present invention. Therefore, the protection scope of the present invention should not be limited to the disclosed embodiments, but should include various replacements and modifications that do not depart from the present invention, and be covered by the appended claims.

Claims (15)

1. A device for packet header preloading, characterized in that it comprises: at least one packet detector for monitoring at least one packet direct memory access controller storing at least one packet into main memory; At least one packet header register; at least one location information queue, the location information queue is coupled to the packet detector and used to store the location of the at least one packet in the main memory; as well as At least one data scheduler, used to pre-load the header data of the at least one packet from the read from the main memory and store in the at least one packet header register; Wherein, when the packet detector detects that at least one packet direct memory access controller stores at least one packet into the main memory, the location of the packet in the main memory is stored in the location information queue. 2. The device according to claim 1 , further comprising a timer, the timer being coupled to the packet header register and used to calculate the time for which header data of the packet is stored in the packet header register . 3. The device according to claim 1, wherein said at least one packet detector comprises an Ethernet port packet detector and a WLAN port packet detector. 4. The device according to claim 1, wherein the at least one packet header register comprises an Ethernet port packet header register and a WLAN port packet header register. 5. The device according to claim 1, wherein the packet DMA controller is an Ethernet port packet DMA controller or a WLAN port packet DMA controller. 6. The device according to claim 1, wherein the packet header register is a static random access memory. 7. The device according to claim 1, wherein the main memory is a dynamic random access memory, a synchronous dynamic random access memory or a dual-channel synchronous dynamic random access memory. 8. The device according to claim 1, wherein the packet detector is implemented by software, hardware, or a platform embedded with a single processor or multiple processors. 9. A method of packet header preloading realized by the device for packet header preloading according to claim 1, characterized in that it comprises: monitoring an action of at least one packet of direct memory access controller storing at least one packet into main memory; downloading header data of the at least one packet into a packet header register; and If within the set time, the central processing unit is to read the header data of the at least one packet, then the header data of the at least one packet is provided by the packet header register; The method further comprises the step of storing the location of said packet in said main memory into a location information queue when at least one packet of direct memory access controller is detected to store at least one packet into main memory; The step of downloading the header data of the packet into the packet header register is based on the location information of the packet in the location information queue. 10. The method according to claim 9, further comprising the step of clearing the location information of the packet in the location information queue after downloading the header data of the packet to the packet header register. 11. The method according to claim 9, wherein the length of the location information queue is set by a user. 12. The method of claim 9, further comprising the steps of: clearing the header data of the packet after the header data of the packet is read by the central processing unit; Download the header data of the next packet into the packet header register. 13. The method of claim 9, further comprising the steps of: If the header data of the packet has not been read by the central processing unit after a set time, then clear the header data of the packet and all stored data in the position information queue. 14. The method according to claim 9, wherein the storage operation is a burst write operation. 15. A packet processing system, characterized in that it comprises a media access control, a packet direct memory access controller, a central processing unit, a main memory, and a packet header preloading device, wherein the packet header preloading device monitors the The packet direct memory access controller stores at least one packet access action to the main memory, and pre-reads the header data of the at least one packet before the central processing unit has read the header data of the at least one packet, And if the central processing unit is to read the header data of the at least one packet within the set time, the header data of the at least one packet is provided by the packet header preloading device; Wherein said packet header preloading device includes: at least one packet detector for monitoring at least said packet DMA controller storing said at least one packet into said main memory; at least one packet header register; and At least one data scheduler, used to read the header data of the at least one packet from the main memory and store it in the at least one packet header register; Wherein the packet header preloading device further includes a location information queue, the location information queue is coupled to the packet detector and used to store the location of the packet in the main memory; Wherein, when the packet detector detects that at least one packet direct memory access controller stores at least one packet into the main memory, the location of the packet in the main memory is stored in the location information queue.

Images