[go: up one dir, main page]

CN101807558A - Element sealing and jointing structure and its process - Google Patents

Element sealing and jointing structure and its process Download PDF

Info

Publication number
CN101807558A
CN101807558A CN200910004134A CN200910004134A CN101807558A CN 101807558 A CN101807558 A CN 101807558A CN 200910004134 A CN200910004134 A CN 200910004134A CN 200910004134 A CN200910004134 A CN 200910004134A CN 101807558 A CN101807558 A CN 101807558A
Authority
CN
China
Prior art keywords
substrate
electrodes
joint structure
sealing joint
layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN200910004134A
Other languages
Chinese (zh)
Other versions
CN101807558B (en
Inventor
杨琮富
陆苏财
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Industrial Technology Research Institute ITRI
Original Assignee
Industrial Technology Research Institute ITRI
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Industrial Technology Research Institute ITRI filed Critical Industrial Technology Research Institute ITRI
Priority to CN200910004134XA priority Critical patent/CN101807558B/en
Publication of CN101807558A publication Critical patent/CN101807558A/en
Application granted granted Critical
Publication of CN101807558B publication Critical patent/CN101807558B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10Bump connectors ; Manufacturing methods related thereto
    • H01L24/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013Alloys
    • H01L2924/0132Binary Alloys
    • H01L2924/01322Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/14Integrated circuits

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Electrotherapy Devices (AREA)

Abstract

The invention discloses an element sealing and connecting structure and a process thereof. The element sealing joint structure comprises a buffer bump layer, a plurality of conductive joints and a sealing joint. The buffer bump layer is arranged between the element and the substrate and comprises a plurality of first parts and second parts, and the second parts surround the peripheries of the first parts. Each conductive joint part comprises a first electrode covering each first part and a second electrode on the substrate, and each first electrode is electrically connected with each second electrode. The sealing joint part comprises a joint ring on the substrate, and the joint ring and the second part are mutually jointed to form a sealing space between the element and the substrate.

Description

元件密封接合结构及其工艺 Component sealing joint structure and its process

技术领域technical field

本发明涉及一种密封接合结构,且特别是涉及一种同时达到元件密封及封装效果的密封接合结构及其工艺。The present invention relates to a sealing joint structure, and in particular to a sealing joint structure and a technique thereof which simultaneously achieve element sealing and packaging effects.

背景技术Background technique

综观医疗电子产品的发展趋势,注入式(implantable)微型封装元件及生物相容性(biocompatibility)技术扮演相当重要的角色,若无法达到生物相容性及密封性的要求,对注入微型封装元件的人体或动物而言,体液的侵蚀、降解或肌肉组织的活动所产生的破坏而使有毒物质侵入活体内,将有相当大的危险性。Looking at the development trend of medical electronic products, implantable micro-package components and biocompatibility technology play a very important role. If the requirements of biocompatibility and sealing cannot be met, the implantable micro-package components For humans or animals, the erosion and degradation of body fluids or the destruction of muscle tissue activities will cause toxic substances to invade the living body, which will be quite dangerous.

在采用钛金属盖(titanium can)的生医电子封装元件中,以多层陶瓷基板的电极将信号导通至外部。此多层陶瓷基板的制作是采用低温共烧陶瓷(LTCC,Low-Temperature Cofired Ceramics)技术,以金、银、铜等低阻抗金属作为电极,再使用平版印刷来涂布电路,最后在摄氏850度到900度中烧结而形成整合式陶瓷元件,并将此整合式陶瓷元件装入于钛金属盖的气闭密封空间中,而完成密封的工艺。In biomedical electronic packaging components using a titanium can, the electrodes of the multilayer ceramic substrate are used to conduct signals to the outside. The production of this multilayer ceramic substrate is based on low-temperature co-fired ceramics (LTCC, Low-Temperature Cofired Ceramics) technology, using gold, silver, copper and other low-impedance metals as electrodes, and then using lithography to coat the circuit, and finally at 850 degrees Celsius The integrated ceramic element is formed by sintering at a temperature of 900°C, and the integrated ceramic element is placed in the air-tight airtight space of the titanium metal cover to complete the sealing process.

近年来,为了达到微型化的要求,采用半导体集成电路工艺及封装技术,可制作出各式各样的微型封装元件,其以硅芯片、玻璃或高分子聚合物为基材,并结合微机电技术与生物医学技术,设计及制作具有微小化、快速、平行处理能力的生物及医疗用检测元件,例如基因芯片、蛋白质芯片、检体处理芯片及生物感测芯片等,充分运用分子生物学、分析化学、生化反应等原理,在微小面积上快速进行大量生化感测或反应。In recent years, in order to meet the requirements of miniaturization, various micro-package components can be produced by using semiconductor integrated circuit technology and packaging technology, which use silicon chips, glass or high molecular polymers as substrates, and combine micro-electromechanical components. Technology and biomedical technology, design and manufacture of biological and medical detection components with miniaturization, fast and parallel processing capabilities, such as gene chips, protein chips, specimen processing chips and biological sensing chips, etc., fully utilize molecular biology, Analyze the principles of chemistry and biochemical reactions, and quickly perform a large number of biochemical sensing or reactions on a small area.

此外,对于心律调整器(pacemaker)、神经刺激器(neurostimulator)或血糖监测器(blood glucose monitor)等注入式微型封装元件而言,为了避免有毒物质侵入活体内,密封材料及封装可靠度在安全上扮演着非常重要的角色。In addition, for injection-type micro-packaged components such as pacemakers, neurostimulators, or blood glucose monitors, in order to prevent toxic substances from invading the living body, the reliability of the sealing material and packaging must be safe. plays a very important role.

发明内容Contents of the invention

本发明提出一种元件密封接合结构,用以将元件封装于基板上,该元件密封结合结构包括缓冲凸块层、多个导电接合部、以及密封接合部。缓冲凸块层配置于该元件与该基板之间,该缓冲凸块层包括多个第一部分以及第二部分,且该第二部分环绕于该些第一部分的外围。多个导电接合部电性连接于该元件与该基板之间,其中各个导电接合部包括覆盖于各该第一部分的第一电极以及该基板上的第二电极,且各该第一电极与各该第二电极电性连接。密封接合部环绕于该些导电接合部的外围,该密封接合部包括该基板上的接合环,且该接合环与该第二部分相互接合,以使该元件与该基板之间形成密封空间。The invention provides an element sealing joint structure for packaging an element on a substrate. The element sealing joint structure includes a buffer bump layer, a plurality of conductive joint parts, and a sealing joint part. The buffer bump layer is disposed between the element and the substrate, the buffer bump layer includes a plurality of first parts and a second part, and the second part surrounds the periphery of the first parts. A plurality of conductive junctions are electrically connected between the element and the substrate, wherein each conductive junction includes a first electrode covering each first portion and a second electrode on the substrate, and each first electrode is connected to each The second electrode is electrically connected. The sealing joint part surrounds the periphery of the conductive joint parts, and the sealing joint part includes a joint ring on the substrate, and the joint ring and the second part are mutually jointed, so that a sealed space is formed between the element and the substrate.

本发明提出一种元件密封接合工艺。首先,提供预定形成元件的基材;形成缓冲层于该元件上;图案化该缓冲层,以形成包括多个第一部分以及第二部分的缓冲凸块层,其中该第二部分环绕于该些第一部分的外围;形成第一电极于各该第一部分上;提供基板,该基板形成有多个第二电极以及接合环,该接合环围绕于该些第二电极的外围。配置该元件于该基板上,其中各该第一电极对应于各该第二电极并与各该第二电极电性连接,且该接合环对应与该第二部分相互接合,以使该元件与该基板之间形成密封空间。The invention proposes an element hermetic bonding process. First, provide a base material for forming an element; form a buffer layer on the element; pattern the buffer layer to form a buffer bump layer including a plurality of first portions and second portions, wherein the second portion surrounds the elements The periphery of the first part; forming first electrodes on each of the first parts; providing a substrate, the substrate is formed with a plurality of second electrodes and a joint ring, and the joint ring surrounds the periphery of the second electrodes. The element is arranged on the substrate, wherein each of the first electrodes corresponds to each of the second electrodes and is electrically connected to each of the second electrodes, and the bonding ring is correspondingly bonded to the second part, so that the element and A sealed space is formed between the substrates.

本发明提出一种元件密封接合结构,用以将元件封装于基板上,该元件密封结合结构包括缓冲凸块层、多个导电接合部、以及密封接合部。缓冲凸块层配置于该元件与该基板之间,该元件具有多个接垫,而该缓冲凸块层具有环状部分,且该环状部分环绕于该些接垫的外围。多个导电接合部电性连接于该元件与该基板之间,其中各个导电接合部包括该元件上电性连接各该接垫的金属凸块以及该基板上的第二电极,且各该金属凸块与各该第二电极电性连接。密封接合部环绕于该些导电接合部的外围,该密封接合部包括该基板上的接合环,且该接合环与该环状部分相互接合,以使该元件与该基板之间形成密封空间。The invention provides an element sealing joint structure for packaging an element on a substrate. The element sealing joint structure includes a buffer bump layer, a plurality of conductive joint parts, and a sealing joint part. The buffer bump layer is disposed between the element and the substrate, the element has a plurality of pads, and the buffer bump layer has a ring-shaped portion surrounding the periphery of the pads. A plurality of conductive joints are electrically connected between the element and the substrate, wherein each conductive joint includes a metal bump electrically connected to each pad on the element and a second electrode on the substrate, and each metal The bumps are electrically connected to each of the second electrodes. The sealing joint part surrounds the periphery of the conductive joint parts, and the sealing joint part includes a joint ring on the substrate, and the joint ring and the ring part are mutually jointed to form a sealed space between the element and the substrate.

本发明提出一种元件密封接合工艺。首先,提供预定形成元件的基材,该元件具有多个接垫;形成缓冲层于该元件上;图案化该缓冲层,以形成具有环状部分的缓冲凸块层,其中该环状部分环绕于该些接垫的外围;形成多个金属凸块于该元件上,且各该金属凸块与各该接垫电性连接;提供基板,该基板形成有多个第二电极以及接合环,该接合环围绕于该些第二电极的外围。配置该元件于该基板上,其中各该金属凸块对应于各该第二电极并与各该第二电极电性连接,且该接合环对应与该环状部分相互接合,以使该元件与该基板之间形成密封空间。The invention proposes an element hermetic bonding process. Firstly, provide a base material for forming an element, the element has a plurality of contact pads; form a buffer layer on the element; pattern the buffer layer to form a buffer bump layer with a ring portion, wherein the ring portion surrounds On the periphery of the pads; forming a plurality of metal bumps on the element, and each of the metal bumps is electrically connected to each of the pads; providing a substrate, the substrate is formed with a plurality of second electrodes and a bonding ring, The bonding ring surrounds the periphery of the second electrodes. The element is disposed on the substrate, wherein each of the metal bumps corresponds to each of the second electrodes and is electrically connected to each of the second electrodes, and the bonding ring is correspondingly bonded to the annular portion, so that the element and A sealed space is formed between the substrates.

为让本发明的上述特征和优点能更明显易懂,下文特举实施例,并配合附图作详细说明如下。In order to make the above-mentioned features and advantages of the present invention more comprehensible, the following specific embodiments are described in detail with reference to the accompanying drawings.

附图说明Description of drawings

图1A及图1B为本发明二实施例的元件密封接合结构的剖面示意图。FIG. 1A and FIG. 1B are cross-sectional schematic diagrams of an element sealing joint structure according to two embodiments of the present invention.

图2A~图2E为图1A的元件密封接合结构的制作方法的流程示意图。2A to 2E are schematic flowcharts of the manufacturing method of the element sealing joint structure in FIG. 1A .

图3A及图3B为本发明另二实施例的元件密封接合结构的剖面示意图。3A and 3B are cross-sectional schematic diagrams of an element sealing joint structure according to another embodiment of the present invention.

图4A及图4B为本发明另二实施例的元件密封接合结构的剖面示意图。4A and 4B are cross-sectional schematic diagrams of an element sealing joint structure according to another embodiment of the present invention.

图5A及图5B为本发明另二实施例的元件密封接合结构的剖面示意图。5A and 5B are schematic cross-sectional views of an element sealing joint structure according to another second embodiment of the present invention.

图6A及图6B为本发明另二实施例的元件密封接合结构的剖面示意图。FIG. 6A and FIG. 6B are cross-sectional schematic views of an element sealing joint structure according to another second embodiment of the present invention.

附图标记说明Explanation of reference signs

1001~1010:元件密封接合结构1001~1010: Component seal joint structure

100:元件100: components

100S:有源表面100S: Active Surface

100P:保护层100P: protective layer

102:接垫102: Pad

104:金属层104: metal layer

104a:凸块底金属层104a: Under bump metallization layer

110’:缓冲材料110': cushioning material

110:缓冲凸块层110: buffer bump layer

110a:第一部分110a: Part I

110b:第二部分110b: Part II

110c:第三部分110c: Part Three

110d:环状部分110d: annular part

120:导电接合部120: Conductive junction

130:密封接合部130: Seal joint

140:基板140: Substrate

W:基材W: Substrate

S1:第一电极S1: first electrode

S2:第二电极S2: second electrode

S3:金属凸块S3: Metal bump

H1:第一粘着金属层H1: first adhesive metal layer

H2:第二粘着金属层H2: second adhesive metal layer

H3:第三粘着金属层H3: third adhesive metal layer

R1:接合环R1: adapter ring

C:密封空间C: sealed space

150:基板150: Substrate

152:导通孔152: via hole

S3:第三电极S3: third electrode

S4:神经刺激电极S4: Nerve stimulation electrodes

160:承载器160: Carrier

162:接垫162: Pad

170:生物相容性涂层170: biocompatible coating

100a:第一元件100a: first element

150a:第一基板150a: first substrate

100b:第二元件100b: second element

150b:第二基板150b: second substrate

具体实施方式Detailed ways

图1A及图1B为本发明二实施例的元件密封接合结构的剖面示意图。图2A~图2E为图1A的元件密封接合结构的制作方法的流程示意图。FIG. 1A and FIG. 1B are cross-sectional schematic diagrams of an element sealing joint structure according to two embodiments of the present invention. 2A to 2E are schematic flowcharts of the manufacturing method of the element sealing joint structure in FIG. 1A .

请参考图1A,元件密封接合结构1001包括缓冲凸块层110、多个导电接合部120、以及密封接合部130。其中,缓冲凸块层110例如以图案化的工艺形成多个第一部分110a以及环绕于这些第一部分110a的外围的第二部分110b(环状部分)。缓冲凸块层110的材料可为高分子材料的聚合物,例如是环氧树脂或聚酰亚胺树脂等,其作法是将高分子材料涂布在预定形成元件100的基材(例如是硅晶片)上,再进行曝光、显影工艺或光蚀刻、干蚀刻等工艺,以使高分子材料形成预定的图案(多个第一部分110a以及环绕于这些第一部分110a的外围的第二部分110b)。Referring to FIG. 1A , the component sealing joint structure 1001 includes a buffer bump layer 110 , a plurality of conductive joints 120 , and a sealing joint 130 . Wherein, the buffer bump layer 110 forms a plurality of first portions 110 a and a second portion 110 b (annular portion) surrounding the periphery of these first portions 110 a by, for example, a patterning process. The material of the buffer bump layer 110 can be a polymer of high molecular material, such as epoxy resin or polyimide resin, etc., and the method is to coat the high molecular material on the substrate (such as silicon Wafer), and then perform exposure, development process or photoetching, dry etching and other processes, so that the polymer material forms a predetermined pattern (a plurality of first parts 110a and the second part 110b surrounding the periphery of these first parts 110a).

有关缓冲凸块层110的图案化工艺及详细的结构,请参考图2A~图2D。首先,提供基材W,例如是半导体基材,用以形成一个或多个集成电路元件100(仅绘示其一),此元件100具有有源表面100S以及保护层100P,而接垫102(仅绘示其一)配置于有源表面100S上,且保护层100P覆盖有源表面100S并显露出接垫102。接着,请参考图2B及图2C,以溅镀或蒸镀方式全面性形成金属层104于保护层100P以及接垫102上,并形成缓冲材料110’(高分子材料或感光型的高分子材料)于元件100上。接着,请参考图2D,图案化缓冲材料110’,例如是进行曝光、显影工艺或光蚀刻、干蚀刻工艺,以形成包括多个第一部分110a(仅绘示其一)以及第二部分110b的缓冲凸块层110,其中第二部分110b环绕于这些第一部分110a的外围,因此,第二部分110b也就是将多个第一部分110a完整包覆于的环状凸起结构,同时具有缓冲及密封的功效。之后,请参考图2E,以溅镀或蒸镀的方式形成第一电极S1(其材料例如为铜、铝或金)于各个第一部分110a上(例如覆盖第一部分110a的侧壁及上表面),且金属层104经过蚀刻之后成为凸块底金属层104a,并与覆盖于各个第一部份110a的第一电极S1电性连接。For the patterning process and detailed structure of the buffer bump layer 110 , please refer to FIGS. 2A-2D . First, a substrate W, such as a semiconductor substrate, is provided to form one or more integrated circuit elements 100 (only one is shown), the element 100 has an active surface 100S and a protective layer 100P, and the pads 102 ( Only one of them is shown) is disposed on the active surface 100S, and the protection layer 100P covers the active surface 100S and exposes the pads 102 . Next, referring to FIG. 2B and FIG. 2C , a metal layer 104 is formed on the protective layer 100P and the pad 102 by sputtering or vapor deposition, and a buffer material 110 ′ (polymer material or photosensitive polymer material is formed. ) on the component 100. Next, please refer to FIG. 2D , patterning the buffer material 110', for example, performing an exposure, development process or photoetching, dry etching process, to form a plurality of first parts 110a (only one of them is shown) and a second part 110b The buffer bump layer 110, wherein the second part 110b surrounds the periphery of these first parts 110a, therefore, the second part 110b is also a ring-shaped protrusion structure that completely covers the first parts 110a, and has both buffering and sealing effect. Afterwards, referring to FIG. 2E , a first electrode S1 (material such as copper, aluminum or gold) is formed on each first portion 110a (for example, covering the sidewall and upper surface of the first portion 110a) by sputtering or evaporation. , and the metal layer 104 becomes the under-bump metal layer 104a after being etched, and is electrically connected to the first electrode S1 covering each first portion 110a.

在本实施例中,这些第一部分110a与第二部分110b以同一道图案化工艺一并完成,以减少工艺的步骤,并使后续的密封工艺以及元件封装步骤能同时进行。此外,这些第一部分110a与第二部分110b之间例如以蚀刻形成间距,使两者在结构上相互分离。但在另一实施例中,这些第一部分110a与第二部分110b之间在结构上相互连接,同样具有缓冲及密封的功效。In this embodiment, the first part 110a and the second part 110b are completed together in the same patterning process, so as to reduce the steps of the process and enable the subsequent sealing process and component packaging steps to be performed simultaneously. In addition, a space is formed between the first portion 110a and the second portion 110b, for example, by etching, so that the two are structurally separated from each other. However, in another embodiment, the first part 110 a and the second part 110 b are structurally connected to each other, which also has the function of cushioning and sealing.

如图1B所示的另一实施例,元件密封接合结构1002包括缓冲凸块层110、多个导电接合部120、以及密封接合部130。其中,缓冲凸块层110例如以图案化的工艺形成多个第一部分110a以及环绕于这些第一部分110a的外围的第二部分110b。有关缓冲凸块层110的制作方法请参考图2A~图2D的步骤,在此不再详述。本实施例与图1A的元件密封结合结构及图2A~图2D的工艺不同的是,这些第一部分110a与第二部分11b之间具有第三部分(连接部)110c,且在结构上相互连接为一体(材料相同),未经由蚀刻而形成间距,故能加强密封的接合强度,并同时达到元件密封及封装的效果。In another embodiment as shown in FIG. 1B , the device sealing joint structure 1002 includes a buffer bump layer 110 , a plurality of conductive joints 120 , and a sealing joint 130 . Wherein, the buffer bump layer 110 forms a plurality of first portions 110 a and a second portion 110 b surrounding the periphery of the first portions 110 a by, for example, a patterning process. For the manufacturing method of the buffer bump layer 110 , please refer to the steps in FIG. 2A to FIG. 2D , which will not be described in detail here. The difference between this embodiment and the element sealing combination structure in FIG. 1A and the process in FIGS. 2A to 2D is that there is a third part (connection part) 110c between the first part 110a and the second part 11b, and they are structurally connected to each other. Integral (same material), no spacing is formed by etching, so the bonding strength of the seal can be enhanced, and the effect of component sealing and packaging can be achieved at the same time.

接着,请参考图1A及图1B,导电接合部120电性连接于元件100与基板140(例如是印刷电路板)之间,用以将电信号经由基板140输入到元件100或经由基板140输出到外部,而各个导电接合部120包括覆盖于各个第一部分110a的第一电极S1以及基板140上的第二电极S2,且各个第一电极S1与各个第二电极S2例如通过第一粘着金属层H1(镍金合金或钛钨合金)电性连接。此外,密封接合部130环绕于这些导电接合部120的外围。密封接合部130包括基板140上的接合环R1(其材料例如是铜、铝或金),环绕于这些第二电极S2的外围,且该接合环R1与第二部分110b例如通过第二粘着金属层H2(镍金合金或钛钨合金)以及第三粘着金属层H3(镍金合金或钛钨合金)相互接合而形成气闭密封结构,以使元件100与基板140之间形成密封空间C。Next, please refer to FIG. 1A and FIG. 1B , the conductive joint 120 is electrically connected between the element 100 and the substrate 140 (such as a printed circuit board), and is used for inputting electrical signals to the element 100 through the substrate 140 or outputting through the substrate 140. to the outside, and each conductive joint 120 includes a first electrode S1 covering each first part 110a and a second electrode S2 on the substrate 140, and each first electrode S1 and each second electrode S2 are, for example, passed through a first adhesive metal layer H1 (nickel-gold alloy or titanium-tungsten alloy) is electrically connected. In addition, the sealing joint part 130 surrounds the periphery of these conductive joint parts 120 . The sealing joint 130 includes a joint ring R1 (the material of which is copper, aluminum or gold, for example) on the substrate 140, surrounding the periphery of the second electrodes S2, and the joint ring R1 and the second part 110b are connected to the second part 110b through a second adhesive metal, for example. The layer H2 (nickel-gold alloy or titanium-tungsten alloy) and the third adhesive metal layer H3 (nickel-gold alloy or titanium-tungsten alloy) are joined together to form an airtight sealing structure, so that a sealed space C is formed between the device 100 and the substrate 140 .

在上述的二实施例中,第一粘着金属层H1例如以溅镀或蒸镀的方式形成于各个第一电极S1上(参见图2E),而第二粘着金属层H2(可与第一电极S1同一道步骤形成)以及第三粘着金属层H3例如分别形成于第二部分100b以及接合环R1上,而当元件100配置于基板140上时,还可进行热压合步骤,以使各个第一粘着金属层H1电性接合于各个第一电极S1与各个第二电极S2之间,而第二粘着金属层H2与第三粘着金属层H3紧密地接合(共晶接合)于接合环R1与第二部分110b之间,以加强密封的接合强度。但第一粘着金属层H1、第二粘着金属层H2与第三粘着金属层H3仅为本发明的实施例,并非用以限制本发明。In the above two embodiments, the first adhesive metal layer H1 is formed on each first electrode S1 (see FIG. 2E ), for example by sputtering or vapor deposition, and the second adhesive metal layer H2 (which can be S1 is formed in the same step) and the third adhesive metal layer H3 are, for example, formed on the second part 100b and the bonding ring R1 respectively, and when the element 100 is disposed on the substrate 140, a thermocompression step can also be performed, so that each first An adhesive metal layer H1 is electrically bonded between each first electrode S1 and each second electrode S2, and the second adhesive metal layer H2 and the third adhesive metal layer H3 are tightly bonded (eutectic bonding) between the bonding ring R1 and the third electrode S2. between the second parts 110b to enhance the joint strength of the seal. However, the first adhesive metal layer H1 , the second adhesive metal layer H2 and the third adhesive metal layer H3 are only examples of the present invention, and are not intended to limit the present invention.

图3A及图3B为本发明另二实施例的元件密封接合结构的剖面示意图。请参考图3A及图3B,此元件密封接合结构1003、1004用以将元件100封装于基板150(例如是软性电路板)上,而基板150的第一表面上除了具有多个第二电极S2以及接合环R1之外,基板150的第二表面还包括多个第三电极S3。这些第三电极S3通过基板150的导通孔152分别与这些第二电极S2电性连接。此外,各个第三电极S3上还包括神经刺激电极S4(或导电贴片),可用于经皮电神经刺激器(TENS,Transcutaneous Electro Nerve Stimulator)中。各个神经刺激电极S4可经由其尖端放电,以提供电治疗或肌肉复健所需的刺激电流。3A and 3B are cross-sectional schematic diagrams of an element sealing joint structure according to another embodiment of the present invention. Please refer to FIG. 3A and FIG. 3B, the component sealing joint structures 1003, 1004 are used to package the component 100 on the substrate 150 (such as a flexible circuit board), and the first surface of the substrate 150 has a plurality of second electrodes In addition to S2 and the bonding ring R1, the second surface of the substrate 150 further includes a plurality of third electrodes S3. The third electrodes S3 are respectively electrically connected to the second electrodes S2 through the via holes 152 of the substrate 150 . In addition, each third electrode S3 also includes a nerve stimulation electrode S4 (or a conductive patch), which can be used in a Transcutaneous Electro Nerve Stimulator (TENS, Transcutaneous Electro Nerve Stimulator). Each nerve stimulating electrode S4 can discharge through its tip to provide stimulating current required for electrical therapy or muscle rehabilitation.

另外,图4A及图4B为本发明另二实施例的元件密封接合结构的剖面示意图,其中图4A为具有生物相容性涂层170的元件密封接合结构1005的剖面示意图,而图4B为堆叠型封装的元件密封接合结构1006的剖面示意图。请先参考图4A,以心律调整器、神经刺激器或血糖监测器等注入式生医元件为例,此元件密封接合结构1005用以将元件100(例如单芯片元件)封装于基板150上,而基板150可通过多个导电体S5(例如焊球)与承载器160的接垫162电性连接,以将信号传递到活体的外部,且基板150上还包括生物相容性涂层170(例如是硅胶等无毒性高分子聚合物),其覆盖于元件100的周围,除了加强元件100的覆盖率及密封性,更不会对活体的组织产生危害。In addition, FIG. 4A and FIG. 4B are schematic cross-sectional views of an element sealing joint structure according to another two embodiments of the present invention, wherein FIG. 4A is a schematic cross-sectional view of an element sealing joint structure 1005 with a biocompatible coating 170, and FIG. 4B is a stack A schematic cross-sectional view of an element sealing joint structure 1006 of a type package. Please refer to FIG. 4A first, taking injectable biomedical components such as a pacemaker, a nerve stimulator, or a blood glucose monitor as an example, the component sealing and bonding structure 1005 is used to package the component 100 (such as a single-chip component) on the substrate 150, The substrate 150 can be electrically connected to the pad 162 of the carrier 160 through a plurality of conductors S5 (such as solder balls) to transmit the signal to the outside of the living body, and the substrate 150 also includes a biocompatible coating 170 ( For example, non-toxic high molecular polymer such as silica gel), which covers the periphery of the element 100, not only enhances the coverage and sealing performance of the element 100, but also does not cause harm to living tissues.

接着,请参考图4B,堆叠型封装的元件密封接合结构1006用以将各个元件100(例如注入式生医元件或其他用途的单芯片元件)封装在各个基板150上,以形成堆叠型多芯片封装元件,其中第一元件100a的第一电极S1与第一基板150a的第二电极S2电性连接,接着第一基板150a的第三电极S3经由多个导电体S5(例如焊球)及穿过第二元件100b的多个导电穿孔S6与第二元件100b的金属接垫102电性连接,接着第二元件100b的第一电极S1与第二基板150b的第二电极S2电性连接,接着第二基板150b的第三电极S3经由多个导电体S5(例如焊球)与承载器160的接垫162电性连接,以将信号传到外部。如同图4A所述,各个基板150上还包括生物相容性涂层170(例如是硅胶等无毒性高分子聚合物),其覆盖于各个元件100的周围,除了加强各个元件100的覆盖率及密封性,更不会对活体的组织产生危害。当然,生物相容性涂层170亦可以其他高分子涂层(例如环氧树脂)取代,并非用以限制本发明。Next, please refer to FIG. 4B , the element sealing bonding structure 1006 of the stacked package is used to package each element 100 (such as an injectable biomedical element or a single-chip element for other purposes) on each substrate 150 to form a stacked multi-chip Packaging components, wherein the first electrode S1 of the first component 100a is electrically connected to the second electrode S2 of the first substrate 150a, and then the third electrode S3 of the first substrate 150a is passed through a plurality of conductors S5 (such as solder balls) and through The plurality of conductive vias S6 of the second element 100b are electrically connected to the metal pads 102 of the second element 100b, and then the first electrode S1 of the second element 100b is electrically connected to the second electrode S2 of the second substrate 150b, and then The third electrodes S3 of the second substrate 150 b are electrically connected to the pads 162 of the carrier 160 through a plurality of conductors S5 (such as solder balls), so as to transmit signals to the outside. As shown in FIG. 4A , each substrate 150 also includes a biocompatible coating 170 (such as a non-toxic polymer such as silica gel), which covers the surroundings of each element 100, in addition to enhancing the coverage of each element 100 and Sealing, and will not cause harm to living tissues. Of course, the biocompatible coating 170 can also be replaced by other polymer coatings (such as epoxy resin), which is not intended to limit the present invention.

再者,图5A及图5B为本发明另二实施例的元件密封接合结构的剖面示意图。请参考图5A及图5B,此元件密封接合结构1007、1008用以将元件100封装于基板140、150上,而基板140、150的第一表面上具有多个第二电极S1以及接合环R1。此外,基板150的第二表面还包括多个第三电极S3。各个第三电极S3通过基板150的导通孔152分别与各个第二电极S2电性连接。此外,在图5B中,各个第三电极S3上还包括神经刺激电极S4(或导电贴片),可用于经皮电神经刺激器(TENS)中。各个神经刺激电极S4可经由其尖端放电,以提供电治疗或肌肉复健所需的刺激电流。然而,图5A及图5B的实施例与上述二实施例(参见图1A、3A)不同的是,缓冲凸块层110的第一部分110a不是经由凸块底金属层104a形成在接垫102的上方,而是形成在接垫102附近的保护层上,接着再经由溅镀或蒸镀的方式形成第一电极S1于各个接垫102与各个第一部分110a之间(例如覆盖各个接垫102与各个第一部分110a的侧壁及上表面),以使各个接垫102通过各个第一电极S1与各个第二电极S2电性连接。Furthermore, FIG. 5A and FIG. 5B are cross-sectional schematic diagrams of an element sealing joint structure according to another second embodiment of the present invention. Please refer to FIG. 5A and FIG. 5B, the component sealing bonding structures 1007, 1008 are used to package the component 100 on the substrate 140, 150, and the first surface of the substrate 140, 150 has a plurality of second electrodes S1 and bonding ring R1 . In addition, the second surface of the substrate 150 further includes a plurality of third electrodes S3. Each third electrode S3 is electrically connected to each second electrode S2 through the via hole 152 of the substrate 150 . In addition, in FIG. 5B , each third electrode S3 also includes nerve stimulation electrodes S4 (or conductive patches), which can be used in a transcutaneous electrical nerve stimulator (TENS). Each nerve stimulating electrode S4 can discharge through its tip to provide stimulating current required for electrical therapy or muscle rehabilitation. However, the embodiment of FIG. 5A and FIG. 5B is different from the above two embodiments (see FIG. 1A, 3A) in that the first portion 110a of the buffer bump layer 110 is not formed on the pad 102 via the UBM layer 104a. , but formed on the protective layer near the pads 102, and then form the first electrode S1 between each pad 102 and each first part 110a by sputtering or evaporation (for example, covering each pad 102 and each The sidewall and the upper surface of the first part 110a), so that each pad 102 is electrically connected to each second electrode S2 through each first electrode S1.

有关图5A及图5B的缓冲凸块层110的工艺与上述的图2D及图2E的缓冲凸块层110的工艺类似,不同之处在于省略图2B的凸块底金属层104的工艺,且于图案化缓冲凸块层110之后,再以溅镀或蒸镀的方式形成第一电极S1,以电性连接各个接垫102。因此,缓冲凸块层110的第一部分110a的位置不限定位于接垫102的上方,亦可经由重布线的第一电极S1往内侧延伸,以适合不同需求的接点设计。The process of the buffer bump layer 110 in FIG. 5A and FIG. 5B is similar to the process of the buffer bump layer 110 in FIG. 2D and FIG. 2E described above, except that the process of the UBM layer 104 in FIG. 2B is omitted, and After the buffer bump layer 110 is patterned, the first electrode S1 is formed by sputtering or evaporation to electrically connect each pad 102 . Therefore, the position of the first portion 110 a of the buffer bump layer 110 is not limited to be located above the pad 102 , and can also extend inward through the redistributed first electrode S1 , so as to meet different contact design requirements.

接着,图6A及图6B为本发明另二实施例的元件密封接合结构的剖面示意图。请参考图6A及图6B,元件密封接合结构1009、1010包括缓冲凸块层110、多个导电接合部120、以及密封接合部130。其中,缓冲凸块层110是以高分子材料的聚合物来制作环状部分110d(图6B中),并采用导电材料来制作多个金属凸块S3(取代原先的第一部分110a),且金属凸块S3可通过凸块底金属层104a与各个接垫102电性连接,以使第一电极S1、金属凸块S3以及第二电极S2构成具有电性连接功能的导电接合部120,而环绕于这些金属凸块S3周围的环状部分110d与密封接合部130接合,同时具有密封及缓冲的功效,以使元件100与基板140之间形成密封空间C。Next, FIG. 6A and FIG. 6B are cross-sectional schematic diagrams of an element sealing joint structure according to another embodiment of the present invention. Please refer to FIG. 6A and FIG. 6B , the component sealing joint structures 1009 , 1010 include a buffer bump layer 110 , a plurality of conductive joints 120 , and a sealing joint 130 . Among them, the buffer bump layer 110 is made of a polymer material with a ring-shaped part 110d (in FIG. 6B ), and a plurality of metal bumps S3 (replacing the original first part 110a) are made of a conductive material, and the metal The bump S3 can be electrically connected to each pad 102 through the under-bump metal layer 104a, so that the first electrode S1, the metal bump S3 and the second electrode S2 form a conductive joint 120 with an electrical connection function, and surround The annular portion 110 d around the metal bumps S3 is bonded to the sealing joint portion 130 , and has the functions of sealing and cushioning, so that a sealed space C is formed between the device 100 and the substrate 140 .

有关图6A及图6B的金属凸块S3的工艺与上述的图2D及图2E的缓冲凸块层110的工艺类似,不同之处在于以电镀方式形成金属凸块S3于接垫102上,且于形成金属凸块S3之后,再以溅镀或蒸镀的方式形成第一电极S1,以覆盖各个金属凸块S3。The process of the metal bump S3 in FIG. 6A and FIG. 6B is similar to the process of the buffer bump layer 110 in FIG. 2D and FIG. 2E described above, except that the metal bump S3 is formed on the pad 102 by electroplating, and After the metal bumps S3 are formed, the first electrode S1 is formed by sputtering or vapor deposition to cover each metal bump S3.

在本实施例中,上述的金属凸块S3的材料若为金时,可直接通过第一粘着金属层H1与第二电极S2电性连接,而不需先形成第一电极S1于金属凸块S3上。另外,金属凸块S3的材料若为铜或铜合金时,可通过金属凸块S3上的第一电极S1做为抗氧化层(例如镍/金层),以避免铜表面的氧化。In this embodiment, if the material of the above-mentioned metal bump S3 is gold, it can be directly electrically connected to the second electrode S2 through the first adhesive metal layer H1, without first forming the first electrode S1 on the metal bump. on S3. In addition, if the material of the metal bump S3 is copper or copper alloy, the first electrode S1 on the metal bump S3 can be used as an anti-oxidation layer (eg nickel/gold layer) to avoid oxidation of the copper surface.

综上所述,本发明提出多种元件密封接合结构及其工艺,可应用在各式各样的微型封装元件上,例如基因芯片、蛋白质芯片、检体处理芯片及生物感测芯片等,或者是注入式生医元件中。除了通过缓冲凸块层来加强密封的接合强度,还可同时达到元件密封及封装的效果,避免有毒物质侵入活体内。此外,缓冲凸块层以同一道图案化工艺完成,不需额外制作多个光掩模及进行多道光掩模工艺,以减少工艺的步骤,并使后续的密封工艺以及元件封装步骤能同时进行,进而简化元件密封及封装工艺及降低生产成本。In summary, the present invention proposes a variety of component sealing and bonding structures and processes thereof, which can be applied to various micro-packaged components, such as gene chips, protein chips, specimen processing chips, and bio-sensing chips, etc., or Injectable biomedical components. In addition to strengthening the bonding strength of the seal through the buffer bump layer, it can also achieve the effect of component sealing and packaging at the same time, preventing toxic substances from invading the living body. In addition, the buffer bump layer is completed in the same patterning process, which does not require additional fabrication of multiple photomasks and multiple photomask processes, so as to reduce process steps and enable subsequent sealing processes and component packaging steps to be performed simultaneously , thereby simplifying the component sealing and packaging process and reducing the production cost.

虽然本发明已以实施例披露如上,然其并非用以限定本发明,任何所属技术领域中普通技术人员,在不脱离本发明的精神和范围内,当可作些许的更动与润饰,故本发明的保护范围当视权利要求所界定者为准。Although the present invention has been disclosed above with embodiments, it is not intended to limit the present invention. Any person skilled in the art may make some modifications and modifications without departing from the spirit and scope of the present invention. The scope of protection of the present invention should be defined by the claims.

Claims (35)

1.一种元件密封接合结构,用以将元件封装于基板上,该元件密封结合结构包括:1. A component sealing joint structure for packaging components on a substrate, the component sealing joint structure comprising: 缓冲凸块层,配置于该元件与该基板之间,该缓冲凸块层包括多个第一部分以及第二部分,且该第二部分环绕于所述第一部分的外围;a buffer bump layer disposed between the element and the substrate, the buffer bump layer includes a plurality of first parts and a second part, and the second part surrounds the periphery of the first part; 多个导电接合部,电性连接于该元件与该基板之间,其中各个导电接合部包括覆盖于各该第一部分的第一电极以及该基板上的第二电极,且各该第一电极与各该第二电极电性连接;以及A plurality of conductive joints are electrically connected between the element and the substrate, wherein each conductive joint includes a first electrode covering each of the first parts and a second electrode on the substrate, and each of the first electrodes is connected to the substrate. each of the second electrodes is electrically connected; and 密封接合部,环绕于该多个导电接合部的外围,该密封接合部包括该基板上的接合环,且该接合环与该第二部分相互接合,以使该元件与该基板之间形成密封空间。a sealing joint part surrounding the periphery of the plurality of conductive joint parts, the sealing joint part includes a joint ring on the substrate, and the joint ring and the second part are mutually jointed to form a seal between the element and the substrate space. 2.如权利要求1所述的元件密封接合结构,其中该多个第一部分与该第二部分之间形成有间距,且在结构上相互分离。2. The element sealing joint structure as claimed in claim 1, wherein a gap is formed between the plurality of first portions and the second portion, and are structurally separated from each other. 3.如权利要求1所述的元件密封接合结构,其中该多个第一部分与该第二部分之间具有第三部分,且在结构上相互连接。3. The component sealing joint structure as claimed in claim 1, wherein a third portion is located between the plurality of first portions and the second portion, and is structurally connected to each other. 4.如权利要求1所述的元件密封接合结构,其中该缓冲凸块层的材料包括高分子材料。4. The device sealing joint structure as claimed in claim 1, wherein a material of the buffer bump layer comprises a polymer material. 5.如权利要求1所述的元件密封接合结构,其中各该第一电极与各该第二电极之间还包括第一粘着金属层。5. The element sealing joint structure as claimed in claim 1, wherein a first adhesive metal layer is further included between each of the first electrodes and each of the second electrodes. 6.如权利要求1所述的元件密封接合结构,其中该接合环与该第二部分之间还包括第二粘着金属层以及第三粘着金属层。6 . The component sealing joint structure as claimed in claim 1 , further comprising a second adhesive metal layer and a third adhesive metal layer between the joint ring and the second part. 7.如权利要求1所述的元件密封接合结构,其中该基板还包括多个第三电极,而该多个第三电极通过该基板分别与该多个第二电极电性连接。7. The element sealing joint structure as claimed in claim 1, wherein the substrate further comprises a plurality of third electrodes, and the plurality of third electrodes are respectively electrically connected to the plurality of second electrodes through the substrate. 8.如权利要求7所述的元件密封接合结构,其中各该第三电极上还包括神经刺激电极。8. The device sealing joint structure as claimed in claim 7, wherein each of the third electrodes further comprises a nerve stimulation electrode. 9.如权利要求1所述的元件密封接合结构,其中该基板上还包括生物相容性涂层,覆盖于该元件的周围。9. The device sealing joint structure as claimed in claim 1, wherein the substrate further comprises a biocompatible coating covering the periphery of the device. 10.如权利要求9所述的元件密封接合结构,其中该元件为注入式生医元件。10. The component sealing engagement of claim 9, wherein the component is an injectable biomedical component. 11.如权利要求1所述的元件密封接合结构,其中该元件具有多个接垫,而各该第一部分经由凸块底金属层配置于各该接垫上,该凸块底金属层与覆盖于各该第一部份的该第一电极电性连接。11. The device sealing joint structure as claimed in claim 1, wherein the device has a plurality of pads, and each of the first portions is disposed on each of the pads via an under-bump metallization layer, and the under-bump metallization layer is covered with The first electrodes of each of the first parts are electrically connected. 12.如权利要求1所述的元件密封接合结构,其中该元件具有多个接垫,而该第一电极形成于各该接垫与各该第一部分之间,且各该接垫通过各该第一电极与各该第二电极电性连接。12. The element sealing joint structure as claimed in claim 1, wherein the element has a plurality of pads, and the first electrode is formed between each of the pads and each of the first parts, and each of the pads passes through each of the The first electrodes are electrically connected to each of the second electrodes. 13.如权利要求1所述的元件密封接合结构,其中该元件包括单芯片元件或堆叠型多芯片封装元件。13. The component hermetic joint structure as claimed in claim 1, wherein the component comprises a single-chip component or a stacked multi-chip package component. 14.一种元件密封接合工艺,包括:14. A component sealing bonding process, comprising: 提供预定形成元件的基材;providing the substrate from which the element is intended to be formed; 形成缓冲层于该元件上;forming a buffer layer on the element; 图案化该缓冲层,以形成包括多个第一部分以及第二部分的缓冲凸块层,其中该第二部分环绕于该多个第一部分的外围;patterning the buffer layer to form a buffer bump layer including a plurality of first portions and a second portion, wherein the second portion surrounds the periphery of the plurality of first portions; 形成第一电极于各该第一部分上;forming a first electrode on each of the first portions; 提供基板,该基板形成有多个第二电极以及接合环,该接合环围绕于该多个第二电极的外围;以及providing a substrate formed with a plurality of second electrodes and a bonding ring surrounding a periphery of the plurality of second electrodes; and 配置该元件于该基板上,其中各该第一电极对应于各该第二电极并与各该第二电极电性连接,且该接合环对应与该第二部分相互接合,以使该元件与该基板之间形成密封空间。The element is arranged on the substrate, wherein each of the first electrodes corresponds to each of the second electrodes and is electrically connected to each of the second electrodes, and the bonding ring is correspondingly bonded to the second part, so that the element and A sealed space is formed between the substrates. 15.如权利要求14所述的元件密封接合工艺,其中图案化该缓冲层的步骤中,该多个第一部分与该第二部分之间经蚀刻而形成有间距,且在结构上相互分离。15 . The device sealing bonding process as claimed in claim 14 , wherein in the step of patterning the buffer layer, the plurality of first portions and the second portions are etched to form gaps and are structurally separated from each other. 16.如权利要求14所述的元件密封接合工艺,其中图案化该缓冲层的步骤中,该多个第一部分与该第二部分之间分别形成有第三部分,且在结构上相互连接。16 . The element sealing bonding process as claimed in claim 14 , wherein in the step of patterning the buffer layer, third portions are respectively formed between the plurality of first portions and the second portions, and are structurally connected to each other. 17.如权利要求14所述的元件密封接合工艺,其中形成第一电极于各该第一部份之后,还包括:17. The element sealing bonding process as claimed in claim 14, wherein after forming the first electrodes after each of the first parts, further comprising: 形成第一粘着金属层于各该第一电极上;forming a first adhesive metal layer on each of the first electrodes; 形成第二粘着金属层于该第二部分上;forming a second adhesive metal layer on the second portion; 形成第三粘着金属层于该接合环上;以及forming a third adhesive metal layer on the bonding ring; and 将该元件配置于该基板时,还进行热压合步骤,以使各该第一粘着金属层电性接合于各该第一电极与各该第二电极之间,而该第二粘着金属层与该第三粘着金属层接合于该接合环与该第二部分之间。When disposing the element on the substrate, a thermocompression bonding step is also performed, so that each of the first adhesive metal layers is electrically bonded between each of the first electrodes and each of the second electrodes, and the second adhesive metal layer The third adhesive metal layer is bonded between the bonding ring and the second portion. 18.如权利要求14所述的元件密封接合工艺,其中提供该基板的步骤中,该基板还包括多个第三电极,该多个第三电极通过该基板分别与该多个第二电极电性连接。18. The element sealing bonding process according to claim 14, wherein in the step of providing the substrate, the substrate further includes a plurality of third electrodes, and the plurality of third electrodes are respectively electrically connected to the plurality of second electrodes through the substrate. sexual connection. 19.如权利要求18所述的元件密封接合工艺,其中提供该基板的步骤中,还包括形成神经刺激电极于各该第三电极上。19. The element sealing bonding process as claimed in claim 18, wherein the step of providing the substrate further comprises forming nerve stimulating electrodes on each of the third electrodes. 20.如权利要求14所述的元件密封接合工艺,其中配置该元件于该基板上时,还包括形成生物相容性涂层,覆盖于该元件的周围。20. The device sealing bonding process as claimed in claim 14, wherein when disposing the device on the substrate, further comprising forming a biocompatible coating to cover the periphery of the device. 21.一种元件密封接合结构,用以将元件封装于基板上,该元件密封结合结构包括:21. A component sealing joint structure for packaging components on a substrate, the component sealing joint structure comprising: 缓冲凸块层,配置于该元件与该基板之间,该元件具有多个接垫,而该缓冲凸块层具有环状部分,且该环状部分环绕于该多个接垫的外围;a buffer bump layer configured between the element and the substrate, the element has a plurality of pads, and the buffer bump layer has a ring portion surrounding the periphery of the plurality of pads; 多个导电接合部,电性连接于该元件与该基板之间,其中各个导电接合部包括该元件上电性连接各该接垫的金属凸块以及该基板上的第二电极,且各该金属凸块与各该第二电极电性连接;以及A plurality of conductive joints are electrically connected between the element and the substrate, wherein each conductive joint includes a metal bump electrically connected to each pad on the element and a second electrode on the substrate, and each of the metal bumps are electrically connected to each of the second electrodes; and 密封接合部,环绕于该多个导电接合部的外围,该密封接合部包括该基板上的接合环,且该接合环与该环状部分相互接合,以使该元件与该基板之间形成密封空间。A sealing joint part, surrounding the periphery of the plurality of conductive joint parts, the sealing joint part includes a joint ring on the substrate, and the joint ring and the annular part are mutually engaged to form a seal between the element and the substrate space. 22.如权利要求21所述的元件密封接合结构,其中该缓冲凸块层的材料包括高分子材料。22. The device sealing joint structure as claimed in claim 21, wherein a material of the buffer bump layer comprises a polymer material. 23.如权利要求21所述的元件密封接合结构,其中各该金属凸块与各该第二电极之间还包括第一粘着金属层。23. The element sealing joint structure as claimed in claim 21, wherein a first adhesive metal layer is further included between each of the metal bumps and each of the second electrodes. 24.如权利要求21所述的元件密封接合结构,其中该接合环与该环状部分之间还包括第二粘着金属层以及第三粘着金属层。24. The component sealing joint structure as claimed in claim 21, further comprising a second adhesive metal layer and a third adhesive metal layer between the joint ring and the annular portion. 25.如权利要求21所述的元件密封接合结构,其中该基板还包括多个第三电极,而该多个第三电极通过该基板分别与该多个第二电极电性连接。25. The device sealing joint structure as claimed in claim 21, wherein the substrate further comprises a plurality of third electrodes, and the plurality of third electrodes are respectively electrically connected to the plurality of second electrodes through the substrate. 26.如权利要求25所述的元件密封接合结构,其中各该第三电极上还包括神经刺激电极。26. The device sealing joint structure as claimed in claim 25, wherein each of the third electrodes further comprises a nerve stimulation electrode. 27.如权利要求21所述的元件密封接合结构,其中该基板上还包括生物相容性涂层,覆盖于该元件的周围。27. The device sealing joint structure as claimed in claim 21, wherein the substrate further comprises a biocompatible coating covering the periphery of the device. 28.如权利要求27所述的元件密封接合结构,其中该元件为注入式生医元件。28. The component sealing engagement of claim 27, wherein the component is an injectable biomedical component. 29.如权利要求21所述的元件密封接合结构,其中各该金属凸块经由凸块底金属层配置于各该接垫上,该凸块底金属层与覆盖于各该金属凸块上的第一电极电性连接。29. The element sealing joint structure as claimed in claim 21, wherein each of the metal bumps is disposed on each of the pads via an under-bump metal layer, and the under-bump metal layer and the first metal bump covering each of the metal bumps One electrode is electrically connected. 30.如权利要求21所述的元件密封接合结构,其中该元件包括单芯片元件或堆叠型多芯片封装元件。30. The device sealing joint structure as claimed in claim 21, wherein the device comprises a single-chip device or a stacked multi-chip package device. 31.一种元件密封接合工艺,包括:31. A component sealing bonding process comprising: 提供预定形成元件的基材,该元件具有多个接垫;providing a substrate intended to form a component having a plurality of pads; 形成缓冲层于该元件上;forming a buffer layer on the element; 图案化该缓冲层,以形成具有环状部分的缓冲凸块层,其中该环状部分环绕于该多个接垫的外围;patterning the buffer layer to form a buffer bump layer having a ring portion, wherein the ring portion surrounds the plurality of pads; 形成多个金属凸块于该元件上,且各该金属凸块与各该接垫电性连接;forming a plurality of metal bumps on the element, and each of the metal bumps is electrically connected to each of the pads; 提供基板,该基板形成有多个第二电极以及接合环,该接合环围绕于该多个第二电极的外围;以及providing a substrate formed with a plurality of second electrodes and a bonding ring surrounding a periphery of the plurality of second electrodes; and 配置该元件于该基板上,其中各该金属凸块对应于各该第二电极并与各该第二电极电性连接,且该接合环对应与该环状部分相互接合,以使该元件与该基板之间形成密封空间。The element is disposed on the substrate, wherein each of the metal bumps corresponds to each of the second electrodes and is electrically connected to each of the second electrodes, and the bonding ring is correspondingly bonded to the annular portion, so that the element and A sealed space is formed between the substrates. 32.如权利要求31所述的元件密封接合工艺,其中形成多个金属凸块于该元件上之后,还包括:32. The device sealing bonding process as claimed in claim 31, wherein after forming a plurality of metal bumps on the device, further comprising: 形成第一粘着金属层于各该金属凸块上;forming a first adhesive metal layer on each of the metal bumps; 形成第二粘着金属层于该环状部分上;forming a second adhesive metal layer on the annular portion; 形成第三粘着金属层于该接合环上;以及forming a third adhesive metal layer on the bonding ring; and 将该元件配置于该基板时,还进行热压合步骤,以使各该第一粘着金属层电性接合于各该金属凸块与各该第二电极之间,而该第二粘着金属层与该第三粘着金属层接合于该接合环与该环状部分之间。When disposing the element on the substrate, a thermocompression bonding step is also performed, so that each of the first adhesive metal layers is electrically bonded between each of the metal bumps and each of the second electrodes, and the second adhesive metal layer The third adhesive metal layer is bonded between the bonding ring and the annular portion. 33.如权利要求31所述的元件密封接合工艺,其中提供该基板的步骤中,该基板还包括多个第三电极,该多个第三电极通过该基板分别与该多个第二电极电性连接。33. The element sealing bonding process according to claim 31, wherein in the step of providing the substrate, the substrate further includes a plurality of third electrodes, and the plurality of third electrodes are respectively electrically connected to the plurality of second electrodes through the substrate. sexual connection. 34.如权利要求33所述的元件密封接合工艺,其中提供该基板的步骤中,还包括形成神经刺激电极于各该第三电极上。34. The element sealing bonding process as claimed in claim 33, wherein the step of providing the substrate further comprises forming a nerve stimulating electrode on each of the third electrodes. 35.如权利要求31所述的元件密封接合工艺,其中配置该元件于该基板上时,还包括形成生物相容性涂层,覆盖于该元件的周围。35. The element sealing bonding process as claimed in claim 31, wherein when disposing the element on the substrate, further comprising forming a biocompatible coating to cover the periphery of the element.
CN200910004134XA 2009-02-12 2009-02-12 Component sealing joint structure and its process Active CN101807558B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN200910004134XA CN101807558B (en) 2009-02-12 2009-02-12 Component sealing joint structure and its process

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN200910004134XA CN101807558B (en) 2009-02-12 2009-02-12 Component sealing joint structure and its process

Publications (2)

Publication Number Publication Date
CN101807558A true CN101807558A (en) 2010-08-18
CN101807558B CN101807558B (en) 2012-07-04

Family

ID=42609280

Family Applications (1)

Application Number Title Priority Date Filing Date
CN200910004134XA Active CN101807558B (en) 2009-02-12 2009-02-12 Component sealing joint structure and its process

Country Status (1)

Country Link
CN (1) CN101807558B (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103915422A (en) * 2013-01-04 2014-07-09 台湾积体电路制造股份有限公司 Method And Apparatus For Semiconductor Structure
CN105609439A (en) * 2016-02-26 2016-05-25 海迪科(南通)光电科技有限公司 CSP eutectic soldering method
CN106298557A (en) * 2015-05-22 2017-01-04 中国科学院苏州纳米技术与纳米仿生研究所 A kind of low-temperature bonding method based on Au/In isothermal solidification
CN112240810A (en) * 2019-07-18 2021-01-19 美宸科技股份有限公司 Pressure sensing device and manufacturing method thereof

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1309067C (en) * 2003-09-24 2007-04-04 财团法人工业技术研究院 Elastic bump structure and manufacturing method thereof
CN100521171C (en) * 2004-10-21 2009-07-29 财团法人工业技术研究院 Packaging and connecting structure of element

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103915422A (en) * 2013-01-04 2014-07-09 台湾积体电路制造股份有限公司 Method And Apparatus For Semiconductor Structure
US10160638B2 (en) 2013-01-04 2018-12-25 Taiwan Semiconductor Manufacturing Company, Ltd. Method and apparatus for a semiconductor structure
CN106298557A (en) * 2015-05-22 2017-01-04 中国科学院苏州纳米技术与纳米仿生研究所 A kind of low-temperature bonding method based on Au/In isothermal solidification
CN106298557B (en) * 2015-05-22 2019-08-02 中国科学院苏州纳米技术与纳米仿生研究所 A kind of low-temperature bonding method based on Au/In isothermal solidification
CN105609439A (en) * 2016-02-26 2016-05-25 海迪科(南通)光电科技有限公司 CSP eutectic soldering method
CN105609439B (en) * 2016-02-26 2018-04-20 海迪科(南通)光电科技有限公司 A kind of CSP eutectic welding methods
CN112240810A (en) * 2019-07-18 2021-01-19 美宸科技股份有限公司 Pressure sensing device and manufacturing method thereof
CN112240810B (en) * 2019-07-18 2022-05-10 美宸科技股份有限公司 Pressure sensing device and manufacturing method thereof

Also Published As

Publication number Publication date
CN101807558B (en) 2012-07-04

Similar Documents

Publication Publication Date Title
US11963796B1 (en) Heterogeneous integration of silicon-fabricated solid microneedle sensors and CMOS circuitry
EP2416841B1 (en) Electronics package for an active implantable medical device
Kim et al. Integrated wireless neural interface based on the Utah electrode array
US8121697B2 (en) Biocompatible bonding method and electronics package suitable for implantation
US8173490B2 (en) Fabrication of electronic devices including flexible electrical circuits
EP3030212B1 (en) Long-term packaging for the protection of implant electronics
US7706887B2 (en) Method for integrating pre-fabricated chip structures into functional electronic systems
US9504177B2 (en) Hermetic electronics package with dual-sided electrical feedthrough configuration
US8134230B2 (en) Sealed joint structure of device and process using the same
US8163596B2 (en) Stackable electronic package and method of making same
US11213690B2 (en) Wafer level packages of high voltage units for implantable medical devices
AU2009344197A1 (en) Bonded hermetic feed through for an active implantable medical device
JP2008055000A (en) Visual regeneration device
US9773715B2 (en) Multi-layer packaging scheme for implant electronics
CN101807558A (en) Element sealing and jointing structure and its process
US20160030753A1 (en) Multi-electrode neural prothesis system
US8288189B2 (en) Package structure having MEMS element and fabrication method thereof
TW588444B (en) Method of forming package structure with cavity
DE60210109D1 (en) SEMICONDUCTOR ASSEMBLY WITH SOFT ELECTRICAL CONNECTIONS, COMPONENT THEREOF AND ITS MANUFACTURING METHOD
Sundaram et al. High density electrical interconnections in liquid crystal polymer (LCP) substrates for retinal and neural prosthesis applications
TWI374524B (en) Sealed joint structure of device and process using the same
US20070260287A1 (en) Chip level biostable interconnect for implantable medical devices
JP2010172667A (en) Hermetic sealing method for electronic element, functional device unit for biological implantation using the method, and visual restoration aiding apparatus
JP3949077B2 (en) Semiconductor device, substrate, semiconductor device manufacturing method, and semiconductor device mounting method
JPH11354713A (en) Semiconductor device and mounting method

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant