CN101807436B - shift register - Google Patents

Abstract

The invention relates to a shift register, which comprises a plurality of transistors, a plurality of first control circuits and a plurality of second control circuits, wherein the transistors receive control of a starting pulse signal, a first clock pulse signal and a second clock pulse signal to generate a grid driving signal; the first clock pulse signal and the second clock pulse signal are opposite in phase, and the low level of the first clock pulse signal is different from the low level of the second clock pulse signal. In addition, each transistor is a negative critical voltage transistor; when each transistor is in a cut-off state, the electric potential of the grid electrode of the transistor is smaller than the electric potential of the source electrode/drain electrode of the transistor. The circuit structure of the shift register can achieve the effects of effectively reducing the size of a transistor and reducing power consumption.

Description

shift register

technical field

The present invention relates to the field of display technology, in particular to a shift register.

Background technique

In the prior art, the shift register is manufactured on a substrate, such as a glass substrate, and the process adopted is mainly an amorphous silicon process technology. Due to the low carrier mobility of the amorphous silicon material, it is necessary to design a large-sized thin film transistor in order to effectively drive the scanning lines of the display panel. However, a thin film transistor with a larger size occupies more space on the panel, making it difficult to design on display panel products with narrow borders or limited circuit space; moreover, the generated parasitic capacitance effect is also greater, causing clock pulse signal The power consumption on the line has also increased significantly. Therefore, although the cost of the gate drive circuit can be saved by fabricating the shift register on the substrate, if the size and power consumption of the thin film transistor are not improved, the application level of this technology will be limited.

Therefore, if the semiconductor material with high carrier mobility can be applied to the design of the shift register, the design size of the thin film transistor can be effectively reduced and the power consumption can be reduced. Although a semiconductor material with high carrier mobility has a large on-current, it is often accompanied by a large off-current. Taking the recently developed semiconductor material indium gallium zinc oxide (IGZO) as an example, the carrier mobility of IGZO is about 5 volts per meter second (V/m s), but the threshold voltage of the fabricated thin film transistor is about -5V. Therefore, if IGZO is applied to the shift register circuit structure proposed in the prior art, a large amount of leakage current will be caused, resulting in failure of the shift register.

Contents of the invention

The purpose of the present invention is to provide a shift register to overcome the technical defects in the prior art.

Therefore, a shift register proposed by an embodiment of the present invention includes a plurality of transistors, which are controlled by a start pulse signal, a first clock signal, and a second clock signal to generate a gate drive signal; wherein The first clock signal and the second clock signal are opposite to each other, and the low level of the first clock signal is different from the low level of the second clock signal. In addition, each transistor is a negative threshold voltage transistor; and when each transistor is in an off state, the potential of the gate of the transistor is lower than the potential of the source/drain of the transistor.

In an embodiment of the present invention, the above-mentioned plurality of transistors include a first transistor, a second transistor, and a third transistor; the gate of the first transistor receives the first clock pulse signal due to an electrical coupling relationship and passes through a coupling capacitor It is electrically connected to the drain/source of the first transistor, and the source/drain of the first transistor is electrically coupled to a power supply voltage, and the level of the power supply voltage is higher than the low level of the first clock pulse signal and low At the low level of the second clock pulse signal; the gate of the second transistor receives the first clock pulse signal due to the electrical coupling relationship, and the source/drain of the second transistor is electrically coupled to the drain/drain of the first transistor source, and the drain/source of the second transistor receives the start pulse signal due to the electrical coupling relationship; the gate of the third transistor is electrically coupled to the drain/source of the first transistor, and the source of the third transistor The /drain is used to output the gate driving signal, and the drain/source of the third transistor receives the second clock pulse signal due to the electrical coupling relationship.

In an embodiment of the present invention, the source/drain of the above-mentioned third transistor is further electrically coupled to the gate of the third transistor through another coupling capacitor.

In an embodiment of the present invention, the aforementioned multiple transistors further include a fourth transistor, wherein the gate of the fourth transistor is electrically coupled to the drain/source of the first transistor, and the source/drain of the fourth transistor is connected to to output another start pulse signal, and the drain/source of the fourth transistor is electrically coupled to the drain/source or source/drain of the third transistor.

In an embodiment of the present invention, the above-mentioned multiple transistors further include a fifth transistor, wherein the gate of the fifth transistor receives the first clock pulse signal due to an electrical coupling relationship, and the source/drain of the fifth transistor is due to Electrically coupled to receive the second power supply voltage and the level of the second power supply voltage is equal to the low level of the second clock pulse signal, the drain/source of the fifth transistor is electrically coupled to the source/source of the third transistor drain.

Another embodiment of the present invention proposes a shift register, which includes a control circuit and an output circuit; wherein the control circuit receives the start pulse signal, the first clock pulse signal and the power supply voltage due to the electrical coupling relationship, and according to The start pulse signal and the first clock pulse signal generate the enable signal, and the low level of the first clock pulse signal is lower than the level of the power supply voltage; the output circuit accepts the control of the enable signal and generates a gate according to the second clock pulse signal As for the driving signal, the second clock pulse signal and the first clock pulse signal are opposite to each other, and the low level of the second clock pulse signal is higher than the level of the power supply voltage.

In an embodiment of the present invention, the above-mentioned control circuit includes a first control transistor and a second control transistor; wherein, the gate of the first control transistor is used to receive the first clock pulse signal, and the source/drain of the first control transistor The pole is electrically coupled to the power supply voltage, the drain/source of the first control transistor is electrically connected to the gate of the first control transistor through a coupling capacitor; the gate of the second control transistor is electrically coupled to the first control transistor The gate of the second control transistor, the source/drain of the second control transistor is electrically coupled to the drain/source of the first control transistor and used to output the enable signal, and the drain/source of the second control transistor is used to receive the start pulse Signal.

In an embodiment of the present invention, the above-mentioned output circuit includes a first output transistor, wherein the gate of the first output transistor is used to receive the enable signal, and the source/drain of the first output transistor is used to output the gate drive signal , and the drain/source of the first output transistor is used for receiving the second clock pulse signal.

In an embodiment of the present invention, the above-mentioned output circuit further includes a second output transistor for generating a second start pulse signal, wherein the gate of the second output transistor is electrically coupled to the gate of the first output transistor, and the second output transistor is electrically coupled to the gate of the first output transistor. The source/drain of the two output transistors is used to output the second start pulse signal, and the drain/source of the second output transistor is electrically coupled to the source/drain or the drain/source of the first output transistor.

In an embodiment of the present invention, the above-mentioned shift register further includes a reset circuit, wherein the reset circuit receives the control of the first clock pulse signal to pull the potential of the output terminal of the gate drive signal of the output circuit to the first Two power supply voltages, and the level of the second power supply voltage is equal to the low level of the second clock pulse signal.

Another embodiment of the present invention proposes a shift register, which includes a control circuit and a first output transistor; wherein, the control circuit has a start pulse signal input terminal, a first clock pulse signal input terminal, and a power supply voltage input terminal , and includes a first control transistor and a second control transistor; the gate of the first control transistor is electrically coupled to the first clock signal input terminal, and the source/drain of the first control transistor is electrically coupled to the power supply voltage input terminal, and the drain/source of the first control transistor is electrically connected to the gate of the first control transistor through a coupling capacitor; the gate of the second control transistor is electrically coupled to the first clock pulse signal input terminal, and the second The source/drain of the control transistor is electrically coupled to the drain/source of the first control transistor, and the drain/source of the second control transistor is electrically coupled to the start pulse signal input terminal; the gate of the first output transistor The pole is electrically coupled to the drain/source of the first control transistor, the source/drain of the first output transistor is used as the gate drive signal output terminal, and the drain/source of the first output transistor is used as the second clock pulse signal input end. In addition, the first control transistor, the second control transistor and the first output transistor are all negative threshold voltage transistors.

In an embodiment of the present invention, the source/drain of the above-mentioned first output transistor is further electrically connected to the gate of the first output transistor through a coupling capacitor.

In an embodiment of the present invention, the above-mentioned shift register further includes a second output transistor, wherein the gate of the second output transistor is electrically coupled to the drain/source of the first control transistor of the control circuit. The source/drain of the second output transistor is used as the start pulse signal output end, and the drain/source of the second output transistor is electrically coupled to the gate drive signal output end or the second clock pulse signal input end, and the second output The transistors are negative threshold voltage transistors.

In an embodiment of the present invention, the above-mentioned shift register further includes a reset transistor, wherein the gate of the reset transistor is electrically coupled to the first clock signal input terminal of the control circuit, and the source of the reset transistor The /drain is used as another power supply voltage input terminal, and the drain/source of the reset transistor is electrically coupled to the gate driving signal output terminal, and the reset transistor is a negative threshold voltage transistor.

In the embodiment of the present invention, by specifically designing the circuit structure and operation process of the shift register, each transistor of the shift register can still operate normally after using a semiconductor material with high carrier mobility, so that The circuit structure of the shift register proposed by the embodiment of the present invention can effectively reduce the transistor size and reduce power consumption.

In order to make the above and other objects, features and advantages of the present invention more comprehensible, preferred embodiments will be described in detail below together with the accompanying drawings.

Description of drawings

FIG. 1 is a circuit structure diagram of a shift register related to the first embodiment of the present invention.

FIG. 2 is a timing diagram of various signals related to the first embodiment of the present invention.

FIG. 3 is a circuit structure diagram of another shift register related to the first embodiment of the present invention.

FIG. 4 is a circuit structure diagram of a shift register related to the second embodiment of the present invention.

Wherein, the reference signs are explained as follows:

10, 20: shift register

12, 22: Control circuit

14, 24: output circuit

T11, T21, T22, T41, T31: Transistors

Cc, Cb: coupling capacitance

26: reset circuit

ST(n-1), ST(n): start pulse signal

XCK, CK: clock pulse signal

VSS, VSS1, VSS2: supply voltage

Q(n): enable signal

G(n): gate drive signal

Detailed ways

Referring to FIG. 1 , it shows a circuit structure diagram of a shift register related to the first embodiment of the present invention. As shown in FIG. 1 , the shift register 10 includes a control circuit 12 and an output circuit 14 . What is explained here is that a plurality of stages of shift registers coupled in series can form a gate drive circuit (not shown), such as a gate drive circuit on an array (Gate Driver On Array, GOA), and this implementation The example shift register 10 may be any one of these stages coupled in series.

Specifically, the control circuit 12 includes transistors T11, T41 and a coupling capacitor Cc. Both the transistors T11 and T41 are negative threshold voltage transistors, such as transistors made of semiconductor material with high carrier mobility. Wherein, the gate of the transistor T41 is used as a clock pulse signal input terminal to receive the clock pulse signal XCK, the source/drain of the transistor T41 is electrically coupled to the power supply voltage VSS as the power supply voltage input terminal, and the drain/source of the transistor T41 is used as The output end of the enable signal Q(n) is electrically connected to the gate of the transistor T41 through the coupling capacitor Cc; the gate of the transistor T11 is electrically connected to the gate of the transistor T41 to receive the control of the clock signal XCK, The source/drain of the transistor T11 is electrically coupled to the drain/source of the transistor T41, and the drain/source of the transistor T11 serves as a start pulse signal input terminal for receiving the start pulse signal ST(n−1).

The output circuit 14 includes transistors T21 , T22 and a coupling capacitor Cb. The transistors T21 , T22 are both negative threshold voltage transistors, such as transistors made of semiconductor materials with high carrier mobility. Wherein, the transistor T21 is used as an output transistor of the gate driving signal G(n), and the transistor T22 is used as an output transistor of another start pulse signal ST(n). Specifically, the gate of the transistor T21 is electrically coupled to the drain/source of the transistor T41 of the control circuit 12, and the drain/source of the transistor T21 serves as a clock signal input terminal to receive another clock signal CK, and the transistor T21 The source/drain is used as the gate drive signal output terminal to output the gate drive signal G(n) and is preferably electrically connected to the gate of the transistor T21 through the coupling capacitor Cb; the gate of the transistor T22 is electrically coupled to The drain/source of the transistor T41 of the control circuit 12, the drain/source of the transistor T22 are electrically coupled to the drain/source of the transistor T21 to receive the clock pulse signal CK, and the source/drain of the transistor T22 is used as a start pulse signal The output terminal outputs a start pulse signal ST(n).

Here, it should be noted that when the shift register 10 is used as the last stage in a shift register with multiple stages coupled in series, the transistor T22 is usually not provided in the output circuit 14 to generate the start pulse signal ST(n); in addition, those skilled in the art may also omit the coupling capacitor Cb according to design considerations.

The operation process of the shift register 10 related to the first embodiment of the present invention will be described in detail below in conjunction with FIGS. 1 and 2. FIG. 2 shows the start pulse signal ST(n-1), the clock pulse signals XCK, CK , the timing diagram of the gate drive signal G(n) and the enable signal Q(n); here, the clock pulse signal XCK and the clock pulse signal CK are opposite to each other, that is, when the clock pulse signal XCK is at a high level, The clock pulse signal CK is low level, otherwise when the clock pulse signal CK is high level, the clock pulse signal XCK is low level; and, the low level of the clock pulse signal XCK is lower than the level of the power supply voltage VSS, and the clock The low level of the pulse signal CK is higher than the level of the power supply voltage VSS, so that each negative threshold voltage transistor T11, T41, T21 and T22 is in the off state, and the potential of the gate is lower than the potential of the source/drain to realize Smaller off current.

Specifically, when both the start pulse signal ST(n-1) and the clock signal XCK are at high level, the clock signal CK is at low level, the transistors T11 and T41 in the control circuit 12 are turned on, and the enable signal Q (n) is pulled up to a preset potential and charges the coupling capacitor Cb in the output circuit 14 to turn on the transistors T21 and T22 in the output circuit 14 . Next, the start pulse signal ST(n-1) and the clock pulse signal XCK both jump to a low level. Since the low level of the clock pulse signal XCK is lower than the level of the power supply voltage VSS, the transistor T11 in the control circuit and T41 are effectively cut off, and the level of the enable signal Q(n) is slightly pulled down due to the reverse coupling effect of the coupling capacitor Cc.

Afterwards, the clock pulse signal CK jumps from low level to high level, and the source/drain of the transistor T21 in the output circuit 14 outputs the gate drive signal G(n) (that is, the gate drive signal G(n) according to the input clock pulse signal CK. Pole drive pulse), at the same time, the source/drain of the transistor T22 in the output circuit 14 outputs the start pulse signal ST(n) according to the input clock pulse signal CK as the start pulse of the subsequent stage shift register signal; at this time, the level of the enable signal Q(n) is further pushed up due to the characteristic that the voltage across the coupling capacitor Cb is continuous, so that the on-current of the transistor T21 increases. Next, the clock pulse signal CK transitions to a low level, and the source/drain potentials of the transistors T21 and T22 are pulled down to be equal to the low level of the clock pulse signal CK.

Then, the clock pulse signal XCK jumps to a high level, the transistors T11 and T41 in the control circuit 12 are turned on, and the enable signal Q(n) is discharged to the power supply voltage VSS through the transistor T41, so that the transistor T21 in the output circuit 14 The potentials of the gates of T22 and T22 are all lower than the potentials of their source/drain, so that the transistors T21 and T22 are effectively cut off. Next, the clock pulse signal XCK jumps to a low level, and the enable signal Q(n) is pulled to a lower level due to the reverse coupling effect of the coupling capacitor Cc. Afterwards, when the clock pulse signal CK jumps to high level again, the level of the enable signal Q(n) will not exceed the power supply voltage VSS, so that the transistors T21 and T22 in the output circuit 14 can be kept in an effective cut-off state.

In addition, the circuit structure of the shift register 10 in the first embodiment of the present invention is not limited to that shown in FIG. 1 , and other circuit structures such as shown in FIG. 3 can also be used. Specifically, the circuit structure of the shift register 10 shown in FIG. 3 is basically the same as that of the shift register 10 shown in FIG. 1, except that the drain/source electrical properties of the transistor T22 in FIG. It is coupled to the source/drain of the transistor T21, instead of being electrically coupled to the drain/source of the transistor T21 as shown in FIG. 1 and directly receiving the clock signal CK.

Referring to FIG. 4 , it shows a circuit structure diagram of a shift register related to the second embodiment of the present invention. As shown in FIG. 4 , the shift register 20 includes a control circuit 22 , an output circuit 24 and a reset circuit 26 . It is explained here that a plurality of stages of shift registers coupled in series can form a gate drive circuit (not shown), such as a gate drive circuit on an array, and the shift register 20 of this embodiment It can be any one of the shift registers in which the stages are coupled in series.

Specifically, the control circuit 22 includes transistors T11, T41 and a coupling capacitor Cc. Both the transistors T11 and T41 are negative threshold voltage transistors, such as transistors made of semiconductor material with high carrier mobility. Wherein, the gate of the transistor T41 is used as a clock pulse signal input terminal to receive the clock pulse signal XCK, the source/drain of the transistor T41 is electrically coupled to the power supply voltage VSS1 as the power supply voltage input terminal, and the drain/source of the transistor T41 is used as The output end of the enable signal Q(n) is electrically connected to the gate of the transistor T41 through the coupling capacitor Cc; the gate of the transistor T11 is electrically connected to the gate of the transistor T41 to receive the control of the clock signal XCK, The source/drain of the transistor T11 is electrically coupled to the drain/source of the transistor T41, and the drain/source of the transistor T11 serves as a start pulse signal input terminal for receiving the start pulse signal ST(n−1).

The output circuit 24 includes transistors T21, T22 and a coupling capacitor Cb. Both the transistors T21 and T22 are negative threshold voltage transistors, such as transistors made of semiconductor material with high carrier mobility. Wherein, the transistor T21 is used as an output transistor of the gate driving signal G(n), and the transistor T22 is used as an output transistor of another start pulse signal ST(n). Specifically, the gate of the transistor T21 is electrically coupled to the drain/source of the transistor T41 of the control circuit 22, and the drain/source of the transistor T21 serves as a clock signal input terminal to receive another clock signal CK, and the transistor T21 The source/drain is used as the gate drive signal output terminal to output the gate drive signal G(n) and is preferably electrically connected to the gate of the transistor T21 through the coupling capacitor Cb; the gate of the transistor T22 is electrically coupled to The drain/source of the transistor T41 of the control circuit 22, the drain/source of the transistor T22 are electrically coupled to the drain/source of the transistor T21 to receive the clock pulse signal CK, and the source/drain of the transistor T22 is used as a start pulse signal The output terminal outputs a start pulse signal ST(n).

The reset circuit 26 includes a transistor T31 , which is a negative threshold voltage transistor, such as a transistor made of a semiconductor material with high carrier mobility. The gate of the transistor T31 receives the clock pulse signal XCK, the source/drain of the transistor T31 is electrically coupled to the power supply voltage VSS2, and the drain/source of the transistor T31 is electrically coupled to the source/drain of the transistor T21 in the output circuit 24 pole to pull its potential to the power supply voltage VSS2.

In the second embodiment of the present invention, in order to make each of the negative threshold voltage transistors T11, T41, T21, T22 and T31 in the cut-off state, the potential of the gate is lower than the potential of the source/drain to achieve a smaller off-current , the clock pulse signals CK and XCK are set to be opposite to each other, the level of the power supply voltage VSS1 is set to be higher than the low level of the clock pulse signal XCK and lower than the low level of the clock pulse signal CK, and the level of the power supply voltage VSS2 Set to be equal to the low level of the clock pulse signal CK.

Here, it should be noted that the operation process of the shift register 20 is substantially the same as that of the shift register 10 in the first embodiment, so it will not be repeated here. In addition, when the shift register 20 is used as the last stage in the shift register with multiple stages coupled in series, usually the transistor T22 may not be provided in the output circuit 24 to generate the start pulse signal ST(n); In addition, those skilled in the art may also omit the coupling capacitor Cb according to design considerations.

To sum up, the embodiments of the present invention make each transistor of the shift register a negative threshold voltage transistor by specifically designing the circuit structure and operation process of the shift register, for example, using high-carrier Transistors made of semiconductor material with high mobility can still operate normally, so that the circuit structure of the shift register proposed by the embodiment of the present invention can effectively reduce the size of the transistor and reduce power consumption.

Although the present invention has been disclosed above with preferred embodiments, it is not intended to limit the present invention. Anyone skilled in the art can make some changes and modifications without departing from the spirit and scope of the present invention. Therefore, this The scope of protection of the invention should be determined by the scope defined by the appended claims.

Claims (11)

1. A shift register, comprising: A plurality of transistors are controlled by a start pulse signal, a first clock signal and a second clock signal to generate a gate drive signal, the first clock signal and the second clock signal are opposite to each other phase, and the low level of the first clock signal is different from the low level of the second clock signal; Wherein, the plurality of transistors are all negative threshold voltage transistors, and when each of the plurality of transistors is in an off state, the potential of the gate of the transistor is lower than the potential of one of the source and drain of the transistor; Wherein the plurality of transistors include: a first transistor, the gate of the first transistor receives the first clock pulse signal due to an electrical coupling relationship and is electrically connected to one of the drain and the source of the first transistor through a coupling capacitor, The other of the source and the drain of the first transistor is electrically coupled to a power supply voltage whose level is higher than the low level of the first clock signal and lower than the second clock signal The low level of the signal; A second transistor, the gate of the second transistor receives the first clock pulse signal due to an electrical coupling relationship, and one of the source and drain of the second transistor is electrically coupled to the first transistor One of the drain and the source of the second transistor, and the other of the drain and the source of the second transistor receives the start pulse signal due to the electrical coupling relationship; and a third transistor, the gate of the third transistor is electrically coupled to one of the drain and the source of the first transistor, and one of the source and the drain of the third transistor is used to output the gate A pole driving signal, and the other of the drain and the source of the third transistor receives the second clock pulse signal due to an electrical coupling relationship. 2. The shift register as claimed in claim 1, wherein the other of the source and the drain of the third transistor is further electrically coupled to the gate of the third transistor through another coupling capacitor. 3. The shift register as claimed in claim 1, wherein said plurality of transistors further comprises: a fourth transistor, the gate of the fourth transistor is electrically coupled to one of the drain and the source of the first transistor, and one of the source and the drain of the fourth transistor is used to output another enable The start pulse signal, and the other of the drain and the source of the fourth transistor is electrically coupled to the other of the drain and the source or one of the source and the drain of the third transistor. 4. The shift register as claimed in claim 1, wherein said plurality of transistors further comprises: A fifth transistor, the gate of the fifth transistor receives the first clock pulse signal due to the electrical coupling relationship, and one of the source and the drain of the fifth transistor receives a The second power supply voltage and the level of the second power supply voltage is equal to the low level of the second clock pulse signal, and the other of the drain and the source of the fifth transistor is electrically coupled to the third transistor. one of source and drain. 5. A shift register, comprising: A control circuit, the control circuit receives a start pulse signal, a first clock pulse signal and a power supply voltage due to electrical coupling, and generates an enable signal according to the start pulse signal and the first clock pulse signal , wherein the low level of the first clock pulse signal is lower than the level of the power supply voltage; and An output circuit, the output circuit accepts the control of the enable signal and generates a gate driving signal according to a second clock pulse signal, wherein the second clock pulse signal and the first clock pulse signal are opposite to each other and the first clock pulse signal The low level of the second clock pulse signal is higher than the level of the power supply voltage; Wherein the control circuit includes: a first control transistor, the gate of the first control transistor is used to receive the first clock pulse signal, one of the source and the drain of the first control transistor is electrically coupled to the power supply voltage, the first control transistor The other of the drain and the source of the transistor is electrically connected to the gate of the first control transistor through a coupling capacitor; and a second control transistor, the gate of the second control transistor is electrically coupled to the gate of the first control transistor, and one of the source and drain of the second control transistor is electrically coupled to the first control transistor The other of the drain and source of a control transistor is used to output the enable signal, and the other of the drain and source of the second control transistor is used to receive the start pulse signal; Wherein the output circuit includes a first output transistor, the gate of the first output transistor is used to receive the enable signal, and one of the source and drain of the first output transistor is used to output the gate drive signal, and The other of the drain and the source of the first output transistor is used for receiving the second clock signal. 6. The shift register as claimed in claim 5, wherein the output circuit further comprises a second output transistor to generate a second start pulse signal, the gate of the second output transistor is electrically coupled to the The gate of the first output transistor, one of the source and the drain of the second output transistor is used to output the second start pulse signal, and the other of the drain and the source of the second output transistor is electrically coupled to one of the source and drain or the other of the drain and source of the first output transistor. 7. The shift register as claimed in claim 5, further comprising: A reset circuit, the reset circuit receives the control of the first clock pulse signal to pull the potential of the output terminal of the gate drive signal of the output circuit to a second power supply voltage, and the level of the second power supply voltage, etc. at the low level of the second clock signal. 8. A shift register, comprising: A control circuit has a start pulse signal input terminal, a first clock pulse signal input terminal and a power supply voltage input terminal, the control circuit includes: A first control transistor, the gate of the first control transistor is electrically coupled to the first clock signal input terminal, and one of the source and drain of the first control transistor is electrically coupled to the power supply voltage input terminal, and the other of the drain and the source of the first control transistor is electrically connected to the gate of the first control transistor through a coupling capacitor; and a second control transistor, the gate of the second control transistor is electrically coupled to the first clock signal input terminal, and one of the source and drain of the second control transistor is electrically coupled to the first control the other of the drain and the source of the transistor, and the other of the drain and the source of the second control transistor is electrically coupled to the start pulse signal input terminal; and a first output transistor, the gate of the first output transistor is electrically coupled to the other of the drain and the source of the first control transistor, and one of the source and the drain of the first output transistor serves as a a gate drive signal output terminal, and the other of the drain and source of the first output transistor is used as a second clock pulse signal input terminal; Wherein, the first control transistor, the second control transistor and the first output transistor are all negative threshold voltage transistors, and the first clock signal and the second clock signal are opposite phases of each other. 9. The shift register as claimed in claim 8, wherein one of the source and the drain of the first output transistor is further electrically connected to the gate of the first output transistor through another coupling capacitor . 10. The shift register as claimed in claim 8, further comprising a second output transistor, the gate of the second output transistor is electrically coupled to the drain and the source of the first control transistor of the control circuit one of the source and the drain of the second output transistor is used as a start pulse signal output terminal, and the other of the drain and the source of the second output transistor is electrically coupled to the gate The pole driving signal output end or the second clock pulse signal input end, and the second output transistor is a negative threshold voltage transistor. 11. The shift register as claimed in claim 8, further comprising a reset transistor, the gate of the reset transistor is electrically coupled to the first clock signal input end of the control circuit, the reset One of the source and the drain of the transistor is used as another power supply voltage input terminal, and the other of the drain and the source of the reset transistor is electrically coupled to the gate drive signal output terminal, and the reset transistor is A negative threshold voltage transistor.

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