CN101800246A

CN101800246A - ESD device

Info

Publication number: CN101800246A
Application number: CN201010123662A
Authority: CN
Inventors: 张昊
Original assignee: Shanghai Huahong Grace Semiconductor Manufacturing Corp
Current assignee: Shanghai Huahong Grace Semiconductor Manufacturing Corp
Priority date: 2010-03-12
Filing date: 2010-03-12
Publication date: 2010-08-11

Abstract

The invention discloses an ESD device. In the ESD device, compensation areas of which a conducting type is opposite to that of a drain area are formed and injected at the two ends of the drain area, so that relatively higher resistance can be obtained under a smaller drain width, the antistatic effect of the ESD device is improved, the area of a chip is saved and the cost is reduced.

Description

A kind of ESD device

Technical field

The present invention relates to technical field of integrated circuits, relate in particular to a kind of ESD device that reduces device size.

Background technology

Enter the deep-submicron epoch of integrated circuit live width along with the integrated circuit fabrication process level, MOS element in the integrated circuit all adopts LDD structure (Lightly Doped Drain), and silicide process has been widely used on the diffusion layer of MOS element, in order to reduce the diffusion series resistance of grid polycrystalline, adopted the manufacturing process of polycrystalline compounds simultaneously.Along with the dwindling of integrated circuit component, the thickness of grid oxide layer of MOS element is more and more thinner in addition, and the improvement of these manufacturing process can increase substantially the arithmetic speed of IC interior, and can improve the integrated level of circuit.But the improvement of these technologies has brought a very big drawback, and promptly deep submicron integrated circuit is easier is subjected to electrostatic impact and lost efficacy, thereby causes reliability of products to descend.

Static is ubiquitous in manufacturing, encapsulation, test and the use of chip, the electrostatic charge of accumulation discharges in the time of microsecond in nanosecond with the electric current of several amperes or tens amperes, instantaneous power is up to hundreds of kilowatt, and discharge energy can reach millijoule, and is very big to the destruction intensity of chip.So it is the electrostatic protection Module Design is directly connected to the functional stabilization of chip in the chip design, very important.Along with the development of technology, device feature size diminishes gradually, and grid oxygen is also proportional to be dwindled.The dielectric strength of silicon dioxide is approximately 8 * 10 ⁶V/cm, so thickness is that the grid oxygen puncture voltage of 10nm is about about 8V, many although this puncture voltage will double than the supply voltage of 3.3V, the static that various factors causes, generally its crest voltage far surpasses 8V; And along with all the metallize use of new technologies such as (Salicid) of polysilicon metallization (Polyside), diffusion region metallization (Silicide), polysilicon and diffusion region, the dead resistance of device reduces, and the esd protection ability weakens greatly.

ESD is meant static discharge (Electrostatic Discharge, be called for short ESD), because of the reason of ESD generation and the mode difference that integrated circuit is discharged thereof, characterizing the ESD phenomenon has 4 kinds of models usually: manikin HBM (Human Body Model), machine mould MM (Machine Model) and Charged Device Model CDM (charged Device Model) and electric field induction model FIM (Field Induced Model).The HBM discharge process can produce several amperes the electric current that sparks at hundreds of in nanosecond; The process of MM discharge is shorter, and the electric current that sparks that has several amperes within several nanoseconds to tens nanoseconds produces.The CDM discharge process is shorter, and is the most serious to the harm of chip, several nanoseconds the time ask in electric current reach tens amperes.

The failure cause that ESD causes mainly contains 2 kinds: thermal failure and electricity lost efficacy.Local current is concentrated and a large amount of heat of generation, make fusing of device localized metallic interconnection line or chip hot spot occur, thereby cause second breakdown, be called thermal failure, the electric field strength that is added in the voltage formation on the gate oxide is greater than its dielectric strength, cause dielectric breakdown or surface breakdown, be called electricity and lost efficacy.The inefficacy that ESD causes has 3 kinds of failure modes, is respectively: hard failure, soft failure and potential failure, so-called hard failure are meant the material damage or damage that so-called soft failure is meant the Iterim Change of logic function, and so-called potential failure is meant that time dependence lost efficacy.

In order to prevent that integrated circuit (IC) products from causing inefficacy because of ESD, integrated circuit (IC) products must be used the esd protection device with high-performance, high tolerance usually.Metal-oxide-semiconductor is extensively adopted by industry as the ESD protective device, and in order to improve the ESD performance, the way of taking at present is to increase ESD to inject (ESD implant) and blocking layer of metal silicide SAB/SB methods such as (Salicide Blocking).ESD implant can select doping type, and unit commonly used have boron (Boron) and arsenic (Arsenic) or phosphorus (Phosphorus).Boron is acceptor impurity P ⁺, arsenic and phosphorus are donor impurity N ⁺Some foundries only provides the ESD implant of boron-doping element, so be called PESD again.SAB technology increases a mask definition Salicide zone, then by sputter cobalt (cobalt) and silicon (silicon) interfacial reaction, forms metallized area.Like this, the zone that has SAB to stop keeps high-impedance state with regard to not metallizing, and produces big pressure drop during static discharge when excessive resistance, and electric current reduces simultaneously, reaches the protective capability that improves ESD.

The domain of existing ESD device and structural representation please refer to Fig. 1 and Fig. 2, wherein Fig. 1 is the domain schematic diagram of existing ESD device, and Fig. 2 is the structural representation of existing ESD device, and is extremely shown in Figure 2 as Fig. 1, this ESD device is the nmos device that is produced in the P trap 100, at N ⁺Doping has been carried out the PESD doping after forming source region 101 and drain region 103, forms ESD zone 104, and when grid 101 polysilicons and diffusion region metallization, increases a mask definition SAB zone 105.In order to improve the antistatic effect of this ESD device, need the width X that increases SAB zone 105 to obtain high resistance usually, thereby can bear high static.But the width X in SAB zone 105 too conference causes device area too big, and the increase of device area has increased the cost of IC design.

Therefore, how to obtain the ESD device that a kind of device area is little, antistatic effect is strong and become the technical problem that industry needs to be resolved hurrily.

Summary of the invention

The object of the present invention is to provide a kind of ESD device, too big to solve existing ESD device area occupied, the problem that cost is too high.

For addressing the above problem, the present invention proposes a kind of ESD device, and described ESD device comprises:

Semiconductor substrate;

The semiconductor well region of first conduction type;

The polysilicon gate that on the semiconductor well region of described first conduction type, defines;

Grid both sides on the semiconductor well region of described first conduction type, the source region and the drain region of second conduction type that heavy doping forms;

On the semiconductor well region of periphery, described drain region, inject the ESD zone of first conduction type that forms;

Inject the compensating basin of first conduction type that forms at two ends, described drain region; And

On described polysilicon gate and described source region and part drain region, form metallized silicide.

Optionally, described ESD device is a nmos device.

Optionally, the semiconductor well region of described first conduction type is a P type well region, and the source region of described second conduction type and drain region are N ⁺The source region of type and drain region.

Optionally, the mode that forms the ESD zone of described first conduction type is that PESD injects.

Optionally, the compensating basin of described first conduction type is P ^-The type compensating basin.

Optionally, the diffusion depth of the compensating basin of described first conduction type is less than the diffusion depth in described drain region.

ESD device provided by the present invention is by injecting the compensating basin that forms with the drain region conductivity type opposite at the two ends, drain region, thereby can under less drain width, obtain higher resistance, improve the antistatic effect of ESD device, saved area of chip, reduced cost.

Description of drawings

Fig. 1 is the domain schematic diagram of existing ESD device;

Fig. 2 is the structural representation of existing ESD device;

Fig. 3 is the domain schematic diagram of ESD device provided by the invention;

Fig. 4 is the structural representation of ESD device provided by the invention.

Embodiment

Below in conjunction with the drawings and specific embodiments the ESD device that the present invention proposes is described in further detail.According to the following describes and claims, advantages and features of the invention will be clearer.It should be noted that accompanying drawing all adopts very the form of simplifying and all uses non-ratio accurately, only in order to convenient, the purpose of the aid illustration embodiment of the invention lucidly.

Core concept of the present invention is, a kind of ESD device is provided, described ESD device is by injecting the compensating basin that forms with the drain region conductivity type opposite at the two ends, drain region, thereby can under less drain width, obtain higher resistance, improved the antistatic effect of ESD device, save area of chip, reduced cost.

Please refer to Fig. 3 and Fig. 4, wherein, Fig. 3 is the domain schematic diagram of ESD device provided by the invention, and Fig. 4 is the structural representation of ESD device provided by the invention, and to shown in Figure 4, described ESD device comprises as Fig. 3:

Semiconductor substrate;

The semiconductor well region 200 of first conduction type;

The polysilicon gate 201 of definition on the semiconductor well region 200 of described first conduction type;

Polysilicon gate 202 both sides on the semiconductor well region 200 of described first conduction type, the source region 201 and the drain region 203 of second conduction type that heavy doping forms;

On the semiconductor well region 200 of 203 peripheries, described drain region, inject the ESD zone 204 of first conduction type that forms;

Inject the compensating basin 206 of first conduction type that forms at 203 two ends, described drain region; And

Form metallized silicide on described polysilicon gate 202 and described source region 201 and part drain region 203, the width that forms the region S AB205 of metallization silicide on the described drain region is X ₂

Wherein, the compensating basin 206 of described first conduction type is to pass through P ⁺Inject the P that forms ^-Type compensating basin, its diffusion depth are less than the diffusion depth in described drain region 203, and for example, the diffusion depth in described drain region 203 is 0.2 μ m, and the diffusion depth of described compensating basin 206 is 0.1 μ m.

In a specific embodiment of the present invention, described ESD device is a nmos device, and the semiconductor well region of described first conduction type is a P type well region, and the source region of described second conduction type and drain region are N ⁺The source region of type and drain region.

In a specific embodiment of the present invention, the mode that forms the ESD zone of described first conduction type is that PESD injects.

General, for the semiconductor technology of 0.18 μ m, adopt existing ESD device architecture, the minimum widith X of described SAB105 ₁Be 1.72 μ m, and adopt ESD device architecture provided by the present invention that under the identical antistatic effect of maintenance, the minimum widith of described compensating basin 206 is 0.44 μ m, the minimum widith X of described SAB205 ₂Be 0.43 μ m, the minimum widith in described ESD zone 204 is 0.4 μ m.Therefore adopt ESD device provided by the present invention, under identical antistatic effect, the minimum widith of described SAB can be reduced to from 1.72 μ m and be lower than 1 μ m.

In sum, the invention provides a kind of ESD device, described ESD device is by injecting the compensating basin that forms with the drain region conductivity type opposite at the two ends, drain region, thereby can under less drain width, obtain higher resistance, improved the antistatic effect of ESD device, save area of chip, reduced cost.

Obviously, those skilled in the art can carry out various changes and modification to invention and not break away from the spirit and scope of the present invention.Like this, if of the present invention these are revised and modification belongs within the scope of claim of the present invention and equivalent technologies thereof, then the present invention also is intended to comprise these changes and modification interior.

Claims

1. an ESD device is characterized in that, comprising:

Semiconductor substrate;

The semiconductor well region of first conduction type;

2. ESD device as claimed in claim 1 is characterized in that, described ESD device is a nmos device.

3. ESD device as claimed in claim 2 is characterized in that, the semiconductor well region of described first conduction type is a P type well region, and the source region of described second conduction type and drain region are N ⁺The source region of type and drain region.

4. ESD device as claimed in claim 2 is characterized in that, the mode that forms the ESD zone of described first conduction type is that PESD injects.

5. ESD device as claimed in claim 2 is characterized in that, the compensating basin of described first conduction type is P ^-The type compensating basin.

6. ESD device as claimed in claim 2 is characterized in that the diffusion depth of the compensating basin of described first conduction type is less than the diffusion depth in described drain region.