CN101800197B - Method for adjusting gate work function of metal gate - Google Patents

Abstract

The invention discloses a method for adjusting the grid work function of a metal grid, which comprises the following steps: local oxidation isolation or shallow trench isolation, pre-implant oxidation, and then implant¹⁴N⁺(ii) a Rinsing the oxide film before injection, oxidizing the gate, and depositing polysilicon; photoetching and etchingForming a polysilicon gate electrode; injecting impurities, and activating the impurities; depositing metal nickel, annealing and silicifying to enable the metal nickel and the polycrystalline silicon to completely react to form a full-silicide metal gate; and selectively removing unreacted metallic nickel. The method provided by the invention is easy to integrate and realizes good compatibility with a CMOS process.

Description

A method for adjusting grid work function of metal grid

technical field

The invention relates to the field of microelectronic ultra-deep submicron technology complementary metal oxide semiconductor device (CMOS) and ultra-large-scale integration technology, in particular to a method for adjusting the gate work function of a fully silicided metal gate.

Background technique

With the development of microelectronic technology, the traditional polysilicon gate electrode can no longer meet the requirements of nanometer devices. The following problems exist in the polysilicon gate electrode of nano-devices: a. boron penetration effect of PMOS transistor; b. polysilicon depletion effect; c. excessive gate series resistance; d. and next-generation gate dielectric material (high dielectric constant gate dielectric) Incompatible, there is a Fermi pinning effect. The metal gate electrode can well solve the above problems of the polysilicon gate electrode, and becomes a substitute for the polysilicon gate electrode, and has become a research hotspot in the world.

However, there are still many problems to be solved in the preparation of metal gate devices. The first factor to consider is the selection of the gate material. There are many factors to consider when deciding which material to choose as the gate material. For example: (1) Compatibility with CMOS process (such as thermal stability, etchable, etc.); (2) Impact on gate dielectric reliability (3) Process scalability (such as high dielectric constant gate dielectric) . In addition to the above factors, the most important consideration for selection is the matching of the grid work function.

Because the gate work function directly affects the threshold voltage (V _th ) of the device and the performance of the transistor. In order to obtain good performance, an appropriate gate work function must be selected to make the threshold voltages of NMOS and PMOS transistors symmetrical and appropriately low. For devices with advanced new structures, the gate work function is particularly important. Many of these new device structures operate in a fully depleted mode of operation. The substrate doping concentration is very low or even undoped. In this way, the threshold value fluctuation caused by doping can be avoided, the scattering effect of impurities on the carriers in the channel region can be reduced, the mobility of the carriers can be improved, and a higher driving current can be obtained. However, the result of this is that the threshold voltage cannot be adjusted by injecting impurities into the channel, and the threshold of the device can only be adjusted by changing the work function of the gate, which has relatively high requirements for the adjustment ability of the work function of the gate electrode.

So far, researchers have proposed a variety of metal gate integration technologies, such as single work function metal gate method, double metal method, metal interdiffusion method, single metal double work function method, and full silicide method. Among these methods, due to the simple method of adjusting the work function of the fully silicided gate, the simple preparation process, and good compatibility with the CMOS process, it is a promising technology for the next-generation metal gate preparation process.

The initial full silicide method usually adopts implanting conventional impurities (B, BF ₂ , As, P, Sb) etc. to adjust the work function of the full silicide metal gate. However, the study found that conventional impurities have limited ability to adjust the gate work function, and cannot meet the requirements of high-performance bulk silicon complementary metal-oxide semiconductor devices (CMOS) for the gate electrode work function; and the implanted As and Sb impurities will also cause gate dielectric and Adhesion problem between gate electrodes. In order to meet the requirements of high-performance complementary metal-oxide-semiconductor devices (CMOS) on the work function of the gate electrode, it is necessary to find new impurities to adjust the gate work function of the fully silicided metal gate. The new impurity should not only be able to obtain a large gate work function adjustment capability, but also be compatible with the CMOS process and be easily integrated into the CMOS process. Therefore, it is necessary to find a new and easy-to-integrate fully silicided metal gate work function adjustment method.

Contents of the invention

(1) Technical problems to be solved

In view of this, the main purpose of the present invention is to provide a new method for adjusting the gate work function of the metal gate, which is easy to integrate and has good compatibility with the CMOS process.

(2) Technical solutions

In order to achieve the above object, the present invention utilizes ion implantation technology to implant impurity gallium (Ga) into the polysilicon gate before silicide and activate the impurity, then deposit metal nickel (Ni) and carry out rapid thermal annealing (RTA) to make metal nickel and polysilicon completely The reaction forms a full silicide metal gate; at the same time, the full silicide process segregates the implanted gallium (Ga) to the vicinity of the full silicide gate/gate dielectric interface and causes accumulation, thereby adjusting the gate work function of the full silicide metal gate.

The specific technical scheme adopted is as follows:

A method for adjusting the gate work function of a metal gate, the method comprising:

Local oxidation isolation or shallow trench isolation, pre-implantation oxidation, and then implantation of ¹⁴ N ⁺ ;

Rinse the pre-implantation oxide film, gate oxide, and deposit polysilicon;

Photolithography and etching to form polysilicon gate electrodes;

Impurities are injected, and impurities are activated;

Deposit metal nickel, anneal silicide, make metal nickel and polysilicon completely react to form a full silicide metal gate;

Selective removal of unreacted nickel metal.

所述注入前氧化的步骤中，氧化厚度为100至所述注入¹⁴N⁺的步骤中，注入条件为：注入能量为10至35Kev，注入剂量为1×10¹⁴至8×10¹⁴cm^-2。In the above solution, in the step of local oxidation isolation or shallow trench isolation, the oxidation temperature is 1000°C, and the thickness of the isolation layer is 3000 to

In the step of oxidation before implantation, the oxidation thickness is 100 to In the step of implanting ¹⁴ N ⁺ , the implantation conditions are as follows: implantation energy is 10 to 35Kev, and implantation dose is 1×10 ¹⁴ to 8×10 ¹⁴ cm ⁻² .

In the above scheme, in the step of rinsing the oxide film before injection, rinse with a solution with a volume ratio of H ₂ O:HF=9:1, then use 3 ^# corrosion solution to clean for 10 minutes, and 1 ^# corrosion solution to clean for 5 minutes, immerse in HF/isopropanol IPA solution at room temperature for 5 minutes; the 3 ^# corrosion solution is a H ₂ SO ₄ and H ₂ O ₂ solution with a volume ratio of (3-5): 1; the 1 ^# corrosion solution is a volume NH ₄ OH+H ₂ O ₂ +H ₂ O solution with a ratio of (1～0.7):1:5; hydrofluoric acid/isopropanol/water is a volume ratio of 0.2% to 1:0.01% to 0.08:1 HF+IPA+H2O solution.

沉积多晶硅采用化学气相淀积LPCVD方法，沉积的多晶硅的厚度为1000至

In the above scheme, in the step of gate oxidation and polysilicon deposition, the thickness of the gate oxide is 15 to

Depositing polysilicon adopts chemical vapor deposition LPCVD method, and the thickness of deposited polysilicon is 1000 to

In the above scheme, before photolithography and etching to form the polysilicon gate electrode, it further includes: removing the back polysilicon, and bleaching the back oxide layer, and then performing back implantation, implanting impurities ³¹ P, the implantation energy is 50 to 100Kev, and the implantation dose 3×10 ¹⁵ to 6×10 ¹⁵ cm ^-2 .

In the above solution, the step of forming the polysilicon gate electrode in photolithography and etching includes: using 9918 glue with a thickness of 1.5 microns as a mask to perform photolithography, and using reactive ion etching to polysilicon to etch the polysilicon in the field area clean , forming a polysilicon gate electrode.

In the above solution, in the step of implanting impurities, the implanted impurity is gallium, and the impurity gallium is implanted into the polysilicon gate, the implantation energy is 50 to 150Kev, and the implantation dose is 1×10 ¹⁴ to 6×10 ¹⁵ cm ^-2 .

In the above scheme, in the step of impurity activation, the implanted impurity is activated by annealing, the annealing temperature is 950 to 1050° C., and the annealing time is 3 seconds to 10 seconds.

In the above scheme, in the step of depositing metallic nickel and annealing and siliciding, the thickness of deposited metallic nickel is 600 to The annealing conditions are: temperature 500-580° C., time 30-60 seconds.

In the above scheme, in the step of selectively removing unreacted metallic nickel, 3 ^# corrosive solution is used to remove unreacted metallic nickel by corrosion, and the 3 ^# corrosive solution is _H2SO with volume ratio (3-5): 1 ₄ with H ₂ O ₂ solution, the corrosion time is 20 to 30 minutes.

(3) Beneficial effects

The present invention uses ion implantation technology to implant impurity gallium (Ga) into the polysilicon gate before silicide, then deposits metal nickel (Ni) and performs rapid thermal annealing (RTA) to completely react the metal nickel and polysilicon to form a fully silicided metal gate; At the same time, the full silicide process segregates the implanted gallium (Ga) impurity near the fully silicided gate/gate dielectric interface and causes accumulation, thereby adjusting the gate work function of the fully silicided metal gate.

In addition, the method for adjusting the gate work function of the metal gate provided by the present invention is easy to integrate and has good compatibility with CMOS technology.

Description of drawings

1 is a flowchart of a method for adjusting the grid work function of a metal grid provided by the present invention;

Figure 2(a)-(e) are the preparation process steps of the metal gate of the present invention; wherein (a) is the structure formed after depositing polysilicon and photolithography and etching; (b) is a schematic diagram of impurity implantation; (c) is Schematic diagram after deposition of metal (Ni); (d) schematic diagram for silicide annealing reaction to generate (Ni) metal silicide gate electrode; (e) schematic diagram after selective removal of unreacted metal (Ni); symbol description in Fig. 1: 1-bulk silicon substrate, 2-gate oxide layer, 3-polysilicon gate electrode, 4-LOCOS isolation, 5-ion implanted elements, 6-deposited metal (Ni), 7-reaction-generated (Ni) metal silicide grid electrode;

Fig. 3 is the TEM picture of the metal grid electrode prepared by the present invention;

Fig. 4 is the CV characteristic curve of the capacitance prepared by the present invention.

Detailed ways

In order to make the object, technical solution and advantages of the present invention clearer, the present invention will be described in further detail below in conjunction with specific embodiments and with reference to the accompanying drawings.

As shown in Figure 1, Figure 1 is a flowchart of a method for adjusting the grid work function of a metal grid provided by the present invention, the method comprising:

Step 101: performing partial oxidation isolation or shallow trench isolation, performing pre-implantation oxidation, and then implanting ¹⁴ N ⁺ ;

注入前氧化的氧化厚度为100至注入¹⁴N⁺的注入条件为：注入能量为10至35Kev，注入剂量为1×10¹⁴至8×10¹⁴cm^-2。In this step, for partial oxidation isolation or shallow trench isolation, the oxidation temperature is 1000°C, and the thickness of the isolation layer is 3000 to

Oxidation thickness before implantation is 100 to The implantation conditions for implanting ¹⁴ N ⁺ are: the implantation energy is 10 to 35Kev, and the implantation dose is 1×10 ¹⁴ to 8×10 ¹⁴ cm ^-2 .

Step 102: rinsing the pre-implantation oxide film, gate oxidation, and depositing polysilicon;

沉积多晶硅采用化学气相淀积LPCVD方法，沉积的多晶硅的厚度为1000至

In this step, before rinsing and injection, the oxide film is rinsed with a solution with a volume ratio of H ₂ O:HF=9:1, and then cleaned with 3 ^# corrosion solution for 10 minutes, 1 ^# corrosion solution for 5 minutes, HF/isopropyl Immerse in alcohol IPA solution for 5 _minutes at room temperature; the 3 ^# corrosion solution is a _H2SO4 and _H2O2 solution with a volume ratio of (3-5): ₁ ; the 1 ^# corrosion solution is a volume ratio of (1-0.7 ): 1:5 NH ₄ OH+H ₂ O ₂ +H ₂ O solution; hydrofluoric acid/isopropanol/water is HF with a volume ratio of 0.2% to 1:% 0.01 to 0.08:1 +IPA+ _H2O solution. In the step of gate oxidation and deposition of polysilicon, the thickness of the gate oxide is 15 to

Depositing polysilicon adopts chemical vapor deposition LPCVD method, and the thickness of deposited polysilicon is 1000 to

Step 103: forming polysilicon gate electrodes by photolithography and etching;

In this step, the 9918 glue with a thickness of 1.5 microns is used as a mask for photolithography, and the polysilicon is etched by reactive ion etching to etch the polysilicon in the field area to form a polysilicon gate electrode.

Before photolithography and etching to form the polysilicon gate electrode, it further includes: removing the back polysilicon, and bleaching the back oxide layer, and then performing back implantation, implanting impurity ³¹ P, the implantation energy is 50 to 100Kev, and the implantation dose is 3×10 ¹⁵ to 6×10 ¹⁵ cm ^-2 .

Step 104: injecting impurities and activating the impurities;

In this step, the implanted impurity is gallium, and the impurity gallium is implanted into the polysilicon gate, the implantation energy is 50 to 150Kev, and the implantation dose is 1×10 ¹⁴ to 6×10 ¹⁵ cm ^-2 . Impurities are activated by annealing to activate the implanted impurities, and the annealing conditions are: temperature 950 to 1050° C., time 3 seconds to 10 seconds.

Step 105: Depositing metallic nickel, annealing and siliciding, allowing the metallic nickel and polysilicon to completely react to form a fully silicided metal gate;

退火条件为：温度500至580℃，时间30至60秒。In this step, the thickness of deposited nickel metal is 600 to

The annealing conditions are: temperature 500-580° C., time 30-60 seconds.

Step 106: Selectively remove unreacted nickel metal.

In this step, unreacted metal nickel is removed by corrosion with 3 ^# corrosion solution, _which is a _H2SO4 and _H2O2 solution with a volume ratio ^of (3-5): 1, and the corrosion _time is 20 to 30 minutes.

2(a)-(e) are the manufacturing process steps of the metal grid of the present invention. (a) is the structure formed after depositing polysilicon and photolithography and etching; (b) is a schematic diagram of impurity implantation; (c) is a schematic diagram after depositing metal (Ni); (d) is the formation of (Ni) by silicidation annealing reaction ) schematic diagram of metal silicide gate electrode; (e) schematic diagram after selective removal of unreacted metal (Ni). The process specifically includes the following steps:

Step 1: Field oxidation: 1000°C, 3000~

Step 2: Oxidation before injection: Thick

Step 3: injecting ¹⁴ N ⁺ , the energy is 10-35Kev, and the dose is 1×10 ¹⁴ cm ^-2 to 8×10 ¹⁴ cm ^-2 ;

Step 4: Rinse the oxide layer before injection: rinse in H ₂ O:HF=9:1 solution;

Step 5: Cleaning: Wash with 3 ^# liquid for 10 minutes, 1 ^# liquid for 5 minutes, HF/isopropanol (IPA), soak for 5 minutes at room temperature;

Step 6: Gate Oxidation: Thickness

Step 7: Chemical Vapor Deposition (LPCVD) Polysilicon:

Step 8: Remove the polysilicon on the back and rinse the oxide layer on the back;

Step 9: back implantation: impurity ³¹ P implantation, energy 50-100Kev, dose 3×10 ¹⁵ ~ 6×10 ¹⁵ ;

Step 10: Photolithography polysilicon: 9918 glue, 1.5 microns;

Step 11: Reactive ion etching polysilicon: the field area is etched clean polysilicon;

Step 12: Gate implantation: Impurity Ga implantation, implantation energy 50-150Kev, dose 1×10 ¹⁴ ~ 6×10 ¹⁵ cm ^-2 ;

Step 13: impurity activation: annealing temperature 950 to 1050°C, annealing time 3 seconds to 10 seconds;

Step 14: Sputtering Metallic Nickel (Ni): Thickness, 600-

Step 15: rapid thermal annealing (RTA): temperature 500-580°C, time 30-60 seconds;

Step 16: Selective corrosion: 3 ^# liquid (H ₂ SO ₄ : _{H 2} O ₂ =5:1), 20-30 minutes, to remove unreacted metallic nickel (Ni);

Fig. 3 is a TEM image of the metal gate electrode prepared by the present invention, from which it can be seen that the polysilicon gate electrode has completely transformed into a silicide metal gate electrode.

Fig. 4 is the CV characteristic curve of the electric capacity that utilizes the present invention to prepare, can find out from it that the CV curve shifts after impurity is implanted in the gate, and the change of flat-band voltage (V _fb ) reflects the change of the gate work function of the gate electrode; In the experimental range, the flat-band voltage of the capacitor after Ga injection has a maximum change of about 0.9V compared with the flat-band voltage of the undoped capacitor; through calculation, the work function can be adjusted to 4.989eV, which can meet the requirements of high-performance bulk silicon PMOS devices .

The specific embodiments described above have further described the purpose, technical solutions and beneficial effects of the present invention in detail. It should be understood that the above descriptions are only specific embodiments of the present invention and are not intended to limit the present invention. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present invention shall be included within the protection scope of the present invention.

Claims (9)

1. A method for adjusting the grid work function of a metal grid, characterized in that the method comprises: Local oxidation isolation or shallow trench isolation, pre-implantation oxidation, and then implantation of ¹⁴ N ⁺ ; Rinse the pre-implantation oxide film, gate oxide, and deposit polysilicon; Photolithography and etching to form polysilicon gate electrodes; Implanting impurities into the formed polysilicon gate electrode and activating the impurities; Deposit metal nickel, anneal silicide, make metal nickel and polysilicon completely react to form a full silicide metal gate; Selective removal of unreacted nickel metal; Wherein, in the step of oxidation before implantation, the oxidation thickness is 100 to

In the step of injecting ¹⁴ N ⁺ , the implantation conditions are as follows: the implantation energy is 10 to 35 KeV, and the implantation dose is 1×10 ¹⁴ to 8×10 ¹⁴ cm ⁻² ; In the step of rinsing the oxide film before injection, rinse with a solution with a volume ratio of H ₂ O:HF=9:1, then use 3 ^# corrosive solution for 10 minutes, 1 ^# corrosive solution for 5 minutes, HF/ Immerse in isopropanol IPA solution for 5 minutes at room temperature; the 3 ^# corrosion solution is a _H2SO4 and _H2O2 solution with a volume ratio _of (3-5): ₁ ; the 1 ^# corrosion solution is a volume ratio of (1 ~0.7):1:5 NH ₄ OH+H ₂ O ₂ +H ₂ O solution; hydrofluoric acid/isopropanol/water is 0.2% to 1% by volume: 0.01% to 0.08:1 HF+IPA+H ₂ O solution. 2. The method for adjusting the gate work function of a metal gate according to claim 1, characterized in that, in the step of local oxidation isolation or shallow trench isolation, the oxidation temperature is 1000°C, and the thickness of the isolation layer is 3000 to

3. The method for adjusting the gate work function of a metal gate according to claim 1, characterized in that, in the step of gate oxidation and polysilicon deposition, the thickness of the gate oxide is 15 to

Depositing polysilicon adopts chemical vapor deposition LPCVD method, and the thickness of deposited polysilicon is 1000 to 4. The method for adjusting the gate work function of the metal gate according to claim 1, wherein the method further comprises: before forming the polysilicon gate electrode by photolithography and etching: Removing the back polysilicon, and bleaching the back oxide layer, and then performing back implantation, implanting impurity ³¹ P, the implantation energy is 50 to 100Kev, and the implantation dose is 3×10 ¹⁵ to 6×10 ¹⁵ cm ^-2 . 5. The method for adjusting the gate work function of a metal gate according to claim 1, wherein the step of forming a polysilicon gate electrode by photolithography and etching comprises: The 9918 glue with a thickness of 1.5 microns is used as a mask for photolithography, and the polysilicon is etched by reactive ion etching to etch the polysilicon in the field area to form a polysilicon gate electrode. 6. The method for adjusting the gate work function of a metal gate according to claim 1, wherein in the step of implanting impurities into the formed polysilicon gate electrode, the implanted impurity is gallium, and the impurity gallium is injected into the polysilicon gate , the implantation energy is 50 to 150Kev, and the implantation dose is 1×10 ¹⁴ to 6×10 ¹⁵ cm ^-2 . 7. The method for adjusting the gate work function of a metal gate according to claim 1, characterized in that in the step of impurity activation, annealing is used to activate the implanted impurity, the annealing temperature is 950 to 1050°C, and the annealing time is 3 seconds to 10 Second. 8. The method for adjusting the gate work function of a metal gate according to claim 1, characterized in that, in the step of depositing metallic nickel and annealing and silicided, the thickness of deposited metallic nickel is 600 to

The annealing conditions are: temperature 500-580° C., time 30-60 seconds. 9. The method for adjusting the grid work function of the metal grid according to claim 1, characterized in that, in the step of selectively removing unreacted metal nickel, 3 ^# corrosion solution is used to remove unreacted metal nickel by corrosion, The 3 ^# etching solution is a solution of H ₂ SO ₄ and H ₂ O ₂ with a volume ratio of (3-5):1, and the etching time is 20 to 30 minutes.

Images